linux-kernel - Re: [PATCH 1/8] riscv: cpufeature: Add parsing for B

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Message-ID: <rbhjt6qmraoxsdur74mhl2ugy7orr2mb237ynq2sxrraqkl5zm@yc6kim3ic6as>
Date: Sun, 8 Feb 2026 10:43:09 -0600
From: Andrew Jones <andrew.jones@....qualcomm.com>
To: Guodong Xu <guodong@...cstar.com>
Cc: Paul Walmsley <pjw@...nel.org>, Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>, Alexandre Ghiti <alex@...ti.fr>,
        Jonathan Corbet <corbet@....net>,
        Shuah Khan <skhan@...uxfoundation.org>,
        Conor Dooley <conor@...nel.org>, linux-riscv@...ts.infradead.org,
        linux-kernel@...r.kernel.org, linux-doc@...r.kernel.org
Subject: Re: [PATCH 1/8] riscv: cpufeature: Add parsing for B

On Sat, Feb 07, 2026 at 06:27:55PM +0800, Guodong Xu wrote:
> The B extension comprises the Zba, Zbb, and Zbs extensions, as defined
> by version 20240411 of the RISC-V Instruction Set Manual Volume I
> Unprivileged Architecture.
> 
> Add B as a superset extension so that when "b" is encountered in the ISA
> string or devicetree, its sub-extensions are automatically enabled.
> 
> Signed-off-by: Guodong Xu <guodong@...cstar.com>
> ---
>  arch/riscv/include/asm/hwcap.h |  1 +
>  arch/riscv/kernel/cpufeature.c | 10 ++++++++++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index aa2af21f3bd32573558e964f94b32f9739f4c89f..35e87e4a8475a9201e84e7f9f8a4d10dfd9e4759 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -11,6 +11,7 @@
>  #include <uapi/asm/hwcap.h>
>  
>  #define RISCV_ISA_EXT_a		('a' - 'a')
> +#define RISCV_ISA_EXT_b		('b' - 'a')
>  #define RISCV_ISA_EXT_c		('c' - 'a')
>  #define RISCV_ISA_EXT_d		('d' - 'a')
>  #define RISCV_ISA_EXT_f		('f' - 'a')
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 63ad6393b2c6dcbfd6e7e247cf4bacb6c11fe58e..3d3af82a53250f29204a3fb138feaf520a878d0e 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -480,6 +480,15 @@ static const unsigned int riscv_supm_exts[] = {
>  	RISCV_ISA_EXT_SUPM
>  };
>  
> +/*
> + * The B extension comprises Zba, Zbb, and Zbs.
> + */
> +static const unsigned int riscv_b_exts[] = {
> +	RISCV_ISA_EXT_ZBA,
> +	RISCV_ISA_EXT_ZBB,
> +	RISCV_ISA_EXT_ZBS,
> +};
> +
>  /*
>   * The canonical order of ISA extension names in the ISA string is defined in
>   * Chapter 27 of the RISC-V Instruction Set Manual Volume I Unprivileged ISA
> @@ -528,6 +537,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
>  	__RISCV_ISA_EXT_DATA_VALIDATE(d, RISCV_ISA_EXT_d, riscv_ext_d_validate),
>  	__RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q),
>  	__RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_c, riscv_c_exts),
> +	__RISCV_ISA_EXT_SUPERSET(b, RISCV_ISA_EXT_b, riscv_b_exts),
>  	__RISCV_ISA_EXT_SUPERSET_VALIDATE(v, RISCV_ISA_EXT_v, riscv_v_exts, riscv_ext_vector_float_validate),
>  	__RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h),
>  	__RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xlinuxenvcfg_exts, riscv_ext_zicbom_validate),
> 
> -- 
> 2.43.0

Hi Guodong Xu,

As part of the "hwprobe: Introduce rva23u64 base behavior" RFC [1] I
posted a similar patch where I also added B to hwcap. Can you take a
look at that?

[1] https://lore.kernel.org/all/20260206002349.96740-1-andrew.jones@oss.qualcomm.com/

Thanks,
drew