linux-kernel - Re: [PATCH] arm64: dts: qcom: sm8550: Add UART15

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Message-ID: <73tz34sp7ojoyenzs7jnukcnxxgdykjp6uv5itep2kxr4prtpd@3ij654wkgsxx>
Date: Mon, 9 Feb 2026 00:20:43 +0200
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: webgeek1234@...il.com
Cc: Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>, linux-arm-msm@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        Xilin Wu <wuxilin123@...il.com>,
        Molly Sophia <mollysophia379@...il.com>,
        Dmitry Baryshkov <lumag@...nel.org>
Subject: Re: [PATCH] arm64: dts: qcom: sm8550: Add UART15

On Sat, Feb 07, 2026 at 08:18:17PM -0600, Aaron Kling via B4 Relay wrote:
> From: Xilin Wu <wuxilin123@...il.com>
> 
> Add uart15 node for UART bus present on sm8550 SoC.
> 
> Signed-off-by: Molly Sophia <mollysophia379@...il.com>
> Signed-off-by: Xilin Wu <wuxilin123@...il.com>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
> Signed-off-by: Aaron Kling <webgeek1234@...il.com>
> ---
> This patch was originally submitted as part of a series to support the
> AYN Odin 2 [0]. That series stalled, so submitting separately.
> 
> [0] https://lore.kernel.org/all/20240424-ayn-odin2-initial-v1-0-e0aa05c991fd@gmail.com/
> ---
>  arch/arm64/boot/dts/qcom/sm8550.dtsi | 24 ++++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index e3f93f4f412ded9583a6bc9215185a0daf5f1b57..ec172c22d928c4d73313c7b4980807760995ecaa 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -1251,6 +1251,22 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
>  				#size-cells = <0>;
>  				status = "disabled";
>  			};
> +
> +			uart15: serial@...000 {
> +				compatible = "qcom,geni-uart";
> +				reg = <0 0x89c000 0 0x4000>;
> +				clock-names = "se";
> +				clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&qup_uart15_default>;
> +				interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
> +				interconnects = <&clk_virt MASTER_QUP_CORE_2 0

QCOM_ICC_TAG_ALWAYS all over the place

> +						 &clk_virt SLAVE_QUP_CORE_2 0>,
> +						<&gem_noc MASTER_APPSS_PROC 0
> +						 &config_noc SLAVE_QUP_2 0>;
> +				interconnect-names = "qup-core", "qup-config";
> +				status = "disabled";
> +			};
>  		};
>  
>  		i2c_master_hub_0: geniqup@...000 {
> @@ -5095,6 +5111,14 @@ qup_uart14_cts_rts: qup-uart14-cts-rts-state {
>  				bias-pull-down;
>  			};
>  
> +			qup_uart15_default: qup-uart15-default-state {
> +				/* TX, RX */
> +				pins = "gpio74", "gpio75";
> +				function = "qup2_se7";
> +				drive-strength = <2>;
> +				bias-pull-up;
> +			};
> +
>  			sdc2_sleep: sdc2-sleep-state {
>  				clk-pins {
>  					pins = "sdc2_clk";
> 
> ---
> base-commit: 9845cf73f7db6094c0d8419d6adb848028f4a921
> change-id: 20260207-sm8550-uart15-9b7bd48e747d
> 
> Best regards,
> -- 
> Aaron Kling <webgeek1234@...il.com>
> 
> 

-- 
With best wishes
Dmitry