linux-kernel - Re: [PATCH RESEND 5/5] KVM: x86: selftests: Fix write MSR_TSC

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Message-ID: <aYoOHzwgxvpZ5Iso@google.com>
Date: Mon, 9 Feb 2026 08:41:03 -0800
From: Sean Christopherson <seanjc@...gle.com>
To: Zhiquan Li <zhiquan_li@....com>
Cc: pbonzini@...hat.com, shuah@...nel.org, kvm@...r.kernel.org, 
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH RESEND 5/5] KVM: x86: selftests: Fix write MSR_TSC_AUX
 reserved bits test failure on Hygon

On Mon, Feb 09, 2026, Zhiquan Li wrote:
> Therefore, the expectation of writing MSR_TSC_AUX reserved bits on Hygon
> CPUs should be:
> 1) either RDTSCP or RDPID is supported case, and both are supported
>    case, expect success and a truncated value, not #GP.
> 2) neither RDTSCP nor RDPID is supported, expect #GP.

That's how Intel and AMD behave as well.  I don't understand why there needs to
be a big pile of special case code for Hygon.  Presumably just fixup_rdmsr_val()
needs to be changed?

> Signed-off-by: Zhiquan Li <zhiquan_li@....com>
> ---
>  tools/testing/selftests/kvm/x86/msrs_test.c | 26 +++++++++++++++++----
>  1 file changed, 21 insertions(+), 5 deletions(-)
> 
> diff --git a/tools/testing/selftests/kvm/x86/msrs_test.c b/tools/testing/selftests/kvm/x86/msrs_test.c
> index 40d918aedce6..2f1e800fe691 100644
> --- a/tools/testing/selftests/kvm/x86/msrs_test.c
> +++ b/tools/testing/selftests/kvm/x86/msrs_test.c
> @@ -77,11 +77,11 @@ static bool ignore_unsupported_msrs;
>  static u64 fixup_rdmsr_val(u32 msr, u64 want)
>  {
>  	/*
> -	 * AMD CPUs drop bits 63:32 on some MSRs that Intel CPUs support.  KVM
> -	 * is supposed to emulate that behavior based on guest vendor model
> +	 * AMD and Hygon CPUs drop bits 63:32 on some MSRs that Intel CPUs support.
> +	 * KVM is supposed to emulate that behavior based on guest vendor model
>  	 * (which is the same as the host vendor model for this test).
>  	 */
> -	if (!host_cpu_is_amd)
> +	if (!host_cpu_is_amd && !host_cpu_is_hygon)
>  		return want;
>  
>  	switch (msr) {
> @@ -94,6 +94,17 @@ static u64 fixup_rdmsr_val(u32 msr, u64 want)
>  	}
>  }
>  
> +/*
> + * On Hygon processors either RDTSCP or RDPID is supported in the host,
> + * MSR_TSC_AUX is able to be accessed.
> + */
> +static bool is_hygon_msr_tsc_aux_supported(const struct kvm_msr *msr)
> +{
> +	return host_cpu_is_hygon &&
> +			msr->index == MSR_TSC_AUX &&
> +			(this_cpu_has(msr->feature) || this_cpu_has(msr->feature2));

Align indentation, but as above, this shouldn't be necessary.

> +}
> +
>  static void __rdmsr(u32 msr, u64 want)
>  {
>  	u64 val;
> @@ -174,9 +185,14 @@ void guest_test_reserved_val(const struct kvm_msr *msr)
>  	/*
>  	 * If the CPU will truncate the written value (e.g. SYSENTER on AMD),
>  	 * expect success and a truncated value, not #GP.
> +	 *
> +	 * On Hygon CPUs whether or not RDPID is supported in the host, once RDTSCP
> +	 * is supported, MSR_TSC_AUX is able to be accessed.  So, for either RDTSCP
> +	 * or RDPID is supported case and both are supported case, expect
> +	 * success and a truncated value, not #GP.
>  	 */
> -	if (!this_cpu_has(msr->feature) ||
> -	    msr->rsvd_val == fixup_rdmsr_val(msr->index, msr->rsvd_val)) {
> +	if (!is_hygon_msr_tsc_aux_supported(msr) && (!this_cpu_has(msr->feature) ||
> +	    msr->rsvd_val == fixup_rdmsr_val(msr->index, msr->rsvd_val))) {
>  		u8 vec = wrmsr_safe(msr->index, msr->rsvd_val);
>  
>  		__GUEST_ASSERT(vec == GP_VECTOR,
> -- 
> 2.43.0
>