linux-kernel - [PATCH 0/8] coresight: cti: Miscellaneous fixes and CPU PM cleanup

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Message-Id: <20260209-arm_coresight_cti_refactor_v1-v1-0-db71ab4d200b@arm.com>
Date: Mon, 09 Feb 2026 18:01:10 +0000
From: Leo Yan <leo.yan@....com>
To: Suzuki K Poulose <suzuki.poulose@....com>, 
 Mike Leach <mike.leach@....com>, James Clark <james.clark@...aro.org>, 
 Alexander Shishkin <alexander.shishkin@...ux.intel.com>, 
 Greg Kroah-Hartman <gregkh@...uxfoundation.org>, 
 Mathieu Poirier <mathieu.poirier@...aro.org>, 
 Tingwei Zhang <quic_tingwei@...cinc.com>, 
 Yingchao Deng <yingchao.deng@....qualcomm.com>, 
 Jie Gan <jie.gan@....qualcomm.com>
Cc: coresight@...ts.linaro.org, linux-arm-kernel@...ts.infradead.org, 
 linux-kernel@...r.kernel.org, Leo Yan <leo.yan@....com>
Subject: [PATCH 0/8] coresight: cti: Miscellaneous fixes and CPU PM cleanup

The CPU power management issue in the CTI driver was first observed in
series [1]; this series resolves that issue.  It fixes bugs and removes
CPU PM operations from the CoreSight CTI driver, the goal is to use the
CoreSight core layer as the central place for CPU power management.
Removing CPU PM from CTI driver can avoid conflicts with the core layer.

Based on review of the Arm ARM, ASICCTL is the only CTI register that
could potentially reside in the CPU power domain.  However, this is
considered highly unlikely for the following reasons:

 - Standard Arm CTIs place the ASICCTL register in the debug power
   domain;
 - ASICCTL is implemented only when CTIDEVID.EXTMUXNUM is non-zero,
   which is rare for CPU CTIs.

As a result, it is safe to remove the CPU PM code as done in this
series.  In addition, avoiding support local CPU access (via SMP calls)
to ASICCTL significantly reduces driver complexity.

If a future hardware implements ASICCTL in the CPU power domain, we can
consider adding a property to describe that characteristic.  That said,
from a software point of view, keeping all CTI registers in the same
power domain is preferable, as it makes the driver implementation much
simpler.

This series can be divided into:

  Patches 01 ~ 02: Fix spinlock with irqsave and register read with CS
                   lock.
  Patches 03 ~ 08: Access ASICCTL condintioanlly, remove CPU PM code,
                   and refactor register access in sysfs knob.

This series is based on coresight-next branch and has been validated on
Juno r1 and r2 platforms, pass normal sysfs and perf test, as well as
CPU PM stress testing.

[1] https://lore.kernel.org/all/20250915-arm_coresight_power_management_fix-v3-0-ea49e91124ec@arm.com/

Signed-off-by: Leo Yan <leo.yan@....com>
---
Leo Yan (8):
      coresight: cti: Make spinlock usage consistent
      coresight: cti: Fix register reads
      coresight: cti: Access ASICCTL only when implemented
      coresight: cti: Remove CPU power management code
      coresight: cti: Rename cti_active() to cti_is_active()
      coresight: cti: Remove hw_powered flag
      coresight: cti: Remove hw_enabled flag
      coresight: cti: Refactor cti_reg32_{show|store}()

 drivers/hwtracing/coresight/coresight-cti-core.c  | 278 ++++------------------
 drivers/hwtracing/coresight/coresight-cti-sysfs.c | 168 ++++++-------
 drivers/hwtracing/coresight/coresight-cti.h       |  13 +-
 3 files changed, 134 insertions(+), 325 deletions(-)
---
base-commit: eebe8dbd8630f51cf70b1f68a440cd3d7f7a914d
change-id: 20251223-arm_coresight_cti_refactor_v1-76e1bda8b716

Best regards,
-- 
Leo Yan <leo.yan@....com>