linux-kernel - RE: [PATCH] iommu/vt-d: fix intel iommu iotlb sync hardlockup & retry

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <BN9PR11MB5276CF1CB3BB86987AAFBCAC8C65A@BN9PR11MB5276.namprd11.prod.outlook.com>
Date: Mon, 9 Feb 2026 05:17:48 +0000
From: "Tian, Kevin" <kevin.tian@...el.com>
To: "guanghuifeng@...ux.alibaba.com" <guanghuifeng@...ux.alibaba.com>, "Baolu
 Lu" <baolu.lu@...ux.intel.com>, "dwmw2@...radead.org" <dwmw2@...radead.org>,
	"joro@...tes.org" <joro@...tes.org>, "will@...nel.org" <will@...nel.org>,
	"robin.murphy@....com" <robin.murphy@....com>, "iommu@...ts.linux.dev"
	<iommu@...ts.linux.dev>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>
CC: xunlei <xlpang@...ux.alibaba.com>
Subject: RE: [PATCH] iommu/vt-d: fix intel iommu iotlb sync hardlockup & retry

> From: guanghuifeng@...ux.alibaba.com <guanghuifeng@...ux.alibaba.com>
> Sent: Thursday, February 5, 2026 6:28 PM
> 
> There are a few points that need clarification:
> The descriptors between head and tail are requests that have not been
> fetched and executed.
> 
> 
> Regarding the requests before the head:
> Method 1: Does the IOMMU update the head address register immediately
> after fetching the descriptor?
> Method 2: Or does the IOMMU update the head register only after fetching
> and executing the request?
> 
> The current Intel IOMMU VT-d specification does not describe this
> behavior in detail.
> Does the IOMMU currently use Method 1?
> 

It's clearly documented in the VT-d spec, 6.5.2 Queued Invalidation
Interface:

"
Invalidation Queue Head Register: This register points to the invalidation
descriptor in the IQ that hardware will process next. The Invalidation
Queue Head register is incremented by hardware after fetching a valid
descriptor from the IQ.
"

"
Hardware implementations may fetch one or more descriptors together.
However, hardware must increment the Invalidation Queue Head Register
only after verifying the fetched descriptor to be valid.
"

the wait descriptor is for synchronizing with hardware completion.