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Message-ID: <aedfd0d8-271c-4b98-a826-a21f3a244a21@iscas.ac.cn>
Date: Mon, 9 Feb 2026 16:39:38 +0800
From: Vivian Wang <wangruikang@...as.ac.cn>
To: Hui Min Mina Chou <minachou@...estech.com>, pjw@...nel.org,
 palmer@...belt.com, aou@...s.berkeley.edu, alex@...ti.fr,
 linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Cc: tim609@...estech.com, ben717@...estech.com, az70021@...il.com,
 Charles Ci-Jyun Wu <dminus@...estech.com>
Subject: Re: [PATCH] riscv: fpu: refine FPU save flow

On 2/9/26 16:34, Vivian Wang wrote:
> [...]
>
> This doesn't really make sense. fstate_save checks for ((regs->status &
> SR_FS) == SR_FS_DIRTY). Do you mean that a platform can be !has_fpu(),
> yet come up with a task_pt_regs(...)->status that's SR_FS?

Meant to say: SR_FS set to SR_FS_DIRTY


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