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Message-ID: <ee886a80-0093-4c35-9701-427c2e166ca8@nvidia.com>
Date: Tue, 10 Feb 2026 17:10:56 +0000
From: Jon Hunter <jonathanh@...dia.com>
To: Manikanta Maddireddy <mmaddireddy@...dia.com>, bhelgaas@...gle.com,
lpieralisi@...nel.org, kwilczynski@...nel.org, mani@...nel.org,
robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
thierry.reding@...il.com, jingoohan1@...il.com, vidyas@...dia.com,
cassel@...nel.org, 18255117159@....com
Cc: linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [V5,03/13] PCI: tegra194: Don't force the device into the D0
state before L2
On 08/02/2026 18:07, Manikanta Maddireddy wrote:
> From: Vidya Sagar <vidyas@...dia.com>
>
> As per PCIe CEM spec rev 4.0 ver 1.0 sec 2.3, the PCIe endpoint device
> should be in D3 state to assert wake# pin. This takes precedence over PCI
> Express Base r4.0 v1.0 September 27-2017, 5.2 Link State Power Management
> which states that the device can be put into D0 state before taking the
> link to L2 state. So, to enable the wake functionality for endpoints, do
> not force the devices to D0 state before taking the link to L2 state.
> There is no functional issue with the endpoints where the link doesn't go
> into L2 state (the reason why the earlier change was made in the first
> place) as the root port proceeds with the usual flow post PME timeout.
>
> Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support")
> Signed-off-by: Vidya Sagar <vidyas@...dia.com>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@...dia.com>
> ---
> V5:
> * None
>
> V4:
> * None
>
> V3:
> * None
>
> V2:
> * None
For future reference, you can always just say ...
Changes V1 -> V5: None
Jon
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