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Message-ID: <87bjhw9ttp.ffs@tglx>
Date: Tue, 10 Feb 2026 22:23:14 +0100
From: Thomas Gleixner <tglx@...utronix.de>
To: Mukesh Rathor <mrathor@...ux.microsoft.com>,
linux-hyperv@...r.kernel.org, linux-kernel@...r.kernel.org
Cc: kys@...rosoft.com, haiyangz@...rosoft.com, wei.liu@...nel.org,
decui@...rosoft.com, longli@...rosoft.com, mingo@...hat.com, bp@...en8.de,
dave.hansen@...ux.intel.com, x86@...nel.org, hpa@...or.com
Subject: Re: [PATCH v1] x86/hyperv: Reserve 3 interrupt vectors used
exclusively by mshv
On Fri, Jan 02 2026 at 14:02, Mukesh Rathor wrote:
>
> +#ifndef CONFIG_X86_FRED
This #ifndef is broken. A FRED enabled kernel is no guarantee that the
CPU has FRED. So this has to be unconditional.
> + * Reserve vectors hard coded in the hypervisor. If used outside, the hypervisor
> + * will crash or hang or break into debugger.
> + */
> +static void hv_reserve_irq_vectors(void)
> +{
> + #define HYPERV_DBG_FASTFAIL_VECTOR 0x29
> + #define HYPERV_DBG_ASSERT_VECTOR 0x2C
> + #define HYPERV_DBG_SERVICE_VECTOR 0x2D
As FRED does not need this bit fiddling you want:
if (cpu_feature_enabled(X86_FEATURE_FRED))
return;
right here.
> + if (test_and_set_bit(HYPERV_DBG_ASSERT_VECTOR, system_vectors) ||
> + test_and_set_bit(HYPERV_DBG_SERVICE_VECTOR, system_vectors) ||
> + test_and_set_bit(HYPERV_DBG_FASTFAIL_VECTOR, system_vectors))
> + BUG();
> +
Thanks,
tglx
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