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Message-ID: <aYsurPBMnzWDZCco@shell.armlinux.org.uk>
Date: Tue, 10 Feb 2026 13:12:12 +0000
From: "Russell King (Oracle)" <linux@...linux.org.uk>
To: Joey Lu <a0987203069@...il.com>
Cc: andrew+netdev@...n.ch, davem@...emloft.net, edumazet@...gle.com,
kuba@...nel.org, pabeni@...hat.com, robh@...nel.org,
krzk+dt@...nel.org, conor+dt@...nel.org, mcoquelin.stm32@...il.com,
richardcochran@...il.com, alexandre.torgue@...s.st.com,
joabreu@...opsys.com, ychuang3@...oton.com, schung@...oton.com,
yclu4@...oton.com, peppe.cavallaro@...com,
linux-arm-kernel@...ts.infradead.org, netdev@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
openbmc@...ts.ozlabs.org, linux-stm32@...md-mailman.stormreply.com,
Andrew Lunn <andrew@...n.ch>
Subject: Re: [PATCH net-next v12 3/3] net: stmmac: dwmac-nuvoton: Add dwmac
glue for Nuvoton MA35 family
Please note that net-next is currently closed, so you should be sending
net-next patches with "RFC". See section 1.4 of:
https://docs.kernel.org/process/maintainer-netdev.html
On Tue, Feb 10, 2026 at 01:22:26PM +0800, Joey Lu wrote:
> +static int nvt_gmac_setup(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + phy_interface_t phy_mode;
> + struct regmap *regmap;
> + u32 macid, miscr, reg;
> + int ret;
> +
> + regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node, "nuvoton,sys", 1, &macid);
> + if (IS_ERR(regmap))
> + ret = dev_err_probe(dev, PTR_ERR(regmap), "Failed to get sys register\n");
> +
> + if (macid > 1)
> + ret = dev_err_probe(dev, -EINVAL, "Invalid sys arguments\n");
> +
> + if (of_get_phy_mode(pdev->dev.of_node, &phy_mode))
> + ret = dev_err_probe(dev, -EINVAL, "Missing phy mode property\n");
If you pass in the plat_dat to this function, then you have access to
plat_dat->phy_interface. I went through all the dwmac glue code and
removed such PHY interface gets, so please don't introduce new
instances.
> +
> + miscr = (macid == 0) ? NVT_REG_SYS_GMAC0MISCR : NVT_REG_SYS_GMAC1MISCR;
I find the use of "miscr" to be the register offset, and "reg" to be
the register value is confusing. Normally they're the other way around.
> +
> + switch (phy_mode) {
> + case PHY_INTERFACE_MODE_RGMII:
> + case PHY_INTERFACE_MODE_RGMII_ID:
> + case PHY_INTERFACE_MODE_RGMII_RXID:
> + case PHY_INTERFACE_MODE_RGMII_TXID:
> + ret = nvt_gmac_get_delay(dev, "rx-internal-delay-ps");
> + if (ret < 0)
> + return ret;
> + reg = FIELD_PREP(NVT_RX_DELAY_MASK, ret);
> +
> + ret = nvt_gmac_get_delay(dev, "tx-internal-delay-ps");
> + if (ret < 0)
> + return ret;
> + reg |= FIELD_PREP(NVT_TX_DELAY_MASK, ret);
> + break;
> + case PHY_INTERFACE_MODE_RMII:
> + reg = NVT_MISCR_RMII;
> + break;
> + default:
> + return dev_err_probe(dev, -EINVAL, "Unsupported phy-mode (%d)\n", phy_mode);
> + }
> +
> + regmap_update_bits(regmap, miscr,
> + NVT_RX_DELAY_MASK | NVT_TX_DELAY_MASK | NVT_MISCR_RMII, reg);
Please consider programming the NVT_MISCR_RMII bit via the
plat_dat->set_phy_intf_sel() method.
Is this register preserved over suspend/resume ?
Thanks.
--
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