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Message-ID: <1a36b013-ae9b-4d51-8259-92728644ceab@lunn.ch>
Date: Tue, 10 Feb 2026 14:47:31 +0100
From: Andrew Lunn <andrew@...n.ch>
To: javen <javen_xu@...lsil.com.cn>
Cc: hkallweit1@...il.com, nic_swsd@...ltek.com, andrew+netdev@...n.ch,
davem@...emloft.net, edumazet@...gle.com, kuba@...nel.org,
pabeni@...hat.com, horms@...nel.org, netdev@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH net-next v4] r8169: add support for RTL8125cp
On Tue, Feb 10, 2026 at 03:11:34PM +0800, javen wrote:
> From: Javen Xu <javen_xu@...lsil.com.cn>
>
> This patch adds support for chip RTL8125cp. Its XID is 0x708. We apply
> different and firmware for RTL8125cp.
>
> Signed-off-by: Javen Xu <javen_xu@...lsil.com.cn>
>
> ---
> v2: This patch fix one mistake on phy_modify_paged(phydev, 0xa43, 0x10,
> 0x0000, 0x1001) which is phy_modify_paged(phydev, 0xa43, 0x00, 0x0000, 0x1001) on patch v1.
>
> v3: Set phy_modify_paged(phydev, 0xa43, 0x10, 0x0000, 0x0003), bit 0
> means 'link speed 10m PLL OFF', bit 1 means 'ALDPS PLL OFF', bit 2 means
> 'ENABLE ALDPS', bit 12 means 'ALDPS XTAL OFF'.
If you know what these bits mean, why not add
#define RTL8125CP_LINK_SPEED_10M_PLL_OFF BIT(0)
#define RTL8125CP_ALDPS_PLL_OFF BIT(1)
etc.
Andrew
---
pw-bot: cr
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