linux-kernel - Re: [RFC PATCH 00/19] x86,fs/resctrl: Support for Global Bandwidth Enforcement and Priviledge Level Zero Association

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <aYvP98xGoKPrDBCE@gen8>
Date: Tue, 10 Feb 2026 16:40:23 -0800
From: Drew Fustini <fustini@...nel.org>
To: Reinette Chatre <reinette.chatre@...el.com>
Cc: "Luck, Tony" <tony.luck@...el.com>, Babu Moger <babu.moger@....com>,
	James Morse <james.morse@....com>,
	Dave Martin <Dave.Martin@....com>, Ben Horgan <ben.horgan@....com>,
	corbet@....net, tglx@...nel.org, mingo@...hat.com, bp@...en8.de,
	dave.hansen@...ux.intel.com, x86@...nel.org, hpa@...or.com,
	peterz@...radead.org, juri.lelli@...hat.com,
	vincent.guittot@...aro.org, dietmar.eggemann@....com,
	rostedt@...dmis.org, bsegall@...gle.com, mgorman@...e.de,
	vschneid@...hat.com, akpm@...ux-foundation.org,
	pawan.kumar.gupta@...ux.intel.com, pmladek@...e.com,
	feng.tang@...ux.alibaba.com, kees@...nel.org, arnd@...db.de,
	fvdl@...gle.com, lirongqing@...du.com, bhelgaas@...gle.com,
	seanjc@...gle.com, xin@...or.com, manali.shukla@....com,
	dapeng1.mi@...ux.intel.com, chang.seok.bae@...el.com,
	mario.limonciello@....com, naveen@...nel.org,
	elena.reshetova@...el.com, thomas.lendacky@....com,
	linux-doc@...r.kernel.org, linux-kernel@...r.kernel.org,
	kvm@...r.kernel.org, peternewman@...gle.com, eranian@...gle.com,
	gautham.shenoy@....com
Subject: Re: [RFC PATCH 00/19] x86,fs/resctrl: Support for Global Bandwidth
 Enforcement and Priviledge Level Zero Association

On Mon, Feb 09, 2026 at 04:27:47PM -0800, Reinette Chatre wrote:
> Adding Ben
> 
> On 2/3/26 11:58 AM, Luck, Tony wrote:
> > On Wed, Jan 21, 2026 at 03:12:38PM -0600, Babu Moger wrote:
> >> Privilege Level Zero Association (PLZA) 
> >>
> >> Privilege Level Zero Association (PLZA) allows the hardware to
> >> automatically associate execution in Privilege Level Zero (CPL=0) with a
> >> specific COS (Class of Service) and/or RMID (Resource Monitoring
> >> Identifier). The QoS feature set already has a mechanism to associate
> >> execution on each logical processor with an RMID or COS. PLZA allows the
> >> system to override this per-thread association for a thread that is
> >> executing with CPL=0. 
> > 
> > Adding Drew, and prodding Dave & James, for this discussion.
> > 
> > At LPC it was stated that both ARM and RISC-V already have support
> > to run kernel code with different quality of service parameters from
> > user code.

Sorry, for RISC-V, I should clarify that there is no hardware feature
that changes the QoS identifier value when switching between kernel mode
and user mode. This could be done in the kernel task switching code, but
there is no implicit hardware operation.

Thanks,
Drew