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Message-Id: <20061128.144911.55733883.davem@davemloft.net>
Date: Tue, 28 Nov 2006 14:49:11 -0800 (PST)
From: David Miller <davem@...emloft.net>
To: eric.lemoine@...il.com
Cc: netdev@...r.kernel.org, benh@...nel.crashing.org
Subject: Re: [patch sungem] improved locking
From: "Eric Lemoine" <eric.lemoine@...il.com>
Date: Tue, 14 Nov 2006 22:54:40 +0100
> On 11/14/06, David Miller <davem@...emloft.net> wrote:
> > From: "Eric Lemoine" <eric.lemoine@...il.com>
> > Date: Tue, 14 Nov 2006 08:28:42 +0100
> >
> > > because it makes it explicit that only bits 0 through 6 are taken into
> > > account when writing the IACK register.
> >
> > The phrase "bits 0 through 6" doesn't make any sense when bit 3 DOES
> > NOT EXIST in the hardware, it's reserved, it's not there, so including
> > it only confuses people and obfuscates the code.
> >
> > Please use the explicit bit mask composed of existing macros, which
> > not only makes sure that the mask has meaning, but it also makes sure
> > that reserved and non-existing bits are never referenced.
>
> Patch attached.
>
> Remember, the GEM_INTERRUPT_LOCKLESS isn't there to stay. It's
> currently there because I'm not sure the lockless implementation of
> gem_interrupt() will work with poll_net_controller.
>
> Thanks,
>
> Signed-off-by: Eric Lemoine <eric.lemoine@...il.com>
This looks mostly fine.
I was thinking about the lockless stuff, and I wonder if there
is a clever way you can get it back down to one PIO on the
GREG_STAT register.
I think you'd need to have the ->poll() clear gp->status, then
do a smp_wb(), right before it re-enables interrupts.
Then in the interrupt handler, you need to find a way to safely
OR-in any unset bits in gp->status in a race-free manner.
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