netdev - [PATCH] sky2: receive queue watermark tweak

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Message-ID: <20061204170819.6d7c85e6@localhost>
Date:	Mon, 4 Dec 2006 17:08:19 -0800
From:	Stephen Hemminger <shemminger@...l.org>
To:	Jeff Garzik <jgarzik@...ox.com>
Cc:	netdev@...r.kernel.org
Subject: [PATCH] sky2: receive queue watermark tweak

This patch makes the receive performance on some systems go from
714MB/s to 941MB/s. It adjusts the watermark of the receive queue
to be lower, thereby avoiding excess hardware flow control. This is
most important on the systems which have little/no additional buffering.

Signed-off-by: Stephen Hemminger <shemminger@...l.org>


---
 drivers/net/sky2.c |   11 ++++++++---
 drivers/net/sky2.h |    1 +
 2 files changed, 9 insertions(+), 3 deletions(-)

--- sky2.orig/drivers/net/sky2.c	2006-12-04 16:53:22.000000000 -0800
+++ sky2/drivers/net/sky2.c	2006-12-04 17:03:51.000000000 -0800
@@ -1062,11 +1062,16 @@
 	sky2->rx_put = sky2->rx_next = 0;
 	sky2_qset(hw, rxq);
 
+	/* On PCI express lowering the watermark gives better performance */
+	if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
+		sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
+
+	/* These chips have no ram buffer?
+	 * MAC Rx RAM Read is controlled by hardware */
 	if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
-	    (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0)) {
-		/* MAC Rx RAM Read is controlled by hardware */
+	    (hw->chip_rev == CHIP_REV_YU_EC_U_A1
+	     || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
 		sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
-	}
 
 	sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
 
--- sky2.orig/drivers/net/sky2.h	2006-12-04 16:56:24.000000000 -0800
+++ sky2/drivers/net/sky2.h	2006-12-04 17:01:05.000000000 -0800
@@ -680,6 +680,7 @@
 			  BMU_FIFO_ENA | BMU_OP_ON,
 
 	BMU_WM_DEFAULT = 0x600,
+	BMU_WM_PEX     = 0x80,
 };
 
 /* Tx BMU Control / Status Registers (Yukon-2) */
-
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