netdev - RE: [PATCH] chelsio 10G (T1/T2)

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Message-ID: <8A71B368A89016469F72CD08050AD334E71FD4@maui.asicdesigners.com>
Date:	Tue, 5 Dec 2006 12:01:59 -0800
From:	"Felix Marti" <felix@...lsio.com>
To:	"Stephen Hemminger" <shemminger@...l.org>
Cc:	<netdev@...r.kernel.org>
Subject: RE: [PATCH] chelsio 10G (T1/T2)



> -----Original Message-----
> From: Stephen Hemminger [mailto:shemminger@...l.org]
> Sent: Tuesday, December 05, 2006 11:59 AM
> To: Felix Marti
> Cc: netdev@...r.kernel.org
> Subject: Re: [PATCH] chelsio 10G (T1/T2)
> 
> On Tue, 5 Dec 2006 10:53:10 -0800
> "Felix Marti" <felix@...lsio.com> wrote:
> 
> > T1's and T2's implementation of MSI has a bug. I believe to remember
> > that it
> >
> > works with some chipsets but we should disable MSI by default.
> 
> 
> Is this really the platform bug, if so it should be handled by the pci
quirks
> already. Or is this a Chelsio hardware bug?
[Felix Marti] Chelsio T1 and T2 hardware bug. - T3 works with MSI as
well as MSI-X.

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