netdev - Re: NAPI and shared interrupt control

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Date:	Thu, 07 Dec 2006 01:16:27 -0800 (PST)
From:	David Miller <davem@...emloft.net>
To:	benh@...nel.crashing.org
Cc:	netdev@...r.kernel.org, ebs@...home.net
Subject: Re: NAPI and shared interrupt control

From: Benjamin Herrenschmidt <benh@...nel.crashing.org>
Date: Thu, 07 Dec 2006 15:24:06 +1100

> 
> > What Eugene does currently, which seems to me like it's actually the
> > only proper solution, is to create a separate net_device structure for
> > the DMA engine and thus have a single NAPI poll & weighting for all the
> > EMACs sharing a given MAL (MAL is the name of that DMA engine). This
> > means that Rx from any of the channels schedules the poll, and
> > interrupts can be properly masked/unmasked globally based on the
> > presence/absence of work on all the channels.
> 
> Actually, another solution would be to have one of the instances do the
> NAPI poll for all of them instead of creating a separate net_device for
> the DMA engine...

I think this idea would work the best.

Just link the other related devices into a list in the driver private
struct.  Or a simple "work pending" bitmask for each of the EMACs,
which tell the primary EMAC netdev which devices should be polled.

This architecture doesn't make things easy, that's for sure :-)

If things get too hairy, don't feel too bad about ideas like forgoing
NAPI altogether and just using the interrupt mitigation features of
the chip.  Does it have any?

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