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Date:	Mon, 25 Jun 2007 13:16:44 -0400
From:	jamal <hadi@...erus.ca>
To:	Benjamin LaHaise <bcrl@...ck.org>
Cc:	David Miller <davem@...emloft.net>, Robert.Olsson@...a.slu.se,
	johnpol@....mipt.ru, krkumar2@...ibm.com, gaagaan@...il.com,
	netdev@...r.kernel.org, rick.jones2@...com, sri@...ibm.com
Subject: Re: FSCKED clock sources WAS(Re: [WIP][PATCHES] Network xmit
	batching

On Mon, 2007-25-06 at 13:08 -0400, Benjamin LaHaise wrote:

> CPUID:
> 
> vendor_id       : GenuineIntel
> cpu family      : 15
> model           : 4
> model name      : Intel(R) Xeon(TM) CPU 2.80GHz
> 
> shows that it is a P4 Xeon, which sucks compared to:
> 
> vendor_id       : GenuineIntel
> cpu family      : 6
> model           : 15
> model name      : Genuine Intel(R) CPU                  @ 2.66GHz
> 
> which is a Core 2 based Xeon. 

Ok. Should the model name at least reflect one being a Xeon P4 and other
as core2 Xeon? ;->
 
>  The tuning required by the P4 is quite 
> different than the Core 2, and it generally performs more poorly due to 
> the length of the pipeline and the expense of pipeline flushes.

I would be very interested to see some numbers on a proper Core2 based
Xeon (unfortunately cant afford one). You have the hardware, what says
you? ;->
AFAIT, the main reason Opterons has the numbers it does is due to 
the integrated on chip MC. I dont see Intel any time soon getting rid of
that (for economical reasons more than technical).
In any case i see batching as actually being a lot more cache friendly
too.

cheers,
jamal 

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