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Message-ID: <20070821000518.GC7292@linux.vnet.ibm.com> Date: Mon, 20 Aug 2007 17:05:18 -0700 From: "Paul E. McKenney" <paulmck@...ux.vnet.ibm.com> To: Segher Boessenkool <segher@...nel.crashing.org> Cc: Russell King <rmk+lkml@....linux.org.uk>, Christoph Lameter <clameter@....com>, Paul Mackerras <paulus@...ba.org>, heiko.carstens@...ibm.com, horms@...ge.net.au, linux-kernel@...r.kernel.org, ak@...e.de, netdev@...r.kernel.org, cfriesen@...tel.com, akpm@...ux-foundation.org, rpjday@...dspring.com, Nick Piggin <nickpiggin@...oo.com.au>, linux-arch@...r.kernel.org, jesper.juhl@...il.com, satyam@...radead.org, zlynx@....org, schwidefsky@...ibm.com, Chris Snook <csnook@...hat.com>, Herbert Xu <herbert@...dor.apana.org.au>, davem@...emloft.net, Linus Torvalds <torvalds@...ux-foundation.org>, wensong@...ux-vs.org, wjiang@...ilience.com Subject: Re: [PATCH 0/24] make atomic_read() behave consistently across all architectures On Tue, Aug 21, 2007 at 01:02:01AM +0200, Segher Boessenkool wrote: > >>And no, RMW on MMIO isn't "problematic" at all, either. > >> > >>An RMW op is a read op, a modify op, and a write op, all rolled > >>into one opcode. But three actual operations. > > > >Maybe for some CPUs, but not all. ARM for instance can't use the > >load exclusive and store exclusive instructions to MMIO space. > > Sure, your CPU doesn't have RMW instructions -- how to emulate > those if you don't have them is a totally different thing. I thought that ARM's load exclusive and store exclusive instructions were its equivalent of LL and SC, which RISC machines typically use to build atomic sequences of instructions -- and which normally cannot be applied to MMIO space. Thanx, Paul - To unsubscribe from this list: send the line "unsubscribe netdev" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
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