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Date:	Sun, 07 Oct 2007 18:23:18 +0200
From:	"Eliezer Tamir" <eliezert@...adcom.com>
To:	davem@...emloft.net, jeff@...zik.org,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	"Michael Chan" <mchan@...adcom.com>
Subject: [BNX2X][PATCH 4/8] bnx2x_hsi.h

bnx2x_hsi.h - machine generated headers defining HW and Micorocode 
constants.

Signed-off-by: Eliezer Tamir <eliezert@...adcom.com 
<mailto:eliezert@...adcom.com>>
---
drivers/net/bnx2x_hsi.h | 7086 
+++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 7066 insertions(+), 0 deletions(-)

diff --git a/drivers/net/bnx2x_hsi.h b/drivers/net/bnx2x_hsi.h
new file mode 100644
index 0000000..21eea48
--- /dev/null
+++ b/drivers/net/bnx2x_hsi.h
@@ -0,0 +1,7086 @@
+/* bnx2x_hsi.h: Broadcom Everest network driver.
+ *
+ * Copyright (c) 2007 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation.
+ *
+ */
+
+/* Machine generated - do not edit */
+
+#define BRB1_REGISTERS_BRB1_INT_STS 0x11cUL
+#define BRB1_REGISTERS_BRB1_INT_STS_CLR 0x120UL
+#define BRB1_REGISTERS_BRB1_INT_STS_WR 0x124UL
+#define BRB1_REGISTERS_FREE_LIST_PRS_CRDT 0x200UL
+#define BRB1_REGISTERS_FREE_LIST_PRS_CRDT_SIZE 3
+#define BRB1_REGISTERS_LL_RAM 0x1000UL
+#define BRB1_REGISTERS_LL_RAM_SIZE 512
+#define BRB1_REGISTERS_NUM_OF_FULL_BLOCKS 0x90UL
+#define BRB1_REGISTERS_NUM_OF_FULL_CYCLES_0 0xc8UL
+#define BRB1_REGISTERS_NUM_OF_FULL_CYCLES_1 0xccUL
+#define BRB1_REGISTERS_NUM_OF_FULL_CYCLES_2 0xd0UL
+#define BRB1_REGISTERS_NUM_OF_FULL_CYCLES_3 0xd4UL
+#define BRB1_REGISTERS_NUM_OF_FULL_CYCLES_4 0xd8UL
+#define BRB1_REGISTERS_NUM_OF_PAUSE_CYCLES_0 0xb8UL
+#define BRB1_REGISTERS_NUM_OF_PAUSE_CYCLES_1 0xbcUL
+#define BRB1_REGISTERS_NUM_OF_PAUSE_CYCLES_2 0xc0UL
+#define BRB1_REGISTERS_NUM_OF_PAUSE_CYCLES_3 0xc4UL
+#define BRB1_REGISTERS_PAUSE_HIGH_THRESHOLD_0 0x78UL
+#define BRB1_REGISTERS_PAUSE_HIGH_THRESHOLD_1 0x7cUL
+#define BRB1_REGISTERS_PAUSE_LOW_THRESHOLD_0 0x68UL
+#define BRB1_REGISTERS_PAUSE_LOW_THRESHOLD_1 0x6cUL
+#define BRB1_REGISTERS_SOFT_RESET 0xdcUL
+#define CCM_REGISTERS_CAM_OCCUP 0x188UL
+#define CCM_REGISTERS_CAM_OCCUP_ST 0x200UL
+#define CCM_REGISTERS_CAM_OCCUP_ST_SIZE 1
+#define CCM_REGISTERS_CCM_CFC_IFEN 0x3cUL
+#define CCM_REGISTERS_CCM_CQM_IFEN 0xcUL
+#define CCM_REGISTERS_CCM_CQM_USE_Q 0xc0UL
+#define CCM_REGISTERS_CCM_INT_STS 0x1d8UL
+#define CCM_REGISTERS_CCM_INT_STS_CLR 0x1dcUL
+#define CCM_REGISTERS_CCM_INT_STS_WR 0x1e0UL
+#define CCM_REGISTERS_CCM_REG0_SZ 0xc4UL
+#define CCM_REGISTERS_CCM_STORM0_IFEN 0x4UL
+#define CCM_REGISTERS_CCM_STORM1_IFEN 0x8UL
+#define CCM_REGISTERS_CDU_AG_RD_IFEN 0x30UL
+#define CCM_REGISTERS_CDU_AG_WR_IFEN 0x2cUL
+#define CCM_REGISTERS_CDU_SM_RD_IFEN 0x38UL
+#define CCM_REGISTERS_CDU_SM_WR_IFEN 0x34UL
+#define CCM_REGISTERS_CFC_INIT_CRD 0x204UL
+#define CCM_REGISTERS_CFC_INIT_CRD_SIZE 1
+#define CCM_REGISTERS_CNT_AUX1_Q 0xc8UL
+#define CCM_REGISTERS_CNT_AUX2_Q 0xccUL
+#define CCM_REGISTERS_CP_WEIGHT 0xb0UL
+#define CCM_REGISTERS_CQM_CCM_HDR_P 0x8cUL
+#define CCM_REGISTERS_CQM_CCM_HDR_S 0x90UL
+#define CCM_REGISTERS_CQM_CCM_IFEN 0x14UL
+#define CCM_REGISTERS_CQM_INIT_CRD 0x20cUL
+#define CCM_REGISTERS_CQM_INIT_CRD_SIZE 1
+#define CCM_REGISTERS_CQM_P_WEIGHT 0xb8UL
+#define CCM_REGISTERS_CSDM_IFEN 0x18UL
+#define CCM_REGISTERS_CSDM_LENGTH_MIS 0x170UL
+#define CCM_REGISTERS_ERR_CCM_HDR 0x94UL
+#define CCM_REGISTERS_ERR_EVNT_ID 0x98UL
+#define CCM_REGISTERS_FIC0_INIT_CRD 0x210UL
+#define CCM_REGISTERS_FIC0_INIT_CRD_SIZE 1
+#define CCM_REGISTERS_FIC1_INIT_CRD 0x214UL
+#define CCM_REGISTERS_FIC1_INIT_CRD_SIZE 1
+#define CCM_REGISTERS_GR_ARB_TYPE 0x15cUL
+#define CCM_REGISTERS_GR_LD0_PR 0x164UL
+#define CCM_REGISTERS_GR_LD1_PR 0x168UL
+#define CCM_REGISTERS_INV_DONE_Q 0x108UL
+#define CCM_REGISTERS_N_SM_CTX_LD_0 0x4cUL
+#define CCM_REGISTERS_N_SM_CTX_LD_1 0x50UL
+#define CCM_REGISTERS_N_SM_CTX_LD_10 0x74UL
+#define CCM_REGISTERS_N_SM_CTX_LD_11 0x78UL
+#define CCM_REGISTERS_N_SM_CTX_LD_12 0x7cUL
+#define CCM_REGISTERS_N_SM_CTX_LD_13 0x80UL
+#define CCM_REGISTERS_N_SM_CTX_LD_14 0x84UL
+#define CCM_REGISTERS_N_SM_CTX_LD_15 0x88UL
+#define CCM_REGISTERS_N_SM_CTX_LD_2 0x54UL
+#define CCM_REGISTERS_N_SM_CTX_LD_3 0x58UL
+#define CCM_REGISTERS_N_SM_CTX_LD_4 0x5cUL
+#define CCM_REGISTERS_N_SM_CTX_LD_5 0x60UL
+#define CCM_REGISTERS_N_SM_CTX_LD_6 0x64UL
+#define CCM_REGISTERS_N_SM_CTX_LD_7 0x68UL
+#define CCM_REGISTERS_PBF_IFEN 0x28UL
+#define CCM_REGISTERS_PBF_LENGTH_MIS 0x180UL
+#define CCM_REGISTERS_PBF_WEIGHT 0xacUL
+#define CCM_REGISTERS_PHYS_QNUM1_0 0x134UL
+#define CCM_REGISTERS_PHYS_QNUM1_1 0x138UL
+#define CCM_REGISTERS_PHYS_QNUM2_0 0x13cUL
+#define CCM_REGISTERS_PHYS_QNUM2_1 0x140UL
+#define CCM_REGISTERS_PHYS_QNUM3_0 0x144UL
+#define CCM_REGISTERS_PHYS_QNUM3_1 0x148UL
+#define CCM_REGISTERS_QOS_PHYS_QNUM0_0 0x114UL
+#define CCM_REGISTERS_QOS_PHYS_QNUM0_1 0x118UL
+#define CCM_REGISTERS_QOS_PHYS_QNUM1_0 0x11cUL
+#define CCM_REGISTERS_QOS_PHYS_QNUM1_1 0x120UL
+#define CCM_REGISTERS_QOS_PHYS_QNUM2_0 0x124UL
+#define CCM_REGISTERS_QOS_PHYS_QNUM2_1 0x128UL
+#define CCM_REGISTERS_QOS_PHYS_QNUM3_0 0x12cUL
+#define CCM_REGISTERS_QOS_PHYS_QNUM3_1 0x130UL
+#define CCM_REGISTERS_STORM_CCM_IFEN 0x10UL
+#define CCM_REGISTERS_STORM_LENGTH_MIS 0x16cUL
+#define CCM_REGISTERS_TSEM_IFEN 0x1cUL
+#define CCM_REGISTERS_TSEM_LENGTH_MIS 0x174UL
+#define CCM_REGISTERS_TSEM_WEIGHT 0xa0UL
+#define CCM_REGISTERS_USEM_IFEN 0x24UL
+#define CCM_REGISTERS_USEM_LENGTH_MIS 0x17cUL
+#define CCM_REGISTERS_USEM_WEIGHT 0xa8UL
+#define CCM_REGISTERS_XSEM_IFEN 0x20UL
+#define CCM_REGISTERS_XSEM_LENGTH_MIS 0x178UL
+#define CCM_REGISTERS_XSEM_WEIGHT 0xa4UL
+#define CCM_REGISTERS_XX_DESCR_TABLE 0x300UL
+#define CCM_REGISTERS_XX_DESCR_TABLE_SIZE 36
+#define CCM_REGISTERS_XX_INIT_CRD 0x220UL
+#define CCM_REGISTERS_XX_INIT_CRD_SIZE 1
+#define CCM_REGISTERS_XX_MSG_NUM 0x224UL
+#define CCM_REGISTERS_XX_MSG_NUM_SIZE 1
+#define CCM_REGISTERS_XX_OVFL_EVNT_ID 0x44UL
+#define CCM_REGISTERS_XX_TABLE 0x280UL
+#define CCM_REGISTERS_XX_TABLE_SIZE 18
+#define CDU_REGISTERS_CDU_CHK_MASK0 0x0UL
+#define CDU_REGISTERS_CDU_CHK_MASK1 0x4UL
+#define CDU_REGISTERS_CDU_CONTROL0 0x8UL
+#define CDU_REGISTERS_CDU_GLOBAL_PARAMS 0x20UL
+#define CDU_REGISTERS_CDU_INT_STS 0x30UL
+#define CDU_REGISTERS_CDU_INT_STS_CLR 0x34UL
+#define CDU_REGISTERS_CDU_INT_STS_WR 0x38UL
+#define CDU_REGISTERS_ERROR_DATA 0x14UL
+#define CDU_REGISTERS_L1TT 0x800UL
+#define CDU_REGISTERS_L1TT_SIZE 512
+#define CDU_REGISTERS_MATT 0x100UL
+#define CDU_REGISTERS_MATT_SIZE 64
+#define CFC_REGISTERS_AC_INIT_DONE 0x78UL
+#define CFC_REGISTERS_ACTIVITY_COUNTER 0x400UL
+#define CFC_REGISTERS_ACTIVITY_COUNTER_SIZE 256
+#define CFC_REGISTERS_ACTIVITY_COUNTER_SIZE 256
+#define CFC_REGISTERS_CAM_INIT_DONE 0x7cUL
+#define CFC_REGISTERS_CFC_INT_STS 0xfcUL
+#define CFC_REGISTERS_CFC_INT_STS_CLR 0x100UL
+#define CFC_REGISTERS_CFC_INT_STS_WR 0x104UL
+#define CFC_REGISTERS_CONTROL0 0x28UL
+#define CFC_REGISTERS_DEBUG0 0x50UL
+#define CFC_REGISTERS_DISABLE_ON_ERROR 0x44UL
+#define CFC_REGISTERS_ERROR_VECTOR 0x3cUL
+#define CFC_REGISTERS_INIT_REG 0x4cUL
+#define CFC_REGISTERS_LCREQ_WEIGHTS 0x84UL
+#define CFC_REGISTERS_LL_INIT_DONE 0x74UL
+#define CFC_REGISTERS_NUM_LCIDS_ALLOC 0x20UL
+#define CFC_REGISTERS_NUM_LCIDS_ARRIVING 0x4UL
+#define CFC_REGISTERS_NUM_LCIDS_INSIDE 0x8UL
+#define CFC_REGISTERS_NUM_LCIDS_LEAVING 0x18UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_0 0x38UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_1 0x3cUL
+#define CSDM_REGISTERS_AGG_INT_EVENT_10 0x60UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_11 0x64UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_12 0x68UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_13 0x6cUL
+#define CSDM_REGISTERS_AGG_INT_EVENT_14 0x70UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_15 0x74UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_16 0x78UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_17 0x7cUL
+#define CSDM_REGISTERS_AGG_INT_EVENT_18 0x80UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_19 0x84UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_10 0x60UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_11 0x64UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_12 0x68UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_13 0x6cUL
+#define CSDM_REGISTERS_AGG_INT_EVENT_14 0x70UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_15 0x74UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_16 0x78UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_17 0x7cUL
+#define CSDM_REGISTERS_AGG_INT_EVENT_18 0x80UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_19 0x84UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_2 0x40UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_20 0x88UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_21 0x8cUL
+#define CSDM_REGISTERS_AGG_INT_EVENT_22 0x90UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_23 0x94UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_24 0x98UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_25 0x9cUL
+#define CSDM_REGISTERS_AGG_INT_EVENT_26 0xa0UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_27 0xa4UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_28 0xa8UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_29 0xacUL
+#define CSDM_REGISTERS_AGG_INT_EVENT_20 0x88UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_21 0x8cUL
+#define CSDM_REGISTERS_AGG_INT_EVENT_22 0x90UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_23 0x94UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_24 0x98UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_25 0x9cUL
+#define CSDM_REGISTERS_AGG_INT_EVENT_26 0xa0UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_27 0xa4UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_28 0xa8UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_29 0xacUL
+#define CSDM_REGISTERS_AGG_INT_EVENT_3 0x44UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_30 0xb0UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_31 0xb4UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_30 0xb0UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_31 0xb4UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_4 0x48UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_5 0x4cUL
+#define CSDM_REGISTERS_AGG_INT_EVENT_6 0x50UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_7 0x54UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_8 0x58UL
+#define CSDM_REGISTERS_AGG_INT_EVENT_9 0x5cUL
+#define CSDM_REGISTERS_AGG_INT_FIC_0 0x138UL
+#define CSDM_REGISTERS_AGG_INT_FIC_1 0x13cUL
+#define CSDM_REGISTERS_AGG_INT_FIC_10 0x160UL
+#define CSDM_REGISTERS_AGG_INT_FIC_11 0x164UL
+#define CSDM_REGISTERS_AGG_INT_FIC_12 0x168UL
+#define CSDM_REGISTERS_AGG_INT_FIC_13 0x16cUL
+#define CSDM_REGISTERS_AGG_INT_FIC_14 0x170UL
+#define CSDM_REGISTERS_AGG_INT_FIC_15 0x174UL
+#define CSDM_REGISTERS_AGG_INT_FIC_16 0x178UL
+#define CSDM_REGISTERS_AGG_INT_FIC_17 0x17cUL
+#define CSDM_REGISTERS_AGG_INT_FIC_18 0x180UL
+#define CSDM_REGISTERS_AGG_INT_FIC_19 0x184UL
+#define CSDM_REGISTERS_AGG_INT_FIC_10 0x160UL
+#define CSDM_REGISTERS_AGG_INT_FIC_11 0x164UL
+#define CSDM_REGISTERS_AGG_INT_FIC_12 0x168UL
+#define CSDM_REGISTERS_AGG_INT_FIC_13 0x16cUL
+#define CSDM_REGISTERS_AGG_INT_FIC_14 0x170UL
+#define CSDM_REGISTERS_AGG_INT_FIC_15 0x174UL
+#define CSDM_REGISTERS_AGG_INT_FIC_16 0x178UL
+#define CSDM_REGISTERS_AGG_INT_FIC_17 0x17cUL
+#define CSDM_REGISTERS_AGG_INT_FIC_18 0x180UL
+#define CSDM_REGISTERS_AGG_INT_FIC_19 0x184UL
+#define CSDM_REGISTERS_AGG_INT_FIC_2 0x140UL
+#define CSDM_REGISTERS_AGG_INT_FIC_20 0x188UL
+#define CSDM_REGISTERS_AGG_INT_FIC_21 0x18cUL
+#define CSDM_REGISTERS_AGG_INT_FIC_22 0x190UL
+#define CSDM_REGISTERS_AGG_INT_FIC_23 0x194UL
+#define CSDM_REGISTERS_AGG_INT_FIC_24 0x198UL
+#define CSDM_REGISTERS_AGG_INT_FIC_25 0x19cUL
+#define CSDM_REGISTERS_AGG_INT_FIC_26 0x1a0UL
+#define CSDM_REGISTERS_AGG_INT_FIC_27 0x1a4UL
+#define CSDM_REGISTERS_AGG_INT_FIC_28 0x1a8UL
+#define CSDM_REGISTERS_AGG_INT_FIC_29 0x1acUL
+#define CSDM_REGISTERS_AGG_INT_FIC_20 0x188UL
+#define CSDM_REGISTERS_AGG_INT_FIC_21 0x18cUL
+#define CSDM_REGISTERS_AGG_INT_FIC_22 0x190UL
+#define CSDM_REGISTERS_AGG_INT_FIC_23 0x194UL
+#define CSDM_REGISTERS_AGG_INT_FIC_24 0x198UL
+#define CSDM_REGISTERS_AGG_INT_FIC_25 0x19cUL
+#define CSDM_REGISTERS_AGG_INT_FIC_26 0x1a0UL
+#define CSDM_REGISTERS_AGG_INT_FIC_27 0x1a4UL
+#define CSDM_REGISTERS_AGG_INT_FIC_28 0x1a8UL
+#define CSDM_REGISTERS_AGG_INT_FIC_29 0x1acUL
+#define CSDM_REGISTERS_AGG_INT_FIC_3 0x144UL
+#define CSDM_REGISTERS_AGG_INT_FIC_30 0x1b0UL
+#define CSDM_REGISTERS_AGG_INT_FIC_31 0x1b4UL
+#define CSDM_REGISTERS_AGG_INT_FIC_30 0x1b0UL
+#define CSDM_REGISTERS_AGG_INT_FIC_31 0x1b4UL
+#define CSDM_REGISTERS_AGG_INT_FIC_4 0x148UL
+#define CSDM_REGISTERS_AGG_INT_FIC_5 0x14cUL
+#define CSDM_REGISTERS_AGG_INT_FIC_6 0x150UL
+#define CSDM_REGISTERS_AGG_INT_FIC_7 0x154UL
+#define CSDM_REGISTERS_AGG_INT_FIC_8 0x158UL
+#define CSDM_REGISTERS_AGG_INT_FIC_9 0x15cUL
+#define CSDM_REGISTERS_AGG_INT_MODE_0 0x1b8UL
+#define CSDM_REGISTERS_AGG_INT_MODE_1 0x1bcUL
+#define CSDM_REGISTERS_AGG_INT_MODE_10 0x1e0UL
+#define CSDM_REGISTERS_AGG_INT_MODE_11 0x1e4UL
+#define CSDM_REGISTERS_AGG_INT_MODE_12 0x1e8UL
+#define CSDM_REGISTERS_AGG_INT_MODE_13 0x1ecUL
+#define CSDM_REGISTERS_AGG_INT_MODE_14 0x1f0UL
+#define CSDM_REGISTERS_AGG_INT_MODE_15 0x1f4UL
+#define CSDM_REGISTERS_AGG_INT_MODE_16 0x1f8UL
+#define CSDM_REGISTERS_AGG_INT_MODE_17 0x1fcUL
+#define CSDM_REGISTERS_AGG_INT_MODE_18 0x200UL
+#define CSDM_REGISTERS_AGG_INT_MODE_19 0x204UL
+#define CSDM_REGISTERS_AGG_INT_MODE_10 0x1e0UL
+#define CSDM_REGISTERS_AGG_INT_MODE_11 0x1e4UL
+#define CSDM_REGISTERS_AGG_INT_MODE_12 0x1e8UL
+#define CSDM_REGISTERS_AGG_INT_MODE_13 0x1ecUL
+#define CSDM_REGISTERS_AGG_INT_MODE_14 0x1f0UL
+#define CSDM_REGISTERS_AGG_INT_MODE_15 0x1f4UL
+#define CSDM_REGISTERS_AGG_INT_MODE_16 0x1f8UL
+#define CSDM_REGISTERS_AGG_INT_MODE_17 0x1fcUL
+#define CSDM_REGISTERS_AGG_INT_MODE_18 0x200UL
+#define CSDM_REGISTERS_AGG_INT_MODE_19 0x204UL
+#define CSDM_REGISTERS_AGG_INT_MODE_2 0x1c0UL
+#define CSDM_REGISTERS_AGG_INT_MODE_20 0x208UL
+#define CSDM_REGISTERS_AGG_INT_MODE_21 0x20cUL
+#define CSDM_REGISTERS_AGG_INT_MODE_22 0x210UL
+#define CSDM_REGISTERS_AGG_INT_MODE_23 0x214UL
+#define CSDM_REGISTERS_AGG_INT_MODE_24 0x218UL
+#define CSDM_REGISTERS_AGG_INT_MODE_25 0x21cUL
+#define CSDM_REGISTERS_AGG_INT_MODE_26 0x220UL
+#define CSDM_REGISTERS_AGG_INT_MODE_27 0x224UL
+#define CSDM_REGISTERS_AGG_INT_MODE_28 0x228UL
+#define CSDM_REGISTERS_AGG_INT_MODE_29 0x22cUL
+#define CSDM_REGISTERS_AGG_INT_MODE_20 0x208UL
+#define CSDM_REGISTERS_AGG_INT_MODE_21 0x20cUL
+#define CSDM_REGISTERS_AGG_INT_MODE_22 0x210UL
+#define CSDM_REGISTERS_AGG_INT_MODE_23 0x214UL
+#define CSDM_REGISTERS_AGG_INT_MODE_24 0x218UL
+#define CSDM_REGISTERS_AGG_INT_MODE_25 0x21cUL
+#define CSDM_REGISTERS_AGG_INT_MODE_26 0x220UL
+#define CSDM_REGISTERS_AGG_INT_MODE_27 0x224UL
+#define CSDM_REGISTERS_AGG_INT_MODE_28 0x228UL
+#define CSDM_REGISTERS_AGG_INT_MODE_29 0x22cUL
+#define CSDM_REGISTERS_AGG_INT_MODE_3 0x1c4UL
+#define CSDM_REGISTERS_AGG_INT_MODE_30 0x230UL
+#define CSDM_REGISTERS_AGG_INT_MODE_31 0x234UL
+#define CSDM_REGISTERS_AGG_INT_MODE_30 0x230UL
+#define CSDM_REGISTERS_AGG_INT_MODE_31 0x234UL
+#define CSDM_REGISTERS_AGG_INT_MODE_4 0x1c8UL
+#define CSDM_REGISTERS_AGG_INT_MODE_5 0x1ccUL
+#define CSDM_REGISTERS_AGG_INT_MODE_6 0x1d0UL
+#define CSDM_REGISTERS_AGG_INT_MODE_7 0x1d4UL
+#define CSDM_REGISTERS_AGG_INT_MODE_8 0x1d8UL
+#define CSDM_REGISTERS_AGG_INT_MODE_9 0x1dcUL
+#define CSDM_REGISTERS_AGG_INT_T_0 0xb8UL
+#define CSDM_REGISTERS_AGG_INT_T_1 0xbcUL
+#define CSDM_REGISTERS_AGG_INT_T_10 0xe0UL
+#define CSDM_REGISTERS_AGG_INT_T_11 0xe4UL
+#define CSDM_REGISTERS_AGG_INT_T_12 0xe8UL
+#define CSDM_REGISTERS_AGG_INT_T_13 0xecUL
+#define CSDM_REGISTERS_AGG_INT_T_14 0xf0UL
+#define CSDM_REGISTERS_AGG_INT_T_15 0xf4UL
+#define CSDM_REGISTERS_AGG_INT_T_16 0xf8UL
+#define CSDM_REGISTERS_AGG_INT_T_17 0xfcUL
+#define CSDM_REGISTERS_AGG_INT_T_18 0x100UL
+#define CSDM_REGISTERS_AGG_INT_T_19 0x104UL
+#define CSDM_REGISTERS_AGG_INT_T_10 0xe0UL
+#define CSDM_REGISTERS_AGG_INT_T_11 0xe4UL
+#define CSDM_REGISTERS_AGG_INT_T_12 0xe8UL
+#define CSDM_REGISTERS_AGG_INT_T_13 0xecUL
+#define CSDM_REGISTERS_AGG_INT_T_14 0xf0UL
+#define CSDM_REGISTERS_AGG_INT_T_15 0xf4UL
+#define CSDM_REGISTERS_AGG_INT_T_16 0xf8UL
+#define CSDM_REGISTERS_AGG_INT_T_17 0xfcUL
+#define CSDM_REGISTERS_AGG_INT_T_18 0x100UL
+#define CSDM_REGISTERS_AGG_INT_T_19 0x104UL
+#define CSDM_REGISTERS_AGG_INT_T_2 0xc0UL
+#define CSDM_REGISTERS_AGG_INT_T_20 0x108UL
+#define CSDM_REGISTERS_AGG_INT_T_21 0x10cUL
+#define CSDM_REGISTERS_AGG_INT_T_22 0x110UL
+#define CSDM_REGISTERS_AGG_INT_T_23 0x114UL
+#define CSDM_REGISTERS_AGG_INT_T_24 0x118UL
+#define CSDM_REGISTERS_AGG_INT_T_25 0x11cUL
+#define CSDM_REGISTERS_AGG_INT_T_26 0x120UL
+#define CSDM_REGISTERS_AGG_INT_T_27 0x124UL
+#define CSDM_REGISTERS_AGG_INT_T_28 0x128UL
+#define CSDM_REGISTERS_AGG_INT_T_29 0x12cUL
+#define CSDM_REGISTERS_AGG_INT_T_20 0x108UL
+#define CSDM_REGISTERS_AGG_INT_T_21 0x10cUL
+#define CSDM_REGISTERS_AGG_INT_T_22 0x110UL
+#define CSDM_REGISTERS_AGG_INT_T_23 0x114UL
+#define CSDM_REGISTERS_AGG_INT_T_24 0x118UL
+#define CSDM_REGISTERS_AGG_INT_T_25 0x11cUL
+#define CSDM_REGISTERS_AGG_INT_T_26 0x120UL
+#define CSDM_REGISTERS_AGG_INT_T_27 0x124UL
+#define CSDM_REGISTERS_AGG_INT_T_28 0x128UL
+#define CSDM_REGISTERS_AGG_INT_T_29 0x12cUL
+#define CSDM_REGISTERS_AGG_INT_T_3 0xc4UL
+#define CSDM_REGISTERS_AGG_INT_T_30 0x130UL
+#define CSDM_REGISTERS_AGG_INT_T_31 0x134UL
+#define CSDM_REGISTERS_AGG_INT_T_30 0x130UL
+#define CSDM_REGISTERS_AGG_INT_T_31 0x134UL
+#define CSDM_REGISTERS_AGG_INT_T_4 0xc8UL
+#define CSDM_REGISTERS_AGG_INT_T_5 0xccUL
+#define CSDM_REGISTERS_AGG_INT_T_6 0xd0UL
+#define CSDM_REGISTERS_AGG_INT_T_7 0xd4UL
+#define CSDM_REGISTERS_AGG_INT_T_8 0xd8UL
+#define CSDM_REGISTERS_AGG_INT_T_9 0xdcUL
+#define CSDM_REGISTERS_CFC_RSP_START_ADDR 0x8UL
+#define CSDM_REGISTERS_CMP_COUNTER_MAX0 0x1cUL
+#define CSDM_REGISTERS_CMP_COUNTER_MAX1 0x20UL
+#define CSDM_REGISTERS_CMP_COUNTER_MAX2 0x24UL
+#define CSDM_REGISTERS_CMP_COUNTER_MAX3 0x28UL
+#define CSDM_REGISTERS_CMP_COUNTER_START_ADDR 0xcUL
+#define CSDM_REGISTERS_ENABLE_IN1 0x238UL
+#define CSDM_REGISTERS_ENABLE_IN2 0x23cUL
+#define CSDM_REGISTERS_ENABLE_OUT1 0x240UL
+#define CSDM_REGISTERS_ENABLE_OUT2 0x244UL
+#define CSDM_REGISTERS_NUM_OF_ACK_AFTER_PLACE 0x27cUL
+#define CSDM_REGISTERS_NUM_OF_PKT_END_MSG 0x274UL
+#define CSDM_REGISTERS_NUM_OF_PXP_ASYNC_REQ 0x278UL
+#define CSDM_REGISTERS_NUM_OF_Q0_CMD 0x248UL
+#define CSDM_REGISTERS_NUM_OF_Q10_CMD 0x26cUL
+#define CSDM_REGISTERS_NUM_OF_Q11_CMD 0x270UL
+#define CSDM_REGISTERS_NUM_OF_Q1_CMD 0x24cUL
+#define CSDM_REGISTERS_NUM_OF_Q3_CMD 0x250UL
+#define CSDM_REGISTERS_NUM_OF_Q4_CMD 0x254UL
+#define CSDM_REGISTERS_NUM_OF_Q5_CMD 0x258UL
+#define CSDM_REGISTERS_NUM_OF_Q6_CMD 0x25cUL
+#define CSDM_REGISTERS_NUM_OF_Q7_CMD 0x260UL
+#define CSDM_REGISTERS_NUM_OF_Q8_CMD 0x264UL
+#define CSDM_REGISTERS_NUM_OF_Q9_CMD 0x268UL
+#define CSDM_REGISTERS_Q_COUNTER_START_ADDR 0x10UL
+#define CSDM_REGISTERS_RSP_PXP_CTRL_RDATA_EMPTY 0x548UL
+#define CSDM_REGISTERS_RSP_PXP_CTRL_RDATA_EMPTY_SIZE 1
+#define CSDM_REGISTERS_SYNC_PARSER_EMPTY 0x550UL
+#define CSDM_REGISTERS_SYNC_PARSER_EMPTY_SIZE 1
+#define CSDM_REGISTERS_SYNC_SYNC_EMPTY 0x558UL
+#define CSDM_REGISTERS_SYNC_SYNC_EMPTY_SIZE 1
+#define CSDM_REGISTERS_TIMER_TICK 0x0UL
+#define CSEM_REGISTERS_ARB_CYCLE_SIZE 0x34UL
+#define CSEM_REGISTERS_ARB_ELEMENT0 0x20UL
+#define CSEM_REGISTERS_ARB_ELEMENT1 0x24UL
+#define CSEM_REGISTERS_ARB_ELEMENT2 0x28UL
+#define CSEM_REGISTERS_ARB_ELEMENT3 0x2cUL
+#define CSEM_REGISTERS_ARB_ELEMENT4 0x30UL
+#define CSEM_REGISTERS_ENABLE_IN 0xa4UL
+#define CSEM_REGISTERS_ENABLE_OUT 0xa8UL
+#define CSEM_REGISTERS_FAST_MEMORY 0x20000UL
+#define CSEM_REGISTERS_FAST_MEMORY_SIZE 32768
+#define CSEM_REGISTERS_FIC0_DISABLE 0x224UL
+#define CSEM_REGISTERS_FIC0_DISABLE_SIZE 1
+#define CSEM_REGISTERS_FIC1_DISABLE 0x234UL
+#define CSEM_REGISTERS_FIC1_DISABLE_SIZE 1
+#define CSEM_REGISTERS_INT_TABLE_TM 0xd4UL
+#define CSEM_REGISTERS_INT_TABLE 0x400UL
+#define CSEM_REGISTERS_INT_TABLE_SIZE 256
+#define CSEM_REGISTERS_MSG_NUM_FIC0 0x0UL
+#define CSEM_REGISTERS_MSG_NUM_FIC1 0x4UL
+#define CSEM_REGISTERS_MSG_NUM_FOC0 0x8UL
+#define CSEM_REGISTERS_MSG_NUM_FOC1 0xcUL
+#define CSEM_REGISTERS_MSG_NUM_FOC2 0x10UL
+#define CSEM_REGISTERS_MSG_NUM_FOC3 0x14UL
+#define CSEM_REGISTERS_PAS_DISABLE 0x24cUL
+#define CSEM_REGISTERS_PAS_DISABLE_SIZE 1
+#define CSEM_REGISTERS_PASSIVE_BUFFER 0x2000UL
+#define CSEM_REGISTERS_PASSIVE_BUFFER_SIZE 2048
+#define CSEM_REGISTERS_PRAM 0x40000UL
+#define CSEM_REGISTERS_PRAM_SIZE 65536
+#define CSEM_REGISTERS_SLEEP_THREADS_VALID 0x26cUL
+#define CSEM_REGISTERS_SLEEP_THREADS_VALID_SIZE 1
+#define CSEM_REGISTERS_SLOW_EXT_STORE_EMPTY 0x2a0UL
+#define CSEM_REGISTERS_SLOW_EXT_STORE_EMPTY_SIZE 1
+#define CSEM_REGISTERS_THREADS_LIST 0x2e4UL
+#define CSEM_REGISTERS_THREADS_LIST_SIZE 1
+#define CSEM_REGISTERS_TS_0_AS 0x38UL
+#define CSEM_REGISTERS_TS_10_AS 0x60UL
+#define CSEM_REGISTERS_TS_11_AS 0x64UL
+#define CSEM_REGISTERS_TS_12_AS 0x68UL
+#define CSEM_REGISTERS_TS_13_AS 0x6cUL
+#define CSEM_REGISTERS_TS_14_AS 0x70UL
+#define CSEM_REGISTERS_TS_15_AS 0x74UL
+#define CSEM_REGISTERS_TS_16_AS 0x78UL
+#define CSEM_REGISTERS_TS_17_AS 0x7cUL
+#define CSEM_REGISTERS_TS_18_AS 0x80UL
+#define CSEM_REGISTERS_TS_19_AS 0x84UL
+#define CSEM_REGISTERS_TS_1_AS 0x3cUL
+#define CSEM_REGISTERS_TS_2_AS 0x40UL
+#define CSEM_REGISTERS_TS_3_AS 0x44UL
+#define CSEM_REGISTERS_TS_4_AS 0x48UL
+#define CSEM_REGISTERS_TS_5_AS 0x4cUL
+#define CSEM_REGISTERS_TS_6_AS 0x50UL
+#define CSEM_REGISTERS_TS_7_AS 0x54UL
+#define CSEM_REGISTERS_TS_8_AS 0x58UL
+#define CSEM_REGISTERS_TS_9_AS 0x5cUL
+#define DMAE_REGISTERS_CMD_MEM 0x400UL
+#define DMAE_REGISTERS_CMD_MEM_SIZE 224
+#define DMAE_REGISTERS_CRC16C_INIT 0x1cUL
+#define DMAE_REGISTERS_CRC16T10_INIT 0x20UL
+#define DMAE_REGISTERS_GO_C0 0x80UL
+#define DMAE_REGISTERS_GO_C0_SIZE 1
+#define DMAE_REGISTERS_GO_C1 0x84UL
+#define DMAE_REGISTERS_GO_C1_SIZE 1
+#define DMAE_REGISTERS_GO_C10 0x88UL
+#define DMAE_REGISTERS_GO_C10_SIZE 1
+#define DMAE_REGISTERS_GO_C11 0x8cUL
+#define DMAE_REGISTERS_GO_C11_SIZE 1
+#define DMAE_REGISTERS_GO_C12 0x90UL
+#define DMAE_REGISTERS_GO_C12_SIZE 1
+#define DMAE_REGISTERS_GO_C13 0x94UL
+#define DMAE_REGISTERS_GO_C13_SIZE 1
+#define DMAE_REGISTERS_GO_C14 0x98UL
+#define DMAE_REGISTERS_GO_C14_SIZE 1
+#define DMAE_REGISTERS_GO_C15 0x9cUL
+#define DMAE_REGISTERS_GO_C15_SIZE 1
+#define DMAE_REGISTERS_GO_C10 0x88UL
+#define DMAE_REGISTERS_GO_C10_SIZE 1
+#define DMAE_REGISTERS_GO_C11 0x8cUL
+#define DMAE_REGISTERS_GO_C11_SIZE 1
+#define DMAE_REGISTERS_GO_C12 0x90UL
+#define DMAE_REGISTERS_GO_C12_SIZE 1
+#define DMAE_REGISTERS_GO_C13 0x94UL
+#define DMAE_REGISTERS_GO_C13_SIZE 1
+#define DMAE_REGISTERS_GO_C14 0x98UL
+#define DMAE_REGISTERS_GO_C14_SIZE 1
+#define DMAE_REGISTERS_GO_C15 0x9cUL
+#define DMAE_REGISTERS_GO_C15_SIZE 1
+#define DMAE_REGISTERS_GO_C2 0xa0UL
+#define DMAE_REGISTERS_GO_C2_SIZE 1
+#define DMAE_REGISTERS_GO_C3 0xa4UL
+#define DMAE_REGISTERS_GO_C3_SIZE 1
+#define DMAE_REGISTERS_GO_C4 0xa8UL
+#define DMAE_REGISTERS_GO_C4_SIZE 1
+#define DMAE_REGISTERS_GO_C5 0xacUL
+#define DMAE_REGISTERS_GO_C5_SIZE 1
+#define DMAE_REGISTERS_GO_C6 0xb0UL
+#define DMAE_REGISTERS_GO_C6_SIZE 1
+#define DMAE_REGISTERS_GO_C7 0xb4UL
+#define DMAE_REGISTERS_GO_C7_SIZE 1
+#define DMAE_REGISTERS_GO_C8 0xb8UL
+#define DMAE_REGISTERS_GO_C8_SIZE 1
+#define DMAE_REGISTERS_GO_C9 0xbcUL
+#define DMAE_REGISTERS_GO_C9_SIZE 1
+#define DMAE_REGISTERS_GRC_IFEN 0x8UL
+#define DMAE_REGISTERS_PCI_IFEN 0x4UL
+#define DMAE_REGISTERS_PXP_REQ_INIT_CRD 0xc0UL
+#define DMAE_REGISTERS_PXP_REQ_INIT_CRD_SIZE 1
+#define DORQ_REGISTERS_AGG_CMD0 0x60UL
+#define DORQ_REGISTERS_AGG_CMD1 0x64UL
+#define DORQ_REGISTERS_AGG_CMD2 0x68UL
+#define DORQ_REGISTERS_AGG_CMD3 0x6cUL
+#define DORQ_REGISTERS_CMHEAD_RX 0x50UL
+#define DORQ_REGISTERS_DORQ_INT_MASK 0x180UL
+#define DORQ_REGISTERS_DORQ_INT_STS 0x174UL
+#define DORQ_REGISTERS_DORQ_INT_STS_CLR 0x178UL
+#define DORQ_REGISTERS_DORQ_INT_STS_WR 0x17cUL
+#define DORQ_REGISTERS_DORQ_INT_STS_CLR 0x178UL
+#define DORQ_REGISTERS_DPM_CID_ADDR 0x44UL
+#define DORQ_REGISTERS_DPM_CID_OFST 0x30UL
+#define DORQ_REGISTERS_DQ_FIFO_AFULL_TH 0x7cUL
+#define DORQ_REGISTERS_DQ_FIFO_FULL_TH 0x78UL
+#define DORQ_REGISTERS_DQ_FILL_LVLF 0xa4UL
+#define DORQ_REGISTERS_DQ_FULL_ST 0xc0UL
+#define DORQ_REGISTERS_ERR_CMHEAD 0x58UL
+#define DORQ_REGISTERS_IF_EN 0x4UL
+#define DORQ_REGISTERS_MODE_ACT 0x8UL
+#define DORQ_REGISTERS_NORM_CID_OFST 0x2cUL
+#define DORQ_REGISTERS_NORM_CMHEAD_TX 0x4cUL
+#define DORQ_REGISTERS_OUTST_REQ 0x3cUL
+#define DORQ_REGISTERS_OUTST_REQ_CNT 0xa8UL
+#define DORQ_REGISTERS_REGN 0x38UL
+#define DORQ_REGISTERS_RSPA_CRD_CNT 0xacUL
+#define DORQ_REGISTERS_RSP_INIT_CRD 0x48UL
+#define DORQ_REGISTERS_SHRT_ACT_CNT 0x70UL
+#define DORQ_REGISTERS_SHRT_CMHEAD 0x54UL
+#define HC_CONFIG_0_REGISTERS_ATTN_BIT_EN_0 (0x1<<4)
+#define HC_CONFIG_0_REGISTERS_ATTN_BIT_EN_0_SIZE 4
+#define HC_CONFIG_0_REGISTERS_INT_LINE_EN_0 (0x1<<3)
+#define HC_CONFIG_0_REGISTERS_INT_LINE_EN_0_SIZE 3
+#define HC_CONFIG_0_REGISTERS_MSI_MSIX_INT_EN_0 (0x1<<2)
+#define HC_CONFIG_0_REGISTERS_MSI_MSIX_INT_EN_0_SIZE 2
+#define HC_CONFIG_0_REGISTERS_SINGLE_ISR_EN_0 (0x1<<1)
+#define HC_CONFIG_0_REGISTERS_SINGLE_ISR_EN_0_SIZE 1
+#define HC_REGISTERS_AGG_INT_0 0x50UL
+#define HC_REGISTERS_AGG_INT_1 0x54UL
+#define HC_REGISTERS_ATTN_BIT 0x120UL
+#define HC_REGISTERS_ATTN_BIT_SIZE 4
+#define HC_REGISTERS_ATTN_IDX 0x100UL
+#define HC_REGISTERS_ATTN_IDX_SIZE 2
+#define HC_REGISTERS_ATTN_MSG0_ADDR_L 0x18UL
+#define HC_REGISTERS_ATTN_MSG1_ADDR_L 0x20UL
+#define HC_REGISTERS_ATTN_NUM_P0 0x38UL
+#define HC_REGISTERS_ATTN_NUM_P1 0x3cUL
+#define HC_REGISTERS_CONFIG_0 0x0UL
+#define HC_REGISTERS_CONFIG_1 0x4UL
+#define HC_REGISTERS_CSTORM_ADDR_FOR_COALESCE 0x6cUL
+#define HC_REGISTERS_INT_MASK 0x108UL
+#define HC_REGISTERS_INT_MASK_SIZE 2
+#define HC_REGISTERS_LEADING_EDGE_0 0x40UL
+#define HC_REGISTERS_LEADING_EDGE_1 0x48UL
+#define HC_REGISTERS_P0_PROD_CONS 0x200UL
+#define HC_REGISTERS_P0_PROD_CONS_SIZE 74
+#define HC_REGISTERS_P1_PROD_CONS 0x400UL
+#define HC_REGISTERS_P1_PROD_CONS_SIZE 74
+#define HC_REGISTERS_PBA_COMMAND 0x140UL
+#define HC_REGISTERS_PBA_COMMAND_SIZE 4
+#define HC_REGISTERS_PCI_CONFIG_0 0x10UL
+#define HC_REGISTERS_PCI_CONFIG_1 0x14UL
+#define HC_REGISTERS_STATISTIC_COUNTERS 0x1000UL
+#define HC_REGISTERS_STATISTIC_COUNTERS_SIZE 516
+#define HC_REGISTERS_TRAILING_EDGE_0 0x44UL
+#define HC_REGISTERS_TRAILING_EDGE_1 0x4cUL
+#define HC_REGISTERS_TSTORM_ADDR_FOR_COALESCE 0x74UL
+#define HC_REGISTERS_UC_RAM_ADDR_0 0x28UL
+#define HC_REGISTERS_UC_RAM_ADDR_1 0x30UL
+#define HC_REGISTERS_USTORM_ADDR_FOR_COALESCE 0x68UL
+#define HC_REGISTERS_VQID_0 0x8UL
+#define HC_REGISTERS_VQID_1 0xcUL
+#define HC_REGISTERS_XSTORM_ADDR_FOR_COALESCE 0x70UL
+#define HC_REGISTERS_XT_RAM_ADDR_0 0x2cUL
+#define HC_REGISTERS_XT_RAM_ADDR_1 0x34UL
+#define MISC_REGISTERS_AEU_AFTER_INVERT_1_FUNC_0 0x42cUL
+#define MISC_REGISTERS_AEU_AFTER_INVERT_1_FUNC_0_SIZE 1
+#define MISC_REGISTERS_AEU_AFTER_INVERT_1_FUNC_1 0x430UL
+#define MISC_REGISTERS_AEU_AFTER_INVERT_1_FUNC_1_SIZE 1
+#define MISC_REGISTERS_AEU_AFTER_INVERT_1_MCP 0x434UL
+#define MISC_REGISTERS_AEU_AFTER_INVERT_1_MCP_SIZE 1
+#define MISC_REGISTERS_AEU_AFTER_INVERT_2_FUNC_0 0x438UL
+#define MISC_REGISTERS_AEU_AFTER_INVERT_2_FUNC_0_SIZE 1
+#define MISC_REGISTERS_AEU_AFTER_INVERT_2_FUNC_1 0x43cUL
+#define MISC_REGISTERS_AEU_AFTER_INVERT_2_FUNC_1_SIZE 1
+#define MISC_REGISTERS_AEU_AFTER_INVERT_2_MCP 0x440UL
+#define MISC_REGISTERS_AEU_AFTER_INVERT_2_MCP_SIZE 1
+#define MISC_REGISTERS_AEU_AFTER_INVERT_3_FUNC_0 0x444UL
+#define MISC_REGISTERS_AEU_AFTER_INVERT_3_FUNC_0_SIZE 1
+#define MISC_REGISTERS_AEU_AFTER_INVERT_3_FUNC_1 0x448UL
+#define MISC_REGISTERS_AEU_AFTER_INVERT_3_FUNC_1_SIZE 1
+#define MISC_REGISTERS_AEU_AFTER_INVERT_3_MCP 0x44cUL
+#define MISC_REGISTERS_AEU_AFTER_INVERT_3_MCP_SIZE 1
+#define MISC_REGISTERS_AEU_AFTER_INVERT_4_FUNC_0 0x450UL
+#define MISC_REGISTERS_AEU_AFTER_INVERT_4_FUNC_0_SIZE 1
+#define MISC_REGISTERS_AEU_AFTER_INVERT_4_FUNC_1 0x454UL
+#define MISC_REGISTERS_AEU_AFTER_INVERT_4_FUNC_1_SIZE 1
+#define MISC_REGISTERS_AEU_AFTER_INVERT_4_MCP 0x458UL
+#define MISC_REGISTERS_AEU_AFTER_INVERT_4_MCP_SIZE 1
+#define MISC_REGISTERS_AEU_CLR_LATCH_SIGNAL 0x45cUL
+#define MISC_REGISTERS_AEU_CLR_LATCH_SIGNAL_SIZE 1
+#define MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_0 0x6cUL
+#define MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_1 0x7cUL
+#define MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_2 0x8cUL
+#define MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_3 0x9cUL
+#define MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_4 0xacUL
+#define MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_5 0xbcUL
+#define MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_6 0xccUL
+#define MISC_REGISTERS_AEU_ENABLE1_FUNC_0_OUT_7 0xdcUL
+#define MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_0 0x10cUL
+#define MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_1 0x11cUL
+#define MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_2 0x12cUL
+#define MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_3 0x13cUL
+#define MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_4 0x14cUL
+#define MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_5 0x15cUL
+#define MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_6 0x16cUL
+#define MISC_REGISTERS_AEU_ENABLE1_FUNC_1_OUT_7 0x17cUL
+#define MISC_REGISTERS_AEU_ENABLE1_NIG_0 0xecUL
+#define MISC_REGISTERS_AEU_ENABLE1_NIG_1 0x18cUL
+#define MISC_REGISTERS_AEU_ENABLE1_PXP_0 0xfcUL
+#define MISC_REGISTERS_AEU_ENABLE1_PXP_1 0x19cUL
+#define MISC_REGISTERS_AEU_ENABLE2_FUNC_0_OUT_0 0x70UL
+#define MISC_REGISTERS_AEU_ENABLE2_FUNC_0_OUT_1 0x80UL
+#define MISC_REGISTERS_AEU_ENABLE2_FUNC_0_OUT_2 0x90UL
+#define MISC_REGISTERS_AEU_ENABLE2_FUNC_0_OUT_3 0xa0UL
+#define MISC_REGISTERS_AEU_ENABLE2_FUNC_0_OUT_4 0xb0UL
+#define MISC_REGISTERS_AEU_ENABLE2_FUNC_0_OUT_5 0xc0UL
+#define MISC_REGISTERS_AEU_ENABLE2_FUNC_0_OUT_6 0xd0UL
+#define MISC_REGISTERS_AEU_ENABLE2_FUNC_0_OUT_7 0xe0UL
+#define MISC_REGISTERS_AEU_ENABLE2_FUNC_1_OUT_0 0x110UL
+#define MISC_REGISTERS_AEU_ENABLE2_FUNC_1_OUT_1 0x120UL
+#define MISC_REGISTERS_AEU_ENABLE2_FUNC_1_OUT_2 0x130UL
+#define MISC_REGISTERS_AEU_ENABLE2_FUNC_1_OUT_3 0x140UL
+#define MISC_REGISTERS_AEU_ENABLE2_FUNC_1_OUT_4 0x150UL
+#define MISC_REGISTERS_AEU_ENABLE2_FUNC_1_OUT_5 0x160UL
+#define MISC_REGISTERS_AEU_ENABLE2_FUNC_1_OUT_6 0x170UL
+#define MISC_REGISTERS_AEU_ENABLE2_FUNC_1_OUT_7 0x180UL
+#define MISC_REGISTERS_AEU_ENABLE2_NIG_0 0xf0UL
+#define MISC_REGISTERS_AEU_ENABLE2_NIG_1 0x190UL
+#define MISC_REGISTERS_AEU_ENABLE2_PXP_0 0x100UL
+#define MISC_REGISTERS_AEU_ENABLE2_PXP_1 0x1a0UL
+#define MISC_REGISTERS_AEU_ENABLE3_FUNC_0_OUT_0 0x74UL
+#define MISC_REGISTERS_AEU_ENABLE3_FUNC_0_OUT_1 0x84UL
+#define MISC_REGISTERS_AEU_ENABLE3_FUNC_0_OUT_2 0x94UL
+#define MISC_REGISTERS_AEU_ENABLE3_FUNC_0_OUT_3 0xa4UL
+#define MISC_REGISTERS_AEU_ENABLE3_FUNC_0_OUT_4 0xb4UL
+#define MISC_REGISTERS_AEU_ENABLE3_FUNC_0_OUT_5 0xc4UL
+#define MISC_REGISTERS_AEU_ENABLE3_FUNC_0_OUT_6 0xd4UL
+#define MISC_REGISTERS_AEU_ENABLE3_FUNC_0_OUT_7 0xe4UL
+#define MISC_REGISTERS_AEU_ENABLE3_FUNC_1_OUT_0 0x114UL
+#define MISC_REGISTERS_AEU_ENABLE3_FUNC_1_OUT_1 0x124UL
+#define MISC_REGISTERS_AEU_ENABLE3_FUNC_1_OUT_2 0x134UL
+#define MISC_REGISTERS_AEU_ENABLE3_FUNC_1_OUT_3 0x144UL
+#define MISC_REGISTERS_AEU_ENABLE3_FUNC_1_OUT_4 0x154UL
+#define MISC_REGISTERS_AEU_ENABLE3_FUNC_1_OUT_5 0x164UL
+#define MISC_REGISTERS_AEU_ENABLE3_FUNC_1_OUT_6 0x174UL
+#define MISC_REGISTERS_AEU_ENABLE3_FUNC_1_OUT_7 0x184UL
+#define MISC_REGISTERS_AEU_ENABLE3_NIG_0 0xf4UL
+#define MISC_REGISTERS_AEU_ENABLE3_NIG_1 0x194UL
+#define MISC_REGISTERS_AEU_ENABLE3_PXP_0 0x104UL
+#define MISC_REGISTERS_AEU_ENABLE3_PXP_1 0x1a4UL
+#define MISC_REGISTERS_AEU_ENABLE4_FUNC_0_OUT_0 0x78UL
+#define MISC_REGISTERS_AEU_ENABLE4_FUNC_0_OUT_1 0x88UL
+#define MISC_REGISTERS_AEU_ENABLE4_FUNC_0_OUT_2 0x98UL
+#define MISC_REGISTERS_AEU_ENABLE4_FUNC_0_OUT_3 0xa8UL
+#define MISC_REGISTERS_AEU_ENABLE4_FUNC_0_OUT_4 0xb8UL
+#define MISC_REGISTERS_AEU_ENABLE4_FUNC_0_OUT_5 0xc8UL
+#define MISC_REGISTERS_AEU_ENABLE4_FUNC_0_OUT_6 0xd8UL
+#define MISC_REGISTERS_AEU_ENABLE4_FUNC_0_OUT_7 0xe8UL
+#define MISC_REGISTERS_AEU_ENABLE4_FUNC_1_OUT_0 0x118UL
+#define MISC_REGISTERS_AEU_ENABLE4_FUNC_1_OUT_1 0x128UL
+#define MISC_REGISTERS_AEU_ENABLE4_FUNC_1_OUT_2 0x138UL
+#define MISC_REGISTERS_AEU_ENABLE4_FUNC_1_OUT_3 0x148UL
+#define MISC_REGISTERS_AEU_ENABLE4_FUNC_1_OUT_4 0x158UL
+#define MISC_REGISTERS_AEU_ENABLE4_FUNC_1_OUT_5 0x168UL
+#define MISC_REGISTERS_AEU_ENABLE4_FUNC_1_OUT_6 0x178UL
+#define MISC_REGISTERS_AEU_ENABLE4_FUNC_1_OUT_7 0x188UL
+#define MISC_REGISTERS_AEU_ENABLE4_NIG_0 0xf8UL
+#define MISC_REGISTERS_AEU_ENABLE4_NIG_1 0x198UL
+#define MISC_REGISTERS_AEU_ENABLE4_PXP_0 0x108UL
+#define MISC_REGISTERS_AEU_ENABLE4_PXP_1 0x1a8UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_0 0x0UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_1 0x4UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_10 0x28UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_11 0x2cUL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_12 0x30UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_13 0x34UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_14 0x38UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_15 0x3cUL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_16 0x40UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_17 0x44UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_18 0x48UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_19 0x4cUL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_10 0x28UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_11 0x2cUL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_12 0x30UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_13 0x34UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_14 0x38UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_15 0x3cUL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_16 0x40UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_17 0x44UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_18 0x48UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_19 0x4cUL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_2 0x8UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_20 0x50UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_21 0x54UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_20 0x50UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_21 0x54UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_3 0xcUL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_4 0x10UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_5 0x14UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_6 0x18UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_7 0x1cUL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_8 0x20UL
+#define MISC_REGISTERS_AEU_GENERAL_ATTN_9 0x24UL
+#define MISC_REGISTERS_AEU_INVERTER_1_FUNC_0 0x22cUL
+#define MISC_REGISTERS_AEU_INVERTER_1_FUNC_1 0x23cUL
+#define MISC_REGISTERS_AEU_INVERTER_2_FUNC_0 0x230UL
+#define MISC_REGISTERS_AEU_INVERTER_2_FUNC_1 0x240UL
+#define MISC_REGISTERS_AEU_INVERTER_3_FUNC_0 0x234UL
+#define MISC_REGISTERS_AEU_INVERTER_3_FUNC_1 0x244UL
+#define MISC_REGISTERS_AEU_INVERTER_4_FUNC_0 0x238UL
+#define MISC_REGISTERS_AEU_INVERTER_4_FUNC_1 0x248UL
+#define MISC_REGISTERS_AEU_MASK_ATTN_FUNC_0 0x60UL
+#define MISC_REGISTERS_AEU_MASK_ATTN_FUNC_1 0x64UL
+#define MISC_REGISTERS_BOND_ID 0x400UL
+#define MISC_REGISTERS_BOND_ID_SIZE 1
+#define MISC_REGISTERS_CHIP_METAL 0x404UL
+#define MISC_REGISTERS_CHIP_METAL_SIZE 1
+#define MISC_REGISTERS_CHIP_NUM 0x408UL
+#define MISC_REGISTERS_CHIP_NUM_SIZE 1
+#define MISC_REGISTERS_CHIP_REV 0x40cUL
+#define MISC_REGISTERS_CHIP_REV_SIZE 1
+#define MISC_REGISTERS_GRC_TIMEOUT_EN 0x280UL
+#define MISC_REGISTERS_LCPLL_CTRL_1 0x2a4UL
+#define MISC_REGISTERS_LCPLL_CTRL_REG_2 0x2a8UL
+#define MISC_REGISTERS_PLL_STORM_CTRL_1 0x294UL
+#define MISC_REGISTERS_PLL_STORM_CTRL_2 0x298UL
+#define MISC_REGISTERS_PLL_STORM_CTRL_3 0x29cUL
+#define MISC_REGISTERS_PLL_STORM_CTRL_4 0x2a0UL
+#define MISC_REGISTERS_RESET_REG_1 0x580UL
+#define MISC_REGISTERS_RESET_REG_1_SIZE 3
+#define MISC_REGISTERS_RESET_REG_2 0x590UL
+#define MISC_REGISTERS_RESET_REG_2_SIZE 3
+#define MISC_REGISTERS_RESET_REG_3 0x5a0UL
+#define MISC_REGISTERS_RESET_REG_3_SIZE 3
+#define MISC_REGISTERS_RESET_REG_1 0x580UL
+#define MISC_REGISTERS_RESET_REG_1_SIZE 3
+#define MISC_REGISTERS_RESET_REG_2 0x590UL
+#define MISC_REGISTERS_RESET_REG_2_SIZE 3
+#define MISC_REGISTERS_SHARED_MEM_ADDR 0x2b4UL
+#define NIG_MASK_INTERRUPT_PORT0_REGISTERS_MASK_EMAC0_MISC_MI_INT (0x1<<0)
+#define NIG_MASK_INTERRUPT_PORT0_REGISTERS_MASK_EMAC0_MISC_MI_INT_SIZE 0
+#define NIG_MASK_INTERRUPT_PORT0_REGISTERS_MASK_SERDES0_LINK_STATUS 
(0x1<<9)
+#define NIG_MASK_INTERRUPT_PORT0_REGISTERS_MASK_SERDES0_LINK_STATUS_SIZE 9
+#define NIG_MASK_INTERRUPT_PORT0_REGISTERS_MASK_XGXS0_LINK10G (0x1<<15)
+#define NIG_MASK_INTERRUPT_PORT0_REGISTERS_MASK_XGXS0_LINK10G_SIZE 15
+#define NIG_MASK_INTERRUPT_PORT0_REGISTERS_MASK_XGXS0_LINK_STATUS (0xf<<18)
+#define NIG_MASK_INTERRUPT_PORT0_REGISTERS_MASK_XGXS0_LINK_STATUS_SIZE 18
+#define NIG_REGISTERS_BMAC0_IN_EN 0xacUL
+#define NIG_REGISTERS_BMAC0_OUT_EN 0xe0UL
+#define NIG_REGISTERS_BMAC0_PAUSE_OUT_EN 0x110UL
+#define NIG_REGISTERS_BMAC0_REGS_OUT_EN 0xe8UL
+#define NIG_REGISTERS_BRB0_OUT_EN 0xf8UL
+#define NIG_REGISTERS_BRB0_PAUSE_IN_EN 0xc4UL
+#define NIG_REGISTERS_BRB1_OUT_EN 0xfcUL
+#define NIG_REGISTERS_BRB1_PAUSE_IN_EN 0xc8UL
+#define NIG_REGISTERS_BRB_LB_OUT_EN 0x100UL
+#define NIG_REGISTERS_DEBUG_PACKET_LB 0x800UL
+#define NIG_REGISTERS_DEBUG_PACKET_LB_SIZE 3
+#define NIG_REGISTERS_EGRESS_DEBUG_IN_EN 0xdcUL
+#define NIG_REGISTERS_EGRESS_DRAIN0_MODE 0x60UL
+#define NIG_REGISTERS_EGRESS_EMAC0_OUT_EN 0x120UL
+#define NIG_REGISTERS_EGRESS_EMAC0_PORT 0x58UL
+#define NIG_REGISTERS_EGRESS_PBF0_IN_EN 0xccUL
+#define NIG_REGISTERS_EGRESS_PBF1_IN_EN 0xd0UL
+#define NIG_REGISTERS_EMAC0_IN_EN 0xa4UL
+#define NIG_REGISTERS_EMAC0_PAUSE_OUT_EN 0x118UL
+#define NIG_REGISTERS_EMAC0_STATUS_MISC_MI_INT 0x494UL
+#define NIG_REGISTERS_EMAC0_STATUS_MISC_MI_INT_SIZE 1
+#define NIG_REGISTERS_INGRESS_BMAC0_MEM 0xc00UL
+#define NIG_REGISTERS_INGRESS_BMAC0_MEM_SIZE 256
+#define NIG_REGISTERS_INGRESS_BMAC1_MEM 0x1000UL
+#define NIG_REGISTERS_INGRESS_BMAC1_MEM_SIZE 256
+#define NIG_REGISTERS_INGRESS_EOP_LB_EMPTY 0x4e0UL
+#define NIG_REGISTERS_INGRESS_EOP_LB_EMPTY_SIZE 1
+#define NIG_REGISTERS_INGRESS_EOP_LB_FIFO 0x4e4UL
+#define NIG_REGISTERS_INGRESS_EOP_LB_FIFO_SIZE 1
+#define NIG_REGISTERS_LED_10G_P0 0x320UL
+#define NIG_REGISTERS_LED_CONTROL_BLINK_RATE_ENA_P0 0x318UL
+#define NIG_REGISTERS_LED_CONTROL_BLINK_RATE_P0 0x310UL
+#define NIG_REGISTERS_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x2f8UL
+#define NIG_REGISTERS_LED_MODE_P0 0x2f0UL
+#define NIG_REGISTERS_LLH0_BRB1_DRV_MASK 0x244UL
+#define NIG_REGISTERS_LLH0_BRB1_NOT_MCP 0x25cUL
+#define NIG_REGISTERS_LLH0_CM_HEADER 0x7cUL
+#define NIG_REGISTERS_LLH0_ERROR_MASK 0x8cUL
+#define NIG_REGISTERS_LLH0_EVENT_ID 0x84UL
+#define NIG_REGISTERS_LLH0_XCM_INIT_CREDIT 0x554UL
+#define NIG_REGISTERS_LLH0_XCM_INIT_CREDIT_SIZE 1
+#define NIG_REGISTERS_LLH0_XCM_MASK 0x130UL
+#define NIG_REGISTERS_LLH1_BRB1_NOT_MCP 0x2dcUL
+#define NIG_REGISTERS_LLH1_CM_HEADER 0x80UL
+#define NIG_REGISTERS_LLH1_ERROR_MASK 0x90UL
+#define NIG_REGISTERS_LLH1_EVENT_ID 0x88UL
+#define NIG_REGISTERS_LLH1_XCM_INIT_CREDIT 0x564UL
+#define NIG_REGISTERS_LLH1_XCM_INIT_CREDIT_SIZE 1
+#define NIG_REGISTERS_LLH1_XCM_MASK 0x134UL
+#define NIG_REGISTERS_MASK_INTERRUPT_PORT0 0x330UL
+#define NIG_REGISTERS_MASK_INTERRUPT_PORT1 0x334UL
+#define NIG_REGISTERS_NIG_EMAC0_EN 0x3cUL
+#define NIG_REGISTERS_NIG_INGRESS_EMAC0_NO_CRC 0x44UL
+#define NIG_REGISTERS_PBF_LB_IN_EN 0xb4UL
+#define NIG_REGISTERS_PRS_EOP_OUT_EN 0x104UL
+#define NIG_REGISTERS_PRS_REQ_IN_EN 0xb8UL
+#define NIG_REGISTERS_SERDES0_CTRL_PHY_ADDR 0x374UL
+#define NIG_REGISTERS_SERDES0_STATUS_LINK_STATUS 0x578UL
+#define NIG_REGISTERS_SERDES0_STATUS_LINK_STATUS_SIZE 1
+#define NIG_REGISTERS_STAT0_BRB_DISCARD 0x5f0UL
+#define NIG_REGISTERS_STAT0_BRB_DISCARD_SIZE 1
+#define NIG_REGISTERS_STAT1_BRB_DISCARD 0x628UL
+#define NIG_REGISTERS_STAT1_BRB_DISCARD_SIZE 1
+#define NIG_REGISTERS_STAT2_BRB_OCTET 0x7e0UL
+#define NIG_REGISTERS_STAT2_BRB_OCTET_SIZE 2
+#define NIG_REGISTERS_STATUS_INTERRUPT_PORT0 0x328UL
+#define NIG_REGISTERS_STATUS_INTERRUPT_PORT1 0x32cUL
+#define NIG_REGISTERS_XCM0_OUT_EN 0xf0UL
+#define NIG_REGISTERS_XCM1_OUT_EN 0xf4UL
+#define NIG_REGISTERS_XGXS0_CTRL_MD_DEVAD 0x33cUL
+#define NIG_REGISTERS_XGXS0_CTRL_PHY_ADDR 0x340UL
+#define NIG_REGISTERS_XGXS0_STATUS_LINK10G 0x680UL
+#define NIG_REGISTERS_XGXS0_STATUS_LINK10G_SIZE 1
+#define NIG_REGISTERS_XGXS0_STATUS_LINK_STATUS 0x684UL
+#define NIG_REGISTERS_XGXS0_STATUS_LINK_STATUS_SIZE 1
+#define NIG_REGISTERS_XGXS_LANE_SEL_P0 0x2e8UL
+#define NIG_REGISTERS_XGXS_SERDES0_MODE_SEL 0x2e0UL
+#define NIG_STATUS_INTERRUPT_PORT0_REGISTERS_STATUS_SERDES0_LINK_STATUS 
(0x1<<9)
+#define 
NIG_STATUS_INTERRUPT_PORT0_REGISTERS_STATUS_SERDES0_LINK_STATUS_SIZE 9
+#define NIG_STATUS_INTERRUPT_PORT0_REGISTERS_STATUS_XGXS0_LINK10G (0x1<<15)
+#define NIG_STATUS_INTERRUPT_PORT0_REGISTERS_STATUS_XGXS0_LINK10G_SIZE 15
+#define NIG_STATUS_INTERRUPT_PORT0_REGISTERS_STATUS_XGXS0_LINK_STATUS 
(0xf<<18)
+#define 
NIG_STATUS_INTERRUPT_PORT0_REGISTERS_STATUS_XGXS0_LINK_STATUS_SIZE 18
+#define 
NIG_STATUS_INTERRUPT_PORT0_REGISTERS_STATUS_XGXS0_LINK_STATUS_SIZE 18
+#define PBF_REGISTERS_DISABLE_NEW_TASK_PROC_P0 0x5cUL
+#define PBF_REGISTERS_DISABLE_NEW_TASK_PROC_P1 0x60UL
+#define PBF_REGISTERS_DISABLE_NEW_TASK_PROC_P4 0x6cUL
+#define PBF_REGISTERS_IF_ENABLE_REG 0x44UL
+#define PBF_REGISTERS_INIT 0x0UL
+#define PBF_REGISTERS_INIT_P0 0x4UL
+#define PBF_REGISTERS_INIT_P1 0x8UL
+#define PBF_REGISTERS_INIT_P4 0xcUL
+#define PBF_REGISTERS_INIT_P0 0x4UL
+#define PBF_REGISTERS_INIT_P1 0x8UL
+#define PBF_REGISTERS_INIT_P4 0xcUL
+#define PBF_REGISTERS_MAC_IF0_ENABLE 0x30UL
+#define PBF_REGISTERS_MAC_IF1_ENABLE 0x34UL
+#define PBF_REGISTERS_MAC_LB_ENABLE 0x40UL
+#define PBF_REGISTERS_P0_ARB_THRSH 0xe4UL
+#define PBF_REGISTERS_P0_CREDIT 0x200UL
+#define PBF_REGISTERS_P0_CREDIT_SIZE 1
+#define PBF_REGISTERS_P0_INIT_CRD 0xd0UL
+#define PBF_REGISTERS_P0_PAUSE_ENABLE 0x14UL
+#define PBF_REGISTERS_P0_TASK_CNT 0x204UL
+#define PBF_REGISTERS_P0_TASK_CNT_SIZE 1
+#define PBF_REGISTERS_P1_CREDIT 0x208UL
+#define PBF_REGISTERS_P1_CREDIT_SIZE 1
+#define PBF_REGISTERS_P1_INIT_CRD 0xd4UL
+#define PBF_REGISTERS_P1_TASK_CNT 0x20cUL
+#define PBF_REGISTERS_P1_TASK_CNT_SIZE 1
+#define PBF_REGISTERS_P4_CREDIT 0x210UL
+#define PBF_REGISTERS_P4_CREDIT_SIZE 1
+#define PBF_REGISTERS_P4_INIT_CRD 0xe0UL
+#define PBF_REGISTERS_P4_TASK_CNT 0x214UL
+#define PBF_REGISTERS_P4_TASK_CNT_SIZE 1
+#define PBF_REGISTERS_PBF_INT_STS 0x1c8UL
+#define PBF_REGISTERS_PBF_INT_STS_CLR 0x1ccUL
+#define PBF_REGISTERS_PBF_INT_STS_WR 0x1d0UL
+#define PB_REGISTERS_CONTROL 0x0UL
+#define PB_REGISTERS_PB_INT_STS 0x1cUL
+#define PB_REGISTERS_PB_INT_STS_CLR 0x20UL
+#define PB_REGISTERS_PB_INT_STS_WR 0x24UL
+#define PRS_REGISTERS_CFC_LD_CURRENT_CREDIT 0x164UL
+#define PRS_REGISTERS_CFC_SEARCH_CURRENT_CREDIT 0x168UL
+#define PRS_REGISTERS_CFC_SEARCH_INITIAL_CREDIT 0x11cUL
+#define PRS_REGISTERS_CID_PORT_0 0xfcUL
+#define PRS_REGISTERS_CID_PORT_1 0x100UL
+#define PRS_REGISTERS_CM_HDR_FLUSH_LOAD_TYPE_0 0xdcUL
+#define PRS_REGISTERS_CM_HDR_FLUSH_LOAD_TYPE_1 0xe0UL
+#define PRS_REGISTERS_CM_HDR_FLUSH_LOAD_TYPE_2 0xe4UL
+#define PRS_REGISTERS_CM_HDR_FLUSH_LOAD_TYPE_3 0xe8UL
+#define PRS_REGISTERS_CM_HDR_FLUSH_LOAD_TYPE_4 0xecUL
+#define PRS_REGISTERS_CM_HDR_FLUSH_LOAD_TYPE_5 0xf0UL
+#define PRS_REGISTERS_CM_HDR_FLUSH_LOAD_TYPE_6 0xf4UL
+#define PRS_REGISTERS_CM_HDR_FLUSH_LOAD_TYPE_7 0xf8UL
+#define PRS_REGISTERS_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0xbcUL
+#define PRS_REGISTERS_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0xc0UL
+#define PRS_REGISTERS_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0xc4UL
+#define PRS_REGISTERS_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0xc8UL
+#define PRS_REGISTERS_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0xccUL
+#define PRS_REGISTERS_CM_HDR_FLUSH_NO_LOAD_TYPE_5 0xd0UL
+#define PRS_REGISTERS_CM_HDR_FLUSH_NO_LOAD_TYPE_6 0xd4UL
+#define PRS_REGISTERS_CM_HDR_FLUSH_NO_LOAD_TYPE_7 0xd8UL
+#define PRS_REGISTERS_CM_HDR_LOOPBACK_TYPE_0 0x98UL
+#define PRS_REGISTERS_CM_HDR_LOOPBACK_TYPE_1 0x9cUL
+#define PRS_REGISTERS_CM_HDR_LOOPBACK_TYPE_2 0xa0UL
+#define PRS_REGISTERS_CM_HDR_LOOPBACK_TYPE_3 0xa4UL
+#define PRS_REGISTERS_CM_HDR_LOOPBACK_TYPE_4 0xa8UL
+#define PRS_REGISTERS_CM_HDR_LOOPBACK_TYPE_5 0xacUL
+#define PRS_REGISTERS_CM_HDR_LOOPBACK_TYPE_6 0xb0UL
+#define PRS_REGISTERS_CM_HDR_LOOPBACK_TYPE_7 0xb4UL
+#define PRS_REGISTERS_CM_HDR_TYPE_0 0x78UL
+#define PRS_REGISTERS_CM_HDR_TYPE_1 0x7cUL
+#define PRS_REGISTERS_CM_HDR_TYPE_2 0x80UL
+#define PRS_REGISTERS_CM_HDR_TYPE_3 0x84UL
+#define PRS_REGISTERS_CM_HDR_TYPE_4 0x88UL
+#define PRS_REGISTERS_CM_HDR_TYPE_5 0x8cUL
+#define PRS_REGISTERS_CM_HDR_TYPE_6 0x90UL
+#define PRS_REGISTERS_CM_HDR_TYPE_7 0x94UL
+#define PRS_REGISTERS_CM_NO_MATCH_HDR 0xb8UL
+#define PRS_REGISTERS_EVENT_ID_1 0x54UL
+#define PRS_REGISTERS_EVENT_ID_2 0x58UL
+#define PRS_REGISTERS_EVENT_ID_3 0x5cUL
+#define PRS_REGISTERS_FLUSH_REGIONS_TYPE_0 0x4UL
+#define PRS_REGISTERS_FLUSH_REGIONS_TYPE_1 0x8UL
+#define PRS_REGISTERS_FLUSH_REGIONS_TYPE_2 0xcUL
+#define PRS_REGISTERS_FLUSH_REGIONS_TYPE_3 0x10UL
+#define PRS_REGISTERS_FLUSH_REGIONS_TYPE_4 0x14UL
+#define PRS_REGISTERS_FLUSH_REGIONS_TYPE_5 0x18UL
+#define PRS_REGISTERS_FLUSH_REGIONS_TYPE_6 0x1cUL
+#define PRS_REGISTERS_FLUSH_REGIONS_TYPE_7 0x20UL
+#define PRS_REGISTERS_INC_VALUE 0x48UL
+#define PRS_REGISTERS_NIC_MODE 0x138UL
+#define PRS_REGISTERS_NO_MATCH_EVENT_ID 0x70UL
+#define PRS_REGISTERS_NUM_OF_CFC_FLUSH_MESSAGES 0x128UL
+#define PRS_REGISTERS_NUM_OF_DEAD_CYCLES 0x130UL
+#define PRS_REGISTERS_NUM_OF_PACKETS 0x124UL
+#define PRS_REGISTERS_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x12cUL
+#define PRS_REGISTERS_PACKET_REGIONS_TYPE_0 0x28UL
+#define PRS_REGISTERS_PACKET_REGIONS_TYPE_1 0x2cUL
+#define PRS_REGISTERS_PACKET_REGIONS_TYPE_2 0x30UL
+#define PRS_REGISTERS_PACKET_REGIONS_TYPE_3 0x34UL
+#define PRS_REGISTERS_PACKET_REGIONS_TYPE_4 0x38UL
+#define PRS_REGISTERS_PACKET_REGIONS_TYPE_5 0x3cUL
+#define PRS_REGISTERS_PACKET_REGIONS_TYPE_6 0x40UL
+#define PRS_REGISTERS_PACKET_REGIONS_TYPE_7 0x44UL
+#define PRS_REGISTERS_PENDING_BRB_CAC0_RQ 0x174UL
+#define PRS_REGISTERS_PENDING_BRB_CAC1_RQ 0x178UL
+#define PRS_REGISTERS_PENDING_BRB_CAC2_RQ 0x17cUL
+#define PRS_REGISTERS_PENDING_BRB_CAC3_RQ 0x180UL
+#define PRS_REGISTERS_PENDING_BRB_CAC4_RQ 0x184UL
+#define PRS_REGISTERS_PENDING_BRB_PRS_RQ 0x170UL
+#define PRS_REGISTERS_PRS_INT_STS 0x188UL
+#define PRS_REGISTERS_PRS_INT_STS_CLR 0x18cUL
+#define PRS_REGISTERS_PRS_INT_STS_WR 0x190UL
+#define PRS_REGISTERS_PURE_REGIONS 0x24UL
+#define PRS_REGISTERS_SERIAL_NUM_STATUS_LSB 0x154UL
+#define PRS_REGISTERS_SERIAL_NUM_STATUS_MSB 0x158UL
+#define PRS_REGISTERS_SRC_CURRENT_CREDIT 0x16cUL
+#define PRS_REGISTERS_TCM_CURRENT_CREDIT 0x160UL
+#define PRS_REGISTERS_TSDM_CURRENT_CREDIT 0x15cUL
+#define PXP2_REGISTERS_HST_DATA_FIFO_STATUS 0x47cUL
+#define PXP2_REGISTERS_HST_HEADER_FIFO_STATUS 0x478UL
+#define PXP2_REGISTERS_PGL_CONTROL0 0x490UL
+#define PXP2_REGISTERS_PGL_CONTROL1 0x514UL
+#define PXP2_REGISTERS_PGL_INT_CSDM_0 0x4f4UL
+#define PXP2_REGISTERS_PGL_INT_CSDM_1 0x4f8UL
+#define PXP2_REGISTERS_PGL_INT_CSDM_2 0x4fcUL
+#define PXP2_REGISTERS_PGL_INT_CSDM_3 0x500UL
+#define PXP2_REGISTERS_PGL_INT_CSDM_4 0x504UL
+#define PXP2_REGISTERS_PGL_INT_CSDM_5 0x508UL
+#define PXP2_REGISTERS_PGL_INT_CSDM_6 0x50cUL
+#define PXP2_REGISTERS_PGL_INT_CSDM_7 0x510UL
+#define PXP2_REGISTERS_PGL_INT_TSDM_0 0x494UL
+#define PXP2_REGISTERS_PGL_INT_TSDM_1 0x498UL
+#define PXP2_REGISTERS_PGL_INT_TSDM_2 0x49cUL
+#define PXP2_REGISTERS_PGL_INT_TSDM_3 0x4a0UL
+#define PXP2_REGISTERS_PGL_INT_TSDM_4 0x4a4UL
+#define PXP2_REGISTERS_PGL_INT_TSDM_5 0x4a8UL
+#define PXP2_REGISTERS_PGL_INT_TSDM_6 0x4acUL
+#define PXP2_REGISTERS_PGL_INT_TSDM_7 0x4b0UL
+#define PXP2_REGISTERS_PGL_INT_USDM_0 0x4b4UL
+#define PXP2_REGISTERS_PGL_INT_USDM_1 0x4b8UL
+#define PXP2_REGISTERS_PGL_INT_USDM_2 0x4bcUL
+#define PXP2_REGISTERS_PGL_INT_USDM_3 0x4c0UL
+#define PXP2_REGISTERS_PGL_INT_USDM_4 0x4c4UL
+#define PXP2_REGISTERS_PGL_INT_USDM_5 0x4c8UL
+#define PXP2_REGISTERS_PGL_INT_USDM_6 0x4ccUL
+#define PXP2_REGISTERS_PGL_INT_USDM_7 0x4d0UL
+#define PXP2_REGISTERS_PGL_INT_XSDM_0 0x4d4UL
+#define PXP2_REGISTERS_PGL_INT_XSDM_1 0x4d8UL
+#define PXP2_REGISTERS_PGL_INT_XSDM_2 0x4dcUL
+#define PXP2_REGISTERS_PGL_INT_XSDM_3 0x4e0UL
+#define PXP2_REGISTERS_PGL_INT_XSDM_4 0x4e4UL
+#define PXP2_REGISTERS_PGL_INT_XSDM_5 0x4e8UL
+#define PXP2_REGISTERS_PGL_INT_XSDM_6 0x4ecUL
+#define PXP2_REGISTERS_PGL_INT_XSDM_7 0x4f0UL
+#define PXP2_REGISTERS_PGL_READ_BLOCKED 0x568UL
+#define PXP2_REGISTERS_PGL_TXR_CDTS 0x528UL
+#define PXP2_REGISTERS_PGL_TXW_CDTS 0x52cUL
+#define PXP2_REGISTERS_PGL_WRITE_BLOCKED 0x564UL
+#define PXP2_REGISTERS_PSWRQ_BW_ADD1 0x1c0UL
+#define PXP2_REGISTERS_PSWRQ_BW_ADD10 0x1e4UL
+#define PXP2_REGISTERS_PSWRQ_BW_ADD11 0x1e8UL
+#define PXP2_REGISTERS_PSWRQ_BW_ADD10 0x1e4UL
+#define PXP2_REGISTERS_PSWRQ_BW_ADD11 0x1e8UL
+#define PXP2_REGISTERS_PSWRQ_BW_ADD2 0x1c4UL
+#define PXP2_REGISTERS_PSWRQ_BW_ADD28 0x228UL
+#define PXP2_REGISTERS_PSWRQ_BW_ADD28 0x228UL
+#define PXP2_REGISTERS_PSWRQ_BW_ADD3 0x1c8UL
+#define PXP2_REGISTERS_PSWRQ_BW_ADD6 0x1d4UL
+#define PXP2_REGISTERS_PSWRQ_BW_ADD7 0x1d8UL
+#define PXP2_REGISTERS_PSWRQ_BW_ADD8 0x1dcUL
+#define PXP2_REGISTERS_PSWRQ_BW_ADD9 0x1e0UL
+#define PXP2_REGISTERS_PSWRQ_BW_CREDIT 0x32cUL
+#define PXP2_REGISTERS_PSWRQ_BW_L1 0x2b0UL
+#define PXP2_REGISTERS_PSWRQ_BW_L10 0x2d4UL
+#define PXP2_REGISTERS_PSWRQ_BW_L11 0x2d8UL
+#define PXP2_REGISTERS_PSWRQ_BW_L10 0x2d4UL
+#define PXP2_REGISTERS_PSWRQ_BW_L11 0x2d8UL
+#define PXP2_REGISTERS_PSWRQ_BW_L2 0x2b4UL
+#define PXP2_REGISTERS_PSWRQ_BW_L28 0x318UL
+#define PXP2_REGISTERS_PSWRQ_BW_L28 0x318UL
+#define PXP2_REGISTERS_PSWRQ_BW_L3 0x2b8UL
+#define PXP2_REGISTERS_PSWRQ_BW_L6 0x2c4UL
+#define PXP2_REGISTERS_PSWRQ_BW_L7 0x2c8UL
+#define PXP2_REGISTERS_PSWRQ_BW_L8 0x2ccUL
+#define PXP2_REGISTERS_PSWRQ_BW_L9 0x2d0UL
+#define PXP2_REGISTERS_PSWRQ_BW_RD 0x324UL
+#define PXP2_REGISTERS_PSWRQ_BW_UB1 0x238UL
+#define PXP2_REGISTERS_PSWRQ_BW_UB10 0x25cUL
+#define PXP2_REGISTERS_PSWRQ_BW_UB11 0x260UL
+#define PXP2_REGISTERS_PSWRQ_BW_UB10 0x25cUL
+#define PXP2_REGISTERS_PSWRQ_BW_UB11 0x260UL
+#define PXP2_REGISTERS_PSWRQ_BW_UB2 0x23cUL
+#define PXP2_REGISTERS_PSWRQ_BW_UB28 0x2a0UL
+#define PXP2_REGISTERS_PSWRQ_BW_UB28 0x2a0UL
+#define PXP2_REGISTERS_PSWRQ_BW_UB3 0x240UL
+#define PXP2_REGISTERS_PSWRQ_BW_UB6 0x24cUL
+#define PXP2_REGISTERS_PSWRQ_BW_UB7 0x250UL
+#define PXP2_REGISTERS_PSWRQ_BW_UB8 0x254UL
+#define PXP2_REGISTERS_PSWRQ_BW_UB9 0x258UL
+#define PXP2_REGISTERS_PSWRQ_BW_WR 0x328UL
+#define PXP2_REGISTERS_PSWRQ_CDU0_L2P 0x0UL
+#define PXP2_REGISTERS_PSWRQ_CDU1_L2P 0x4UL
+#define PXP2_REGISTERS_PSWRQ_QM0_L2P 0x38UL
+#define PXP2_REGISTERS_PSWRQ_QM1_L2P 0x3cUL
+#define PXP2_REGISTERS_PSWRQ_SRC0_L2P 0x54UL
+#define PXP2_REGISTERS_PSWRQ_SRC1_L2P 0x58UL
+#define PXP2_REGISTERS_PSWRQ_TM0_L2P 0x1cUL
+#define PXP2_REGISTERS_PSWRQ_TM1_L2P 0x20UL
+#define PXP2_REGISTERS_RD_ALMOST_FULL_0 0x424UL
+#define PXP2_REGISTERS_RD_ALMOST_FULL_1 0x428UL
+#define PXP2_REGISTERS_RD_ALMOST_FULL_10 0x44cUL
+#define PXP2_REGISTERS_RD_ALMOST_FULL_10 0x44cUL
+#define PXP2_REGISTERS_RD_ALMOST_FULL_2 0x42cUL
+#define PXP2_REGISTERS_RD_ALMOST_FULL_3 0x430UL
+#define PXP2_REGISTERS_RD_ALMOST_FULL_4 0x434UL
+#define PXP2_REGISTERS_RD_ALMOST_FULL_5 0x438UL
+#define PXP2_REGISTERS_RD_ALMOST_FULL_6 0x43cUL
+#define PXP2_REGISTERS_RD_ALMOST_FULL_7 0x440UL
+#define PXP2_REGISTERS_RD_ALMOST_FULL_8 0x444UL
+#define PXP2_REGISTERS_RD_ALMOST_FULL_9 0x448UL
+#define PXP2_REGISTERS_RD_BLK_CNT 0x418UL
+#define PXP2_REGISTERS_RD_BLK_NUM_CFG 0x40cUL
+#define PXP2_REGISTERS_RD_CDURD_SWAP_MODE 0x404UL
+#define PXP2_REGISTERS_RD_DISABLE_INPUTS 0x374UL
+#define PXP2_REGISTERS_RD_INIT_DONE 0x370UL
+#define PXP2_REGISTERS_RD_MAX_BLKS_VQ10 0x3a0UL
+#define PXP2_REGISTERS_RD_MAX_BLKS_VQ11 0x3a4UL
+#define PXP2_REGISTERS_RD_MAX_BLKS_VQ17 0x3bcUL
+#define PXP2_REGISTERS_RD_MAX_BLKS_VQ18 0x3c0UL
+#define PXP2_REGISTERS_RD_MAX_BLKS_VQ19 0x3c4UL
+#define PXP2_REGISTERS_RD_MAX_BLKS_VQ22 0x3d0UL
+#define PXP2_REGISTERS_RD_MAX_BLKS_VQ6 0x390UL
+#define PXP2_REGISTERS_RD_MAX_BLKS_VQ9 0x39cUL
+#define PXP2_REGISTERS_RD_PBF_SWAP_MODE 0x3f4UL
+#define PXP2_REGISTERS_RD_PORT_IS_IDLE_0 0x41cUL
+#define PXP2_REGISTERS_RD_PORT_IS_IDLE_1 0x420UL
+#define PXP2_REGISTERS_RD_QM_SWAP_MODE 0x3f8UL
+#define PXP2_REGISTERS_RD_SR_CNT 0x414UL
+#define PXP2_REGISTERS_RD_SRC_SWAP_MODE 0x400UL
+#define PXP2_REGISTERS_RD_SR_NUM_CFG 0x408UL
+#define PXP2_REGISTERS_RD_START_INIT 0x36cUL
+#define PXP2_REGISTERS_RD_TM_SWAP_MODE 0x3fcUL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD0 0x1bcUL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD12 0x1ecUL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD13 0x1f0UL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD14 0x1f4UL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD15 0x1f8UL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD16 0x1fcUL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD17 0x200UL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD18 0x204UL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD19 0x208UL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD20 0x20cUL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD22 0x210UL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD23 0x214UL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD24 0x218UL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD25 0x21cUL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD26 0x220UL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD27 0x224UL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD4 0x1ccUL
+#define PXP2_REGISTERS_RQ_BW_RD_ADD5 0x1d0UL
+#define PXP2_REGISTERS_RQ_BW_RD_L0 0x2acUL
+#define PXP2_REGISTERS_RQ_BW_RD_L12 0x2dcUL
+#define PXP2_REGISTERS_RQ_BW_RD_L13 0x2e0UL
+#define PXP2_REGISTERS_RQ_BW_RD_L14 0x2e4UL
+#define PXP2_REGISTERS_RQ_BW_RD_L15 0x2e8UL
+#define PXP2_REGISTERS_RQ_BW_RD_L16 0x2ecUL
+#define PXP2_REGISTERS_RQ_BW_RD_L17 0x2f0UL
+#define PXP2_REGISTERS_RQ_BW_RD_L18 0x2f4UL
+#define PXP2_REGISTERS_RQ_BW_RD_L19 0x2f8UL
+#define PXP2_REGISTERS_RQ_BW_RD_L20 0x2fcUL
+#define PXP2_REGISTERS_RQ_BW_RD_L22 0x300UL
+#define PXP2_REGISTERS_RQ_BW_RD_L23 0x304UL
+#define PXP2_REGISTERS_RQ_BW_RD_L24 0x308UL
+#define PXP2_REGISTERS_RQ_BW_RD_L25 0x30cUL
+#define PXP2_REGISTERS_RQ_BW_RD_L26 0x310UL
+#define PXP2_REGISTERS_RQ_BW_RD_L27 0x314UL
+#define PXP2_REGISTERS_RQ_BW_RD_L4 0x2bcUL
+#define PXP2_REGISTERS_RQ_BW_RD_L5 0x2c0UL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND0 0x234UL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND12 0x264UL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND13 0x268UL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND14 0x26cUL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND15 0x270UL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND16 0x274UL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND17 0x278UL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND18 0x27cUL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND19 0x280UL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND20 0x284UL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND22 0x288UL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND23 0x28cUL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND24 0x290UL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND25 0x294UL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND26 0x298UL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND27 0x29cUL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND4 0x244UL
+#define PXP2_REGISTERS_RQ_BW_RD_UBOUND5 0x248UL
+#define PXP2_REGISTERS_RQ_BW_WR_ADD29 0x22cUL
+#define PXP2_REGISTERS_RQ_BW_WR_ADD30 0x230UL
+#define PXP2_REGISTERS_RQ_BW_WR_L29 0x31cUL
+#define PXP2_REGISTERS_RQ_BW_WR_L30 0x320UL
+#define PXP2_REGISTERS_RQ_BW_WR_UBOUND29 0x2a4UL
+#define PXP2_REGISTERS_RQ_BW_WR_UBOUND30 0x2a8UL
+#define PXP2_REGISTERS_RQ_CDU_ENDIAN_M 0x1a0UL
+#define PXP2_REGISTERS_RQ_CDU_P_SIZE 0x18UL
+#define PXP2_REGISTERS_RQ_CFG_DONE 0x1b4UL
+#define PXP2_REGISTERS_RQ_DBG_ENDIAN_M 0x1a4UL
+#define PXP2_REGISTERS_RQ_DISABLE_INPUTS 0x330UL
+#define PXP2_REGISTERS_RQ_HC_ENDIAN_M 0x1a8UL
+#define PXP2_REGISTERS_RQ_ONCHIP_AT 0x2000UL
+#define PXP2_REGISTERS_RQ_ONCHIP_AT_SIZE 2048
+#define PXP2_REGISTERS_RQ_QM_ENDIAN_M 0x194UL
+#define PXP2_REGISTERS_RQ_QM_P_SIZE 0x50UL
+#define PXP2_REGISTERS_RQ_RBC_DONE 0x1b0UL
+#define PXP2_REGISTERS_RQ_RD_MBS0 0x160UL
+#define PXP2_REGISTERS_RQ_SRC_ENDIAN_M 0x19cUL
+#define PXP2_REGISTERS_RQ_SRC_P_SIZE 0x6cUL
+#define PXP2_REGISTERS_RQ_TM_ENDIAN_M 0x198UL
+#define PXP2_REGISTERS_RQ_TM_P_SIZE 0x34UL
+#define PXP2_REGISTERS_RQ_UFIFO_NUM_OF_ENTRY 0x80cUL
+#define PXP2_REGISTERS_RQ_UFIFO_NUM_OF_ENTRY_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ0_ENTRY_CNT 0x810UL
+#define PXP2_REGISTERS_RQ_VQ0_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ10_ENTRY_CNT 0x818UL
+#define PXP2_REGISTERS_RQ_VQ10_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ11_ENTRY_CNT 0x820UL
+#define PXP2_REGISTERS_RQ_VQ11_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ12_ENTRY_CNT 0x828UL
+#define PXP2_REGISTERS_RQ_VQ12_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ13_ENTRY_CNT 0x830UL
+#define PXP2_REGISTERS_RQ_VQ13_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ14_ENTRY_CNT 0x838UL
+#define PXP2_REGISTERS_RQ_VQ14_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ15_ENTRY_CNT 0x840UL
+#define PXP2_REGISTERS_RQ_VQ15_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ16_ENTRY_CNT 0x848UL
+#define PXP2_REGISTERS_RQ_VQ16_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ17_ENTRY_CNT 0x850UL
+#define PXP2_REGISTERS_RQ_VQ17_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ18_ENTRY_CNT 0x858UL
+#define PXP2_REGISTERS_RQ_VQ18_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ19_ENTRY_CNT 0x860UL
+#define PXP2_REGISTERS_RQ_VQ19_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ1_ENTRY_CNT 0x868UL
+#define PXP2_REGISTERS_RQ_VQ1_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ20_ENTRY_CNT 0x870UL
+#define PXP2_REGISTERS_RQ_VQ20_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ21_ENTRY_CNT 0x878UL
+#define PXP2_REGISTERS_RQ_VQ21_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ22_ENTRY_CNT 0x880UL
+#define PXP2_REGISTERS_RQ_VQ22_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ23_ENTRY_CNT 0x888UL
+#define PXP2_REGISTERS_RQ_VQ23_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ24_ENTRY_CNT 0x890UL
+#define PXP2_REGISTERS_RQ_VQ24_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ25_ENTRY_CNT 0x898UL
+#define PXP2_REGISTERS_RQ_VQ25_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ26_ENTRY_CNT 0x8a0UL
+#define PXP2_REGISTERS_RQ_VQ26_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ27_ENTRY_CNT 0x8a8UL
+#define PXP2_REGISTERS_RQ_VQ27_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ28_ENTRY_CNT 0x8b0UL
+#define PXP2_REGISTERS_RQ_VQ28_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ29_ENTRY_CNT 0x8b8UL
+#define PXP2_REGISTERS_RQ_VQ29_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ2_ENTRY_CNT 0x8c0UL
+#define PXP2_REGISTERS_RQ_VQ2_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ30_ENTRY_CNT 0x8c8UL
+#define PXP2_REGISTERS_RQ_VQ30_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ31_ENTRY_CNT 0x8d0UL
+#define PXP2_REGISTERS_RQ_VQ31_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ3_ENTRY_CNT 0x8d8UL
+#define PXP2_REGISTERS_RQ_VQ3_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ4_ENTRY_CNT 0x8e0UL
+#define PXP2_REGISTERS_RQ_VQ4_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ5_ENTRY_CNT 0x8e8UL
+#define PXP2_REGISTERS_RQ_VQ5_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ6_ENTRY_CNT 0x8f0UL
+#define PXP2_REGISTERS_RQ_VQ6_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ7_ENTRY_CNT 0x8f8UL
+#define PXP2_REGISTERS_RQ_VQ7_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ8_ENTRY_CNT 0x900UL
+#define PXP2_REGISTERS_RQ_VQ8_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_VQ9_ENTRY_CNT 0x908UL
+#define PXP2_REGISTERS_RQ_VQ9_ENTRY_CNT_SIZE 1
+#define PXP2_REGISTERS_RQ_WR_MBS0 0x15cUL
+#define PXP_REGISTERS_HST_ARB_IS_IDLE 0x4UL
+#define PXP_REGISTERS_HST_CLIENTS_WAITING_TO_ARB 0x8UL
+#define PXP_REGISTERS_HST_INBOUND_INT 0x800UL
+#define PXP_REGISTERS_HST_INBOUND_INT_SIZE 512
+#define PXP_REGISTERS_PXP_INT_MASK_0 0x74UL
+#define PXP_REGISTERS_PXP_INT_STS_0 0x68UL
+#define PXP_REGISTERS_PXP_INT_STS_1 0x78UL
+#define PXP_REGISTERS_PXP_INT_STS_CLR_0 0x6cUL
+#define QM_REGISTERS_ACTCTRINITVAL_0 0x40UL
+#define QM_REGISTERS_ACTCTRINITVAL_1 0x44UL
+#define QM_REGISTERS_ACTCTRINITVAL_2 0x48UL
+#define QM_REGISTERS_ACTCTRINITVAL_3 0x4cUL
+#define QM_REGISTERS_BASEADDR 0x900UL
+#define QM_REGISTERS_BASEADDR_SIZE 64
+#define QM_REGISTERS_BYTECRDCOST 0x234UL
+#define QM_REGISTERS_BYTECRDINITVAL 0x238UL
+#define QM_REGISTERS_BYTECRDPORT_LSB 0x228UL
+#define QM_REGISTERS_BYTECRDPORT_MSB 0x224UL
+#define QM_REGISTERS_BYTECREDITAFULLTHR 0x94UL
+#define QM_REGISTERS_CMINITCRD_0 0xccUL
+#define QM_REGISTERS_CMINITCRD_1 0xd0UL
+#define QM_REGISTERS_CMINITCRD_2 0xd4UL
+#define QM_REGISTERS_CMINITCRD_3 0xd8UL
+#define QM_REGISTERS_CMINITCRD_4 0xdcUL
+#define QM_REGISTERS_CMINITCRD_5 0xe0UL
+#define QM_REGISTERS_CMINITCRD_6 0xe4UL
+#define QM_REGISTERS_CMINITCRD_7 0xe8UL
+#define QM_REGISTERS_CMINTEN 0xecUL
+#define QM_REGISTERS_CMINTVOQMASK_0 0x1f4UL
+#define QM_REGISTERS_CMINTVOQMASK_1 0x1f8UL
+#define QM_REGISTERS_CMINTVOQMASK_2 0x1fcUL
+#define QM_REGISTERS_CMINTVOQMASK_3 0x200UL
+#define QM_REGISTERS_CMINTVOQMASK_4 0x204UL
+#define QM_REGISTERS_CMINTVOQMASK_5 0x208UL
+#define QM_REGISTERS_CMINTVOQMASK_6 0x20cUL
+#define QM_REGISTERS_CMINTVOQMASK_7 0x210UL
+#define QM_REGISTERS_CONNNUM_0 0x20UL
+#define QM_REGISTERS_CONNNUM_1 0x24UL
+#define QM_REGISTERS_CTXREG_0 0x30UL
+#define QM_REGISTERS_CTXREG_1 0x34UL
+#define QM_REGISTERS_CTXREG_2 0x38UL
+#define QM_REGISTERS_CTXREG_3 0x3cUL
+#define QM_REGISTERS_ENBYPVOQMASK 0x23cUL
+#define QM_REGISTERS_ENBYTECRD_LSB 0x220UL
+#define QM_REGISTERS_ENBYTECRD_MSB 0x21cUL
+#define QM_REGISTERS_ENSEC 0xf0UL
+#define QM_REGISTERS_FUNCNUMSEL_LSB 0x230UL
+#define QM_REGISTERS_FUNCNUMSEL_MSB 0x22cUL
+#define QM_REGISTERS_HWAEMPTYMASK_LSB 0x218UL
+#define QM_REGISTERS_HWAEMPTYMASK_MSB 0x214UL
+#define QM_REGISTERS_OUTLDREQ 0x804UL
+#define QM_REGISTERS_OUTLDREQ_SIZE 1
+#define QM_REGISTERS_PCIREQAT 0x54UL
+#define QM_REGISTERS_PORT0BYTECRD 0x300UL
+#define QM_REGISTERS_PORT1BYTECRD 0x304UL
+#define QM_REGISTERS_PTRTBL 0xa00UL
+#define QM_REGISTERS_PTRTBL_SIZE 128
+#define QM_REGISTERS_QTASKCTR_0 0x308UL
+#define QM_REGISTERS_QVOQIDX_0 0xf4UL
+#define QM_REGISTERS_QVOQIDX_1 0xf8UL
+#define QM_REGISTERS_QVOQIDX_10 0x11cUL
+#define QM_REGISTERS_QVOQIDX_11 0x120UL
+#define QM_REGISTERS_QVOQIDX_12 0x124UL
+#define QM_REGISTERS_QVOQIDX_13 0x128UL
+#define QM_REGISTERS_QVOQIDX_14 0x12cUL
+#define QM_REGISTERS_QVOQIDX_15 0x130UL
+#define QM_REGISTERS_QVOQIDX_16 0x134UL
+#define QM_REGISTERS_QVOQIDX_17 0x138UL
+#define QM_REGISTERS_QVOQIDX_18 0x13cUL
+#define QM_REGISTERS_QVOQIDX_19 0x140UL
+#define QM_REGISTERS_QVOQIDX_10 0x11cUL
+#define QM_REGISTERS_QVOQIDX_11 0x120UL
+#define QM_REGISTERS_QVOQIDX_12 0x124UL
+#define QM_REGISTERS_QVOQIDX_13 0x128UL
+#define QM_REGISTERS_QVOQIDX_14 0x12cUL
+#define QM_REGISTERS_QVOQIDX_15 0x130UL
+#define QM_REGISTERS_QVOQIDX_16 0x134UL
+#define QM_REGISTERS_QVOQIDX_17 0x138UL
+#define QM_REGISTERS_QVOQIDX_18 0x13cUL
+#define QM_REGISTERS_QVOQIDX_19 0x140UL
+#define QM_REGISTERS_QVOQIDX_2 0xfcUL
+#define QM_REGISTERS_QVOQIDX_20 0x144UL
+#define QM_REGISTERS_QVOQIDX_21 0x148UL
+#define QM_REGISTERS_QVOQIDX_22 0x14cUL
+#define QM_REGISTERS_QVOQIDX_23 0x150UL
+#define QM_REGISTERS_QVOQIDX_24 0x154UL
+#define QM_REGISTERS_QVOQIDX_25 0x158UL
+#define QM_REGISTERS_QVOQIDX_26 0x15cUL
+#define QM_REGISTERS_QVOQIDX_27 0x160UL
+#define QM_REGISTERS_QVOQIDX_28 0x164UL
+#define QM_REGISTERS_QVOQIDX_29 0x168UL
+#define QM_REGISTERS_QVOQIDX_20 0x144UL
+#define QM_REGISTERS_QVOQIDX_21 0x148UL
+#define QM_REGISTERS_QVOQIDX_22 0x14cUL
+#define QM_REGISTERS_QVOQIDX_23 0x150UL
+#define QM_REGISTERS_QVOQIDX_24 0x154UL
+#define QM_REGISTERS_QVOQIDX_25 0x158UL
+#define QM_REGISTERS_QVOQIDX_26 0x15cUL
+#define QM_REGISTERS_QVOQIDX_27 0x160UL
+#define QM_REGISTERS_QVOQIDX_28 0x164UL
+#define QM_REGISTERS_QVOQIDX_29 0x168UL
+#define QM_REGISTERS_QVOQIDX_3 0x100UL
+#define QM_REGISTERS_QVOQIDX_30 0x16cUL
+#define QM_REGISTERS_QVOQIDX_31 0x170UL
+#define QM_REGISTERS_QVOQIDX_32 0x174UL
+#define QM_REGISTERS_QVOQIDX_33 0x178UL
+#define QM_REGISTERS_QVOQIDX_34 0x17cUL
+#define QM_REGISTERS_QVOQIDX_35 0x180UL
+#define QM_REGISTERS_QVOQIDX_36 0x184UL
+#define QM_REGISTERS_QVOQIDX_37 0x188UL
+#define QM_REGISTERS_QVOQIDX_38 0x18cUL
+#define QM_REGISTERS_QVOQIDX_39 0x190UL
+#define QM_REGISTERS_QVOQIDX_30 0x16cUL
+#define QM_REGISTERS_QVOQIDX_31 0x170UL
+#define QM_REGISTERS_QVOQIDX_32 0x174UL
+#define QM_REGISTERS_QVOQIDX_33 0x178UL
+#define QM_REGISTERS_QVOQIDX_34 0x17cUL
+#define QM_REGISTERS_QVOQIDX_35 0x180UL
+#define QM_REGISTERS_QVOQIDX_36 0x184UL
+#define QM_REGISTERS_QVOQIDX_37 0x188UL
+#define QM_REGISTERS_QVOQIDX_38 0x18cUL
+#define QM_REGISTERS_QVOQIDX_39 0x190UL
+#define QM_REGISTERS_QVOQIDX_4 0x104UL
+#define QM_REGISTERS_QVOQIDX_40 0x194UL
+#define QM_REGISTERS_QVOQIDX_41 0x198UL
+#define QM_REGISTERS_QVOQIDX_42 0x19cUL
+#define QM_REGISTERS_QVOQIDX_43 0x1a0UL
+#define QM_REGISTERS_QVOQIDX_44 0x1a4UL
+#define QM_REGISTERS_QVOQIDX_45 0x1a8UL
+#define QM_REGISTERS_QVOQIDX_46 0x1acUL
+#define QM_REGISTERS_QVOQIDX_47 0x1b0UL
+#define QM_REGISTERS_QVOQIDX_48 0x1b4UL
+#define QM_REGISTERS_QVOQIDX_49 0x1b8UL
+#define QM_REGISTERS_QVOQIDX_40 0x194UL
+#define QM_REGISTERS_QVOQIDX_41 0x198UL
+#define QM_REGISTERS_QVOQIDX_42 0x19cUL
+#define QM_REGISTERS_QVOQIDX_43 0x1a0UL
+#define QM_REGISTERS_QVOQIDX_44 0x1a4UL
+#define QM_REGISTERS_QVOQIDX_45 0x1a8UL
+#define QM_REGISTERS_QVOQIDX_46 0x1acUL
+#define QM_REGISTERS_QVOQIDX_47 0x1b0UL
+#define QM_REGISTERS_QVOQIDX_48 0x1b4UL
+#define QM_REGISTERS_QVOQIDX_49 0x1b8UL
+#define QM_REGISTERS_QVOQIDX_5 0x108UL
+#define QM_REGISTERS_QVOQIDX_50 0x1bcUL
+#define QM_REGISTERS_QVOQIDX_51 0x1c0UL
+#define QM_REGISTERS_QVOQIDX_52 0x1c4UL
+#define QM_REGISTERS_QVOQIDX_53 0x1c8UL
+#define QM_REGISTERS_QVOQIDX_54 0x1ccUL
+#define QM_REGISTERS_QVOQIDX_55 0x1d0UL
+#define QM_REGISTERS_QVOQIDX_56 0x1d4UL
+#define QM_REGISTERS_QVOQIDX_57 0x1d8UL
+#define QM_REGISTERS_QVOQIDX_58 0x1dcUL
+#define QM_REGISTERS_QVOQIDX_59 0x1e0UL
+#define QM_REGISTERS_QVOQIDX_50 0x1bcUL
+#define QM_REGISTERS_QVOQIDX_51 0x1c0UL
+#define QM_REGISTERS_QVOQIDX_52 0x1c4UL
+#define QM_REGISTERS_QVOQIDX_53 0x1c8UL
+#define QM_REGISTERS_QVOQIDX_54 0x1ccUL
+#define QM_REGISTERS_QVOQIDX_55 0x1d0UL
+#define QM_REGISTERS_QVOQIDX_56 0x1d4UL
+#define QM_REGISTERS_QVOQIDX_57 0x1d8UL
+#define QM_REGISTERS_QVOQIDX_58 0x1dcUL
+#define QM_REGISTERS_QVOQIDX_59 0x1e0UL
+#define QM_REGISTERS_QVOQIDX_6 0x10cUL
+#define QM_REGISTERS_QVOQIDX_60 0x1e4UL
+#define QM_REGISTERS_QVOQIDX_61 0x1e8UL
+#define QM_REGISTERS_QVOQIDX_62 0x1ecUL
+#define QM_REGISTERS_QVOQIDX_63 0x1f0UL
+#define QM_REGISTERS_QVOQIDX_60 0x1e4UL
+#define QM_REGISTERS_QVOQIDX_61 0x1e8UL
+#define QM_REGISTERS_QVOQIDX_62 0x1ecUL
+#define QM_REGISTERS_QVOQIDX_63 0x1f0UL
+#define QM_REGISTERS_QVOQIDX_7 0x110UL
+#define QM_REGISTERS_QVOQIDX_8 0x114UL
+#define QM_REGISTERS_QVOQIDX_9 0x118UL
+#define QM_REGISTERS_SOFT_RESET 0x428UL
+#define QM_REGISTERS_TASKCRDCOST_0 0x9cUL
+#define QM_REGISTERS_TASKCRDCOST_1 0xa0UL
+#define QM_REGISTERS_TASKCRDCOST_10 0xc4UL
+#define QM_REGISTERS_TASKCRDCOST_11 0xc8UL
+#define QM_REGISTERS_TASKCRDCOST_10 0xc4UL
+#define QM_REGISTERS_TASKCRDCOST_11 0xc8UL
+#define QM_REGISTERS_TASKCRDCOST_2 0xa4UL
+#define QM_REGISTERS_TASKCRDCOST_3 0xa8UL
+#define QM_REGISTERS_TASKCRDCOST_4 0xacUL
+#define QM_REGISTERS_TASKCRDCOST_5 0xb0UL
+#define QM_REGISTERS_TASKCRDCOST_6 0xb4UL
+#define QM_REGISTERS_TASKCRDCOST_7 0xb8UL
+#define QM_REGISTERS_TASKCRDCOST_8 0xbcUL
+#define QM_REGISTERS_TASKCRDCOST_9 0xc0UL
+#define QM_REGISTERS_VOQCRDERRREG 0x408UL
+#define QM_REGISTERS_VOQCREDIT_0 0x2d0UL
+#define QM_REGISTERS_VOQCREDIT_1 0x2d4UL
+#define QM_REGISTERS_VOQCREDIT_10 0x2f8UL
+#define QM_REGISTERS_VOQCREDIT_11 0x2fcUL
+#define QM_REGISTERS_VOQCREDIT_4 0x2e0UL
+#define QM_REGISTERS_VOQCREDITAFULLTHR 0x90UL
+#define QM_REGISTERS_VOQINITCREDIT_0 0x60UL
+#define QM_REGISTERS_VOQINITCREDIT_1 0x64UL
+#define QM_REGISTERS_VOQINITCREDIT_10 0x88UL
+#define QM_REGISTERS_VOQINITCREDIT_11 0x8cUL
+#define QM_REGISTERS_VOQINITCREDIT_10 0x88UL
+#define QM_REGISTERS_VOQINITCREDIT_11 0x8cUL
+#define QM_REGISTERS_VOQINITCREDIT_2 0x68UL
+#define QM_REGISTERS_VOQINITCREDIT_3 0x6cUL
+#define QM_REGISTERS_VOQINITCREDIT_4 0x70UL
+#define QM_REGISTERS_VOQINITCREDIT_5 0x74UL
+#define QM_REGISTERS_VOQINITCREDIT_6 0x78UL
+#define QM_REGISTERS_VOQINITCREDIT_7 0x7cUL
+#define QM_REGISTERS_VOQINITCREDIT_8 0x80UL
+#define QM_REGISTERS_VOQINITCREDIT_9 0x84UL
+#define QM_REGISTERS_VOQPORT_0 0x2a0UL
+#define QM_REGISTERS_VOQPORT_1 0x2a4UL
+#define QM_REGISTERS_VOQPORT_10 0x2c8UL
+#define QM_REGISTERS_VOQPORT_11 0x2ccUL
+#define QM_REGISTERS_VOQPORT_10 0x2c8UL
+#define QM_REGISTERS_VOQPORT_11 0x2ccUL
+#define QM_REGISTERS_VOQPORT_2 0x2a8UL
+#define QM_REGISTERS_VOQPORT_3 0x2acUL
+#define QM_REGISTERS_VOQPORT_4 0x2b0UL
+#define QM_REGISTERS_VOQPORT_5 0x2b4UL
+#define QM_REGISTERS_VOQPORT_6 0x2b8UL
+#define QM_REGISTERS_VOQPORT_7 0x2bcUL
+#define QM_REGISTERS_VOQPORT_8 0x2c0UL
+#define QM_REGISTERS_VOQPORT_9 0x2c4UL
+#define QM_REGISTERS_VOQQMASK_0_LSB 0x240UL
+#define QM_REGISTERS_VOQQMASK_0_MSB 0x244UL
+#define QM_REGISTERS_VOQQMASK_10_LSB 0x290UL
+#define QM_REGISTERS_VOQQMASK_10_MSB 0x294UL
+#define QM_REGISTERS_VOQQMASK_11_LSB 0x298UL
+#define QM_REGISTERS_VOQQMASK_11_MSB 0x29cUL
+#define QM_REGISTERS_VOQQMASK_1_LSB 0x248UL
+#define QM_REGISTERS_VOQQMASK_1_MSB 0x24cUL
+#define QM_REGISTERS_VOQQMASK_2_LSB 0x250UL
+#define QM_REGISTERS_VOQQMASK_2_MSB 0x254UL
+#define QM_REGISTERS_VOQQMASK_3_LSB 0x258UL
+#define QM_REGISTERS_VOQQMASK_3_MSB 0x25cUL
+#define QM_REGISTERS_VOQQMASK_4_LSB 0x260UL
+#define QM_REGISTERS_VOQQMASK_4_MSB 0x264UL
+#define QM_REGISTERS_VOQQMASK_5_LSB 0x268UL
+#define QM_REGISTERS_VOQQMASK_5_MSB 0x26cUL
+#define QM_REGISTERS_VOQQMASK_6_LSB 0x270UL
+#define QM_REGISTERS_VOQQMASK_6_MSB 0x274UL
+#define QM_REGISTERS_VOQQMASK_7_LSB 0x278UL
+#define QM_REGISTERS_VOQQMASK_7_MSB 0x27cUL
+#define QM_REGISTERS_VOQQMASK_8_LSB 0x280UL
+#define QM_REGISTERS_VOQQMASK_8_MSB 0x284UL
+#define QM_REGISTERS_VOQQMASK_9_LSB 0x288UL
+#define QM_REGISTERS_VOQQMASK_9_MSB 0x28cUL
+#define QM_REGISTERS_WRRWEIGHTS_0 0x80cUL
+#define QM_REGISTERS_WRRWEIGHTS_0_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_1 0x810UL
+#define QM_REGISTERS_WRRWEIGHTS_1_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_10 0x814UL
+#define QM_REGISTERS_WRRWEIGHTS_10_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_11 0x818UL
+#define QM_REGISTERS_WRRWEIGHTS_11_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_12 0x81cUL
+#define QM_REGISTERS_WRRWEIGHTS_12_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_13 0x820UL
+#define QM_REGISTERS_WRRWEIGHTS_13_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_14 0x824UL
+#define QM_REGISTERS_WRRWEIGHTS_14_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_15 0x828UL
+#define QM_REGISTERS_WRRWEIGHTS_15_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_10 0x814UL
+#define QM_REGISTERS_WRRWEIGHTS_10_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_11 0x818UL
+#define QM_REGISTERS_WRRWEIGHTS_11_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_12 0x81cUL
+#define QM_REGISTERS_WRRWEIGHTS_12_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_13 0x820UL
+#define QM_REGISTERS_WRRWEIGHTS_13_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_14 0x824UL
+#define QM_REGISTERS_WRRWEIGHTS_14_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_15 0x828UL
+#define QM_REGISTERS_WRRWEIGHTS_15_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_2 0x82cUL
+#define QM_REGISTERS_WRRWEIGHTS_2_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_3 0x830UL
+#define QM_REGISTERS_WRRWEIGHTS_3_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_4 0x834UL
+#define QM_REGISTERS_WRRWEIGHTS_4_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_5 0x838UL
+#define QM_REGISTERS_WRRWEIGHTS_5_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_6 0x83cUL
+#define QM_REGISTERS_WRRWEIGHTS_6_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_7 0x840UL
+#define QM_REGISTERS_WRRWEIGHTS_7_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_8 0x844UL
+#define QM_REGISTERS_WRRWEIGHTS_8_SIZE 1
+#define QM_REGISTERS_WRRWEIGHTS_9 0x848UL
+#define QM_REGISTERS_WRRWEIGHTS_9_SIZE 1
+#define SRC_REGISTERS_COUNTFREE0 0x100UL
+#define SRC_REGISTERS_COUNTFREE0_SIZE 1
+#define SRC_REGISTERS_FIRSTFREE0 0x110UL
+#define SRC_REGISTERS_FIRSTFREE0_SIZE 2
+#define SRC_REGISTERS_KEYRSS0_0 0x8UL
+#define SRC_REGISTERS_KEYRSS1_9 0x54UL
+#define SRC_REGISTERS_LASTFREE0 0x130UL
+#define SRC_REGISTERS_LASTFREE0_SIZE 2
+#define SRC_REGISTERS_NUMBER_HASH_BITS0 0x0UL
+#define SRC_REGISTERS_SOFT_RST 0x9cUL
+#define SRC_REGISTERS_SRC_INT_STS 0xacUL
+#define SRC_REGISTERS_SRC_INT_STS_CLR 0xb0UL
+#define SRC_REGISTERS_SRC_INT_STS_WR 0xb4UL
+#define TCM_REGISTERS_CAM_OCCUP 0x17cUL
+#define TCM_REGISTERS_CAM_OCCUP_ST 0x200UL
+#define TCM_REGISTERS_CAM_OCCUP_ST_SIZE 1
+#define TCM_REGISTERS_CDU_AG_RD_IFEN 0x34UL
+#define TCM_REGISTERS_CDU_AG_WR_IFEN 0x30UL
+#define TCM_REGISTERS_CDU_SM_RD_IFEN 0x3cUL
+#define TCM_REGISTERS_CDU_SM_WR_IFEN 0x38UL
+#define TCM_REGISTERS_CFC_INIT_CRD 0x204UL
+#define TCM_REGISTERS_CFC_INIT_CRD_SIZE 1
+#define TCM_REGISTERS_CP_WEIGHT 0xc0UL
+#define TCM_REGISTERS_CSEM_IFEN 0x2cUL
+#define TCM_REGISTERS_CSEM_LENGTH_MIS 0x174UL
+#define TCM_REGISTERS_ERR_EVNT_ID 0xa0UL
+#define TCM_REGISTERS_ERR_TCM_HDR 0x9cUL
+#define TCM_REGISTERS_EXPR_EVNT_ID 0xa4UL
+#define TCM_REGISTERS_FIC0_INIT_CRD 0x20cUL
+#define TCM_REGISTERS_FIC0_INIT_CRD_SIZE 1
+#define TCM_REGISTERS_FIC1_INIT_CRD 0x210UL
+#define TCM_REGISTERS_FIC1_INIT_CRD_SIZE 1
+#define TCM_REGISTERS_GR_ARB_TYPE 0x114UL
+#define TCM_REGISTERS_GR_LD0_PR 0x11cUL
+#define TCM_REGISTERS_GR_LD1_PR 0x120UL
+#define TCM_REGISTERS_N_SM_CTX_LD_0 0x50UL
+#define TCM_REGISTERS_N_SM_CTX_LD_1 0x54UL
+#define TCM_REGISTERS_N_SM_CTX_LD_10 0x78UL
+#define TCM_REGISTERS_N_SM_CTX_LD_11 0x7cUL
+#define TCM_REGISTERS_N_SM_CTX_LD_12 0x80UL
+#define TCM_REGISTERS_N_SM_CTX_LD_13 0x84UL
+#define TCM_REGISTERS_N_SM_CTX_LD_14 0x88UL
+#define TCM_REGISTERS_N_SM_CTX_LD_15 0x8cUL
+#define TCM_REGISTERS_N_SM_CTX_LD_2 0x58UL
+#define TCM_REGISTERS_N_SM_CTX_LD_3 0x5cUL
+#define TCM_REGISTERS_N_SM_CTX_LD_4 0x60UL
+#define TCM_REGISTERS_N_SM_CTX_LD_5 0x64UL
+#define TCM_REGISTERS_N_SM_CTX_LD_6 0x68UL
+#define TCM_REGISTERS_N_SM_CTX_LD_7 0x6cUL
+#define TCM_REGISTERS_PBF_IFEN 0x24UL
+#define TCM_REGISTERS_PBF_LENGTH_MIS 0x16cUL
+#define TCM_REGISTERS_PBF_WEIGHT 0xb4UL
+#define TCM_REGISTERS_PHYS_QNUM0_0 0xe0UL
+#define TCM_REGISTERS_PHYS_QNUM0_1 0xe4UL
+#define TCM_REGISTERS_PHYS_QNUM1_0 0xe8UL
+#define TCM_REGISTERS_PHYS_QNUM1_1 0xecUL
+#define TCM_REGISTERS_PHYS_QNUM2_0 0xf0UL
+#define TCM_REGISTERS_PHYS_QNUM2_1 0xf4UL
+#define TCM_REGISTERS_PHYS_QNUM3_0 0xf8UL
+#define TCM_REGISTERS_PHYS_QNUM3_1 0xfcUL
+#define TCM_REGISTERS_PRS_IFEN 0x20UL
+#define TCM_REGISTERS_PRS_LENGTH_MIS 0x168UL
+#define TCM_REGISTERS_PRS_WEIGHT 0xb0UL
+#define TCM_REGISTERS_STOP_EVNT_ID 0xa8UL
+#define TCM_REGISTERS_STORM_LENGTH_MIS 0x160UL
+#define TCM_REGISTERS_STORM_TCM_IFEN 0x10UL
+#define TCM_REGISTERS_TCM_CFC_IFEN 0x40UL
+#define TCM_REGISTERS_TCM_INT_STS 0x1d0UL
+#define TCM_REGISTERS_TCM_INT_STS_CLR 0x1d4UL
+#define TCM_REGISTERS_TCM_INT_STS_WR 0x1d8UL
+#define TCM_REGISTERS_TCM_REG0_SZ 0xd8UL
+#define TCM_REGISTERS_TCM_STORM0_IFEN 0x4UL
+#define TCM_REGISTERS_TCM_STORM1_IFEN 0x8UL
+#define TCM_REGISTERS_TCM_TQM_IFEN 0xcUL
+#define TCM_REGISTERS_TCM_TQM_USE_Q 0xd4UL
+#define TCM_REGISTERS_TM_TCM_HDR 0x98UL
+#define TCM_REGISTERS_TM_TCM_IFEN 0x1cUL
+#define TCM_REGISTERS_TQM_INIT_CRD 0x21cUL
+#define TCM_REGISTERS_TQM_INIT_CRD_SIZE 1
+#define TCM_REGISTERS_TQM_TCM_HDR_P 0x90UL
+#define TCM_REGISTERS_TQM_TCM_HDR_S 0x94UL
+#define TCM_REGISTERS_TQM_TCM_IFEN 0x14UL
+#define TCM_REGISTERS_TSDM_IFEN 0x18UL
+#define TCM_REGISTERS_TSDM_LENGTH_MIS 0x164UL
+#define TCM_REGISTERS_TSDM_WEIGHT 0xc4UL
+#define TCM_REGISTERS_USEM_IFEN 0x28UL
+#define TCM_REGISTERS_USEM_LENGTH_MIS 0x170UL
+#define TCM_REGISTERS_XX_DESCR_TABLE 0x280UL
+#define TCM_REGISTERS_XX_DESCR_TABLE_SIZE 32
+#define TCM_REGISTERS_XX_INIT_CRD 0x220UL
+#define TCM_REGISTERS_XX_INIT_CRD_SIZE 1
+#define TCM_REGISTERS_XX_MAX_LL_SZ 0x44UL
+#define TCM_REGISTERS_XX_MSG_NUM 0x224UL
+#define TCM_REGISTERS_XX_MSG_NUM_SIZE 1
+#define TCM_REGISTERS_XX_OVFL_EVNT_ID 0x48UL
+#define TCM_REGISTERS_XX_TABLE 0x240UL
+#define TCM_REGISTERS_XX_TABLE_SIZE 10
+#define TM_REGISTERS_CFC_AC_CRDCNT_VAL 0x208UL
+#define TM_REGISTERS_CFC_AC_CRDCNT_VAL_SIZE 1
+#define TM_REGISTERS_CFC_CLD_CRDCNT_VAL 0x210UL
+#define TM_REGISTERS_CFC_CLD_CRDCNT_VAL_SIZE 1
+#define TM_REGISTERS_CL0_CONT_REGION 0x30UL
+#define TM_REGISTERS_CL1_CONT_REGION 0x34UL
+#define TM_REGISTERS_CL2_CONT_REGION 0x38UL
+#define TM_REGISTERS_CLIN_PRIOR0_CLIENT 0x24UL
+#define TM_REGISTERS_CLIN_PRIOR1_CLIENT 0x28UL
+#define TM_REGISTERS_CLOUT_CRDCNT0_VAL 0x220UL
+#define TM_REGISTERS_CLOUT_CRDCNT0_VAL_SIZE 1
+#define TM_REGISTERS_CLOUT_CRDCNT1_VAL 0x228UL
+#define TM_REGISTERS_CLOUT_CRDCNT1_VAL_SIZE 1
+#define TM_REGISTERS_CLOUT_CRDCNT2_VAL 0x230UL
+#define TM_REGISTERS_CLOUT_CRDCNT2_VAL_SIZE 1
+#define TM_REGISTERS_EN_CL0_INPUT 0x8UL
+#define TM_REGISTERS_EN_CL1_INPUT 0xcUL
+#define TM_REGISTERS_EN_CL2_INPUT 0x10UL
+#define TM_REGISTERS_EN_LINEAR0_TIMER 0x14UL
+#define TM_REGISTERS_EN_LINEAR1_TIMER 0x18UL
+#define TM_REGISTERS_EN_REAL_TIME_CNT 0xd8UL
+#define TM_REGISTERS_EN_TIMERS 0x0UL
+#define TM_REGISTERS_EXP_CRDCNT_VAL 0x238UL
+#define TM_REGISTERS_EXP_CRDCNT_VAL_SIZE 1
+#define TM_REGISTERS_LIN0_MAX_ACTIVE_CID 0x48UL
+#define TM_REGISTERS_LIN0_PHY_ADDR_VALID 0x248UL
+#define TM_REGISTERS_LIN0_PHY_ADDR_VALID_SIZE 1
+#define TM_REGISTERS_LIN0_PHY_ADDR 0x270UL
+#define TM_REGISTERS_LIN0_PHY_ADDR_SIZE 2
+#define TM_REGISTERS_LIN0_SCAN_TIME 0x3cUL
+#define TM_REGISTERS_LIN1_PHY_ADDR_VALID 0x258UL
+#define TM_REGISTERS_LIN1_PHY_ADDR_VALID_SIZE 1
+#define TM_REGISTERS_LIN1_PHY_ADDR 0x280UL
+#define TM_REGISTERS_LIN1_PHY_ADDR_SIZE 2
+#define TM_REGISTERS_LIN_SETCLR_FIFO_ALFULL_THR 0x70UL
+#define TM_REGISTERS_PCIARB_CRDCNT_VAL 0x260UL
+#define TM_REGISTERS_PCIARB_CRDCNT_VAL_SIZE 1
+#define TM_REGISTERS_TIMER_SOFT_RST 0x4UL
+#define TM_REGISTERS_TIMER_TICK_SIZE 0x1cUL
+#define TM_REGISTERS_TM_CONTEXT_REGION 0x44UL
+#define TM_REGISTERS_TM_INT_STS 0xf0UL
+#define TM_REGISTERS_TM_INT_STS_CLR 0xf4UL
+#define TM_REGISTERS_TM_INT_STS_WR 0xf8UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_0 0x38UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_1 0x3cUL
+#define TSDM_REGISTERS_AGG_INT_EVENT_10 0x60UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_11 0x64UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_12 0x68UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_13 0x6cUL
+#define TSDM_REGISTERS_AGG_INT_EVENT_14 0x70UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_15 0x74UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_16 0x78UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_17 0x7cUL
+#define TSDM_REGISTERS_AGG_INT_EVENT_18 0x80UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_19 0x84UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_10 0x60UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_11 0x64UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_12 0x68UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_13 0x6cUL
+#define TSDM_REGISTERS_AGG_INT_EVENT_14 0x70UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_15 0x74UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_16 0x78UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_17 0x7cUL
+#define TSDM_REGISTERS_AGG_INT_EVENT_18 0x80UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_19 0x84UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_2 0x40UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_20 0x88UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_21 0x8cUL
+#define TSDM_REGISTERS_AGG_INT_EVENT_22 0x90UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_23 0x94UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_24 0x98UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_25 0x9cUL
+#define TSDM_REGISTERS_AGG_INT_EVENT_26 0xa0UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_27 0xa4UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_28 0xa8UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_29 0xacUL
+#define TSDM_REGISTERS_AGG_INT_EVENT_20 0x88UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_21 0x8cUL
+#define TSDM_REGISTERS_AGG_INT_EVENT_22 0x90UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_23 0x94UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_24 0x98UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_25 0x9cUL
+#define TSDM_REGISTERS_AGG_INT_EVENT_26 0xa0UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_27 0xa4UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_28 0xa8UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_29 0xacUL
+#define TSDM_REGISTERS_AGG_INT_EVENT_3 0x44UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_30 0xb0UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_31 0xb4UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_30 0xb0UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_31 0xb4UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_4 0x48UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_5 0x4cUL
+#define TSDM_REGISTERS_AGG_INT_EVENT_6 0x50UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_7 0x54UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_8 0x58UL
+#define TSDM_REGISTERS_AGG_INT_EVENT_9 0x5cUL
+#define TSDM_REGISTERS_AGG_INT_FIC_0 0x138UL
+#define TSDM_REGISTERS_AGG_INT_FIC_1 0x13cUL
+#define TSDM_REGISTERS_AGG_INT_FIC_10 0x160UL
+#define TSDM_REGISTERS_AGG_INT_FIC_11 0x164UL
+#define TSDM_REGISTERS_AGG_INT_FIC_12 0x168UL
+#define TSDM_REGISTERS_AGG_INT_FIC_13 0x16cUL
+#define TSDM_REGISTERS_AGG_INT_FIC_14 0x170UL
+#define TSDM_REGISTERS_AGG_INT_FIC_15 0x174UL
+#define TSDM_REGISTERS_AGG_INT_FIC_16 0x178UL
+#define TSDM_REGISTERS_AGG_INT_FIC_17 0x17cUL
+#define TSDM_REGISTERS_AGG_INT_FIC_18 0x180UL
+#define TSDM_REGISTERS_AGG_INT_FIC_19 0x184UL
+#define TSDM_REGISTERS_AGG_INT_FIC_10 0x160UL
+#define TSDM_REGISTERS_AGG_INT_FIC_11 0x164UL
+#define TSDM_REGISTERS_AGG_INT_FIC_12 0x168UL
+#define TSDM_REGISTERS_AGG_INT_FIC_13 0x16cUL
+#define TSDM_REGISTERS_AGG_INT_FIC_14 0x170UL
+#define TSDM_REGISTERS_AGG_INT_FIC_15 0x174UL
+#define TSDM_REGISTERS_AGG_INT_FIC_16 0x178UL
+#define TSDM_REGISTERS_AGG_INT_FIC_17 0x17cUL
+#define TSDM_REGISTERS_AGG_INT_FIC_18 0x180UL
+#define TSDM_REGISTERS_AGG_INT_FIC_19 0x184UL
+#define TSDM_REGISTERS_AGG_INT_FIC_2 0x140UL
+#define TSDM_REGISTERS_AGG_INT_FIC_20 0x188UL
+#define TSDM_REGISTERS_AGG_INT_FIC_21 0x18cUL
+#define TSDM_REGISTERS_AGG_INT_FIC_22 0x190UL
+#define TSDM_REGISTERS_AGG_INT_FIC_23 0x194UL
+#define TSDM_REGISTERS_AGG_INT_FIC_24 0x198UL
+#define TSDM_REGISTERS_AGG_INT_FIC_25 0x19cUL
+#define TSDM_REGISTERS_AGG_INT_FIC_26 0x1a0UL
+#define TSDM_REGISTERS_AGG_INT_FIC_27 0x1a4UL
+#define TSDM_REGISTERS_AGG_INT_FIC_28 0x1a8UL
+#define TSDM_REGISTERS_AGG_INT_FIC_29 0x1acUL
+#define TSDM_REGISTERS_AGG_INT_FIC_20 0x188UL
+#define TSDM_REGISTERS_AGG_INT_FIC_21 0x18cUL
+#define TSDM_REGISTERS_AGG_INT_FIC_22 0x190UL
+#define TSDM_REGISTERS_AGG_INT_FIC_23 0x194UL
+#define TSDM_REGISTERS_AGG_INT_FIC_24 0x198UL
+#define TSDM_REGISTERS_AGG_INT_FIC_25 0x19cUL
+#define TSDM_REGISTERS_AGG_INT_FIC_26 0x1a0UL
+#define TSDM_REGISTERS_AGG_INT_FIC_27 0x1a4UL
+#define TSDM_REGISTERS_AGG_INT_FIC_28 0x1a8UL
+#define TSDM_REGISTERS_AGG_INT_FIC_29 0x1acUL
+#define TSDM_REGISTERS_AGG_INT_FIC_3 0x144UL
+#define TSDM_REGISTERS_AGG_INT_FIC_30 0x1b0UL
+#define TSDM_REGISTERS_AGG_INT_FIC_31 0x1b4UL
+#define TSDM_REGISTERS_AGG_INT_FIC_30 0x1b0UL
+#define TSDM_REGISTERS_AGG_INT_FIC_31 0x1b4UL
+#define TSDM_REGISTERS_AGG_INT_FIC_4 0x148UL
+#define TSDM_REGISTERS_AGG_INT_FIC_5 0x14cUL
+#define TSDM_REGISTERS_AGG_INT_FIC_6 0x150UL
+#define TSDM_REGISTERS_AGG_INT_FIC_7 0x154UL
+#define TSDM_REGISTERS_AGG_INT_FIC_8 0x158UL
+#define TSDM_REGISTERS_AGG_INT_FIC_9 0x15cUL
+#define TSDM_REGISTERS_AGG_INT_MODE_0 0x1b8UL
+#define TSDM_REGISTERS_AGG_INT_MODE_1 0x1bcUL
+#define TSDM_REGISTERS_AGG_INT_MODE_10 0x1e0UL
+#define TSDM_REGISTERS_AGG_INT_MODE_11 0x1e4UL
+#define TSDM_REGISTERS_AGG_INT_MODE_12 0x1e8UL
+#define TSDM_REGISTERS_AGG_INT_MODE_13 0x1ecUL
+#define TSDM_REGISTERS_AGG_INT_MODE_14 0x1f0UL
+#define TSDM_REGISTERS_AGG_INT_MODE_15 0x1f4UL
+#define TSDM_REGISTERS_AGG_INT_MODE_16 0x1f8UL
+#define TSDM_REGISTERS_AGG_INT_MODE_17 0x1fcUL
+#define TSDM_REGISTERS_AGG_INT_MODE_18 0x200UL
+#define TSDM_REGISTERS_AGG_INT_MODE_19 0x204UL
+#define TSDM_REGISTERS_AGG_INT_MODE_10 0x1e0UL
+#define TSDM_REGISTERS_AGG_INT_MODE_11 0x1e4UL
+#define TSDM_REGISTERS_AGG_INT_MODE_12 0x1e8UL
+#define TSDM_REGISTERS_AGG_INT_MODE_13 0x1ecUL
+#define TSDM_REGISTERS_AGG_INT_MODE_14 0x1f0UL
+#define TSDM_REGISTERS_AGG_INT_MODE_15 0x1f4UL
+#define TSDM_REGISTERS_AGG_INT_MODE_16 0x1f8UL
+#define TSDM_REGISTERS_AGG_INT_MODE_17 0x1fcUL
+#define TSDM_REGISTERS_AGG_INT_MODE_18 0x200UL
+#define TSDM_REGISTERS_AGG_INT_MODE_19 0x204UL
+#define TSDM_REGISTERS_AGG_INT_MODE_2 0x1c0UL
+#define TSDM_REGISTERS_AGG_INT_MODE_20 0x208UL
+#define TSDM_REGISTERS_AGG_INT_MODE_21 0x20cUL
+#define TSDM_REGISTERS_AGG_INT_MODE_22 0x210UL
+#define TSDM_REGISTERS_AGG_INT_MODE_23 0x214UL
+#define TSDM_REGISTERS_AGG_INT_MODE_24 0x218UL
+#define TSDM_REGISTERS_AGG_INT_MODE_25 0x21cUL
+#define TSDM_REGISTERS_AGG_INT_MODE_26 0x220UL
+#define TSDM_REGISTERS_AGG_INT_MODE_27 0x224UL
+#define TSDM_REGISTERS_AGG_INT_MODE_28 0x228UL
+#define TSDM_REGISTERS_AGG_INT_MODE_29 0x22cUL
+#define TSDM_REGISTERS_AGG_INT_MODE_20 0x208UL
+#define TSDM_REGISTERS_AGG_INT_MODE_21 0x20cUL
+#define TSDM_REGISTERS_AGG_INT_MODE_22 0x210UL
+#define TSDM_REGISTERS_AGG_INT_MODE_23 0x214UL
+#define TSDM_REGISTERS_AGG_INT_MODE_24 0x218UL
+#define TSDM_REGISTERS_AGG_INT_MODE_25 0x21cUL
+#define TSDM_REGISTERS_AGG_INT_MODE_26 0x220UL
+#define TSDM_REGISTERS_AGG_INT_MODE_27 0x224UL
+#define TSDM_REGISTERS_AGG_INT_MODE_28 0x228UL
+#define TSDM_REGISTERS_AGG_INT_MODE_29 0x22cUL
+#define TSDM_REGISTERS_AGG_INT_MODE_3 0x1c4UL
+#define TSDM_REGISTERS_AGG_INT_MODE_30 0x230UL
+#define TSDM_REGISTERS_AGG_INT_MODE_31 0x234UL
+#define TSDM_REGISTERS_AGG_INT_MODE_30 0x230UL
+#define TSDM_REGISTERS_AGG_INT_MODE_31 0x234UL
+#define TSDM_REGISTERS_AGG_INT_MODE_4 0x1c8UL
+#define TSDM_REGISTERS_AGG_INT_MODE_5 0x1ccUL
+#define TSDM_REGISTERS_AGG_INT_MODE_6 0x1d0UL
+#define TSDM_REGISTERS_AGG_INT_MODE_7 0x1d4UL
+#define TSDM_REGISTERS_AGG_INT_MODE_8 0x1d8UL
+#define TSDM_REGISTERS_AGG_INT_MODE_9 0x1dcUL
+#define TSDM_REGISTERS_AGG_INT_T_0 0xb8UL
+#define TSDM_REGISTERS_AGG_INT_T_1 0xbcUL
+#define TSDM_REGISTERS_AGG_INT_T_10 0xe0UL
+#define TSDM_REGISTERS_AGG_INT_T_11 0xe4UL
+#define TSDM_REGISTERS_AGG_INT_T_12 0xe8UL
+#define TSDM_REGISTERS_AGG_INT_T_13 0xecUL
+#define TSDM_REGISTERS_AGG_INT_T_14 0xf0UL
+#define TSDM_REGISTERS_AGG_INT_T_15 0xf4UL
+#define TSDM_REGISTERS_AGG_INT_T_16 0xf8UL
+#define TSDM_REGISTERS_AGG_INT_T_17 0xfcUL
+#define TSDM_REGISTERS_AGG_INT_T_18 0x100UL
+#define TSDM_REGISTERS_AGG_INT_T_19 0x104UL
+#define TSDM_REGISTERS_AGG_INT_T_10 0xe0UL
+#define TSDM_REGISTERS_AGG_INT_T_11 0xe4UL
+#define TSDM_REGISTERS_AGG_INT_T_12 0xe8UL
+#define TSDM_REGISTERS_AGG_INT_T_13 0xecUL
+#define TSDM_REGISTERS_AGG_INT_T_14 0xf0UL
+#define TSDM_REGISTERS_AGG_INT_T_15 0xf4UL
+#define TSDM_REGISTERS_AGG_INT_T_16 0xf8UL
+#define TSDM_REGISTERS_AGG_INT_T_17 0xfcUL
+#define TSDM_REGISTERS_AGG_INT_T_18 0x100UL
+#define TSDM_REGISTERS_AGG_INT_T_19 0x104UL
+#define TSDM_REGISTERS_AGG_INT_T_2 0xc0UL
+#define TSDM_REGISTERS_AGG_INT_T_20 0x108UL
+#define TSDM_REGISTERS_AGG_INT_T_21 0x10cUL
+#define TSDM_REGISTERS_AGG_INT_T_22 0x110UL
+#define TSDM_REGISTERS_AGG_INT_T_23 0x114UL
+#define TSDM_REGISTERS_AGG_INT_T_24 0x118UL
+#define TSDM_REGISTERS_AGG_INT_T_25 0x11cUL
+#define TSDM_REGISTERS_AGG_INT_T_26 0x120UL
+#define TSDM_REGISTERS_AGG_INT_T_27 0x124UL
+#define TSDM_REGISTERS_AGG_INT_T_28 0x128UL
+#define TSDM_REGISTERS_AGG_INT_T_29 0x12cUL
+#define TSDM_REGISTERS_AGG_INT_T_20 0x108UL
+#define TSDM_REGISTERS_AGG_INT_T_21 0x10cUL
+#define TSDM_REGISTERS_AGG_INT_T_22 0x110UL
+#define TSDM_REGISTERS_AGG_INT_T_23 0x114UL
+#define TSDM_REGISTERS_AGG_INT_T_24 0x118UL
+#define TSDM_REGISTERS_AGG_INT_T_25 0x11cUL
+#define TSDM_REGISTERS_AGG_INT_T_26 0x120UL
+#define TSDM_REGISTERS_AGG_INT_T_27 0x124UL
+#define TSDM_REGISTERS_AGG_INT_T_28 0x128UL
+#define TSDM_REGISTERS_AGG_INT_T_29 0x12cUL
+#define TSDM_REGISTERS_AGG_INT_T_3 0xc4UL
+#define TSDM_REGISTERS_AGG_INT_T_30 0x130UL
+#define TSDM_REGISTERS_AGG_INT_T_31 0x134UL
+#define TSDM_REGISTERS_AGG_INT_T_30 0x130UL
+#define TSDM_REGISTERS_AGG_INT_T_31 0x134UL
+#define TSDM_REGISTERS_AGG_INT_T_4 0xc8UL
+#define TSDM_REGISTERS_AGG_INT_T_5 0xccUL
+#define TSDM_REGISTERS_AGG_INT_T_6 0xd0UL
+#define TSDM_REGISTERS_AGG_INT_T_7 0xd4UL
+#define TSDM_REGISTERS_AGG_INT_T_8 0xd8UL
+#define TSDM_REGISTERS_AGG_INT_T_9 0xdcUL
+#define TSDM_REGISTERS_CFC_RSP_START_ADDR 0x8UL
+#define TSDM_REGISTERS_CMP_COUNTER_MAX0 0x1cUL
+#define TSDM_REGISTERS_CMP_COUNTER_MAX1 0x20UL
+#define TSDM_REGISTERS_CMP_COUNTER_MAX2 0x24UL
+#define TSDM_REGISTERS_CMP_COUNTER_MAX3 0x28UL
+#define TSDM_REGISTERS_CMP_COUNTER_START_ADDR 0xcUL
+#define TSDM_REGISTERS_ENABLE_IN1 0x238UL
+#define TSDM_REGISTERS_ENABLE_IN2 0x23cUL
+#define TSDM_REGISTERS_ENABLE_OUT1 0x240UL
+#define TSDM_REGISTERS_ENABLE_OUT2 0x244UL
+#define TSDM_REGISTERS_NUM_OF_ACK_AFTER_PLACE 0x27cUL
+#define TSDM_REGISTERS_NUM_OF_PKT_END_MSG 0x274UL
+#define TSDM_REGISTERS_NUM_OF_PXP_ASYNC_REQ 0x278UL
+#define TSDM_REGISTERS_NUM_OF_Q0_CMD 0x248UL
+#define TSDM_REGISTERS_NUM_OF_Q10_CMD 0x26cUL
+#define TSDM_REGISTERS_NUM_OF_Q11_CMD 0x270UL
+#define TSDM_REGISTERS_NUM_OF_Q1_CMD 0x24cUL
+#define TSDM_REGISTERS_NUM_OF_Q3_CMD 0x250UL
+#define TSDM_REGISTERS_NUM_OF_Q4_CMD 0x254UL
+#define TSDM_REGISTERS_NUM_OF_Q5_CMD 0x258UL
+#define TSDM_REGISTERS_NUM_OF_Q6_CMD 0x25cUL
+#define TSDM_REGISTERS_NUM_OF_Q7_CMD 0x260UL
+#define TSDM_REGISTERS_NUM_OF_Q8_CMD 0x264UL
+#define TSDM_REGISTERS_NUM_OF_Q9_CMD 0x268UL
+#define TSDM_REGISTERS_PCK_END_MSG_START_ADDR 0x14UL
+#define TSDM_REGISTERS_Q_COUNTER_START_ADDR 0x10UL
+#define TSDM_REGISTERS_RSP_PXP_CTRL_RDATA_EMPTY 0x548UL
+#define TSDM_REGISTERS_RSP_PXP_CTRL_RDATA_EMPTY_SIZE 1
+#define TSDM_REGISTERS_SYNC_PARSER_EMPTY 0x550UL
+#define TSDM_REGISTERS_SYNC_PARSER_EMPTY_SIZE 1
+#define TSDM_REGISTERS_SYNC_SYNC_EMPTY 0x558UL
+#define TSDM_REGISTERS_SYNC_SYNC_EMPTY_SIZE 1
+#define TSDM_REGISTERS_TIMER_TICK 0x0UL
+#define TSEM_REGISTERS_ARB_CYCLE_SIZE 0x34UL
+#define TSEM_REGISTERS_ARB_ELEMENT0 0x20UL
+#define TSEM_REGISTERS_ARB_ELEMENT1 0x24UL
+#define TSEM_REGISTERS_ARB_ELEMENT2 0x28UL
+#define TSEM_REGISTERS_ARB_ELEMENT3 0x2cUL
+#define TSEM_REGISTERS_ARB_ELEMENT4 0x30UL
+#define TSEM_REGISTERS_ENABLE_IN 0xa4UL
+#define TSEM_REGISTERS_ENABLE_OUT 0xa8UL
+#define TSEM_REGISTERS_FAST_MEMORY 0x20000UL
+#define TSEM_REGISTERS_FAST_MEMORY_SIZE 32768
+#define TSEM_REGISTERS_FIC0_DISABLE 0x224UL
+#define TSEM_REGISTERS_FIC0_DISABLE_SIZE 1
+#define TSEM_REGISTERS_FIC1_DISABLE 0x234UL
+#define TSEM_REGISTERS_FIC1_DISABLE_SIZE 1
+#define TSEM_REGISTERS_INT_TABLE_TM 0xc4UL
+#define TSEM_REGISTERS_INT_TABLE 0x400UL
+#define TSEM_REGISTERS_INT_TABLE_SIZE 256
+#define TSEM_REGISTERS_MSG_NUM_FIC0 0x0UL
+#define TSEM_REGISTERS_MSG_NUM_FIC1 0x4UL
+#define TSEM_REGISTERS_MSG_NUM_FOC0 0x8UL
+#define TSEM_REGISTERS_MSG_NUM_FOC1 0xcUL
+#define TSEM_REGISTERS_MSG_NUM_FOC2 0x10UL
+#define TSEM_REGISTERS_MSG_NUM_FOC3 0x14UL
+#define TSEM_REGISTERS_PAS_DISABLE 0x24cUL
+#define TSEM_REGISTERS_PAS_DISABLE_SIZE 1
+#define TSEM_REGISTERS_PASSIVE_BUFFER 0x1000UL
+#define TSEM_REGISTERS_PASSIVE_BUFFER_SIZE 1024
+#define TSEM_REGISTERS_PRAM 0x40000UL
+#define TSEM_REGISTERS_PRAM_SIZE 65536
+#define TSEM_REGISTERS_SLEEP_THREADS_VALID 0x26cUL
+#define TSEM_REGISTERS_SLEEP_THREADS_VALID_SIZE 1
+#define TSEM_REGISTERS_SLOW_EXT_STORE_EMPTY 0x2a0UL
+#define TSEM_REGISTERS_SLOW_EXT_STORE_EMPTY_SIZE 1
+#define TSEM_REGISTERS_THREADS_LIST 0x2e4UL
+#define TSEM_REGISTERS_THREADS_LIST_SIZE 1
+#define TSEM_REGISTERS_TS_0_AS 0x38UL
+#define TSEM_REGISTERS_TS_10_AS 0x60UL
+#define TSEM_REGISTERS_TS_11_AS 0x64UL
+#define TSEM_REGISTERS_TS_12_AS 0x68UL
+#define TSEM_REGISTERS_TS_13_AS 0x6cUL
+#define TSEM_REGISTERS_TS_14_AS 0x70UL
+#define TSEM_REGISTERS_TS_15_AS 0x74UL
+#define TSEM_REGISTERS_TS_16_AS 0x78UL
+#define TSEM_REGISTERS_TS_17_AS 0x7cUL
+#define TSEM_REGISTERS_TS_18_AS 0x80UL
+#define TSEM_REGISTERS_TS_19_AS 0x84UL
+#define TSEM_REGISTERS_TS_1_AS 0x3cUL
+#define TSEM_REGISTERS_TS_2_AS 0x40UL
+#define TSEM_REGISTERS_TS_3_AS 0x44UL
+#define TSEM_REGISTERS_TS_4_AS 0x48UL
+#define TSEM_REGISTERS_TS_5_AS 0x4cUL
+#define TSEM_REGISTERS_TS_6_AS 0x50UL
+#define TSEM_REGISTERS_TS_7_AS 0x54UL
+#define TSEM_REGISTERS_TS_8_AS 0x58UL
+#define TSEM_REGISTERS_TS_9_AS 0x5cUL
+#define UCM_REGISTERS_CAM_OCCUP 0x170UL
+#define UCM_REGISTERS_CAM_OCCUP_ST 0x200UL
+#define UCM_REGISTERS_CAM_OCCUP_ST_SIZE 1
+#define UCM_REGISTERS_CDU_AG_RD_IFEN 0x38UL
+#define UCM_REGISTERS_CDU_AG_WR_IFEN 0x34UL
+#define UCM_REGISTERS_CDU_SM_RD_IFEN 0x40UL
+#define UCM_REGISTERS_CDU_SM_WR_IFEN 0x3cUL
+#define UCM_REGISTERS_CFC_INIT_CRD 0x204UL
+#define UCM_REGISTERS_CFC_INIT_CRD_SIZE 1
+#define UCM_REGISTERS_CP_WEIGHT 0xc4UL
+#define UCM_REGISTERS_CSEM_IFEN 0x28UL
+#define UCM_REGISTERS_CSEM_LENGTH_MIS 0x160UL
+#define UCM_REGISTERS_CSEM_WEIGHT 0xb8UL
+#define UCM_REGISTERS_DORQ_IFEN 0x30UL
+#define UCM_REGISTERS_DORQ_LENGTH_MIS 0x168UL
+#define UCM_REGISTERS_ERR_EVNT_ID 0xa4UL
+#define UCM_REGISTERS_ERR_UCM_HDR 0xa0UL
+#define UCM_REGISTERS_EXPR_EVNT_ID 0xa8UL
+#define UCM_REGISTERS_FIC0_INIT_CRD 0x20cUL
+#define UCM_REGISTERS_FIC0_INIT_CRD_SIZE 1
+#define UCM_REGISTERS_FIC1_INIT_CRD 0x210UL
+#define UCM_REGISTERS_FIC1_INIT_CRD_SIZE 1
+#define UCM_REGISTERS_GR_ARB_TYPE 0x144UL
+#define UCM_REGISTERS_GR_LD0_PR 0x14cUL
+#define UCM_REGISTERS_GR_LD1_PR 0x150UL
+#define UCM_REGISTERS_INV_CFLG_Q 0xe4UL
+#define UCM_REGISTERS_N_SM_CTX_LD_0 0x54UL
+#define UCM_REGISTERS_N_SM_CTX_LD_1 0x58UL
+#define UCM_REGISTERS_N_SM_CTX_LD_10 0x7cUL
+#define UCM_REGISTERS_N_SM_CTX_LD_11 0x80UL
+#define UCM_REGISTERS_N_SM_CTX_LD_12 0x84UL
+#define UCM_REGISTERS_N_SM_CTX_LD_13 0x88UL
+#define UCM_REGISTERS_N_SM_CTX_LD_14 0x8cUL
+#define UCM_REGISTERS_N_SM_CTX_LD_15 0x90UL
+#define UCM_REGISTERS_N_SM_CTX_LD_2 0x5cUL
+#define UCM_REGISTERS_N_SM_CTX_LD_3 0x60UL
+#define UCM_REGISTERS_N_SM_CTX_LD_4 0x64UL
+#define UCM_REGISTERS_N_SM_CTX_LD_5 0x68UL
+#define UCM_REGISTERS_N_SM_CTX_LD_6 0x6cUL
+#define UCM_REGISTERS_N_SM_CTX_LD_7 0x70UL
+#define UCM_REGISTERS_PHYS_QNUM0_0 0x110UL
+#define UCM_REGISTERS_PHYS_QNUM0_1 0x114UL
+#define UCM_REGISTERS_PHYS_QNUM1_0 0x118UL
+#define UCM_REGISTERS_PHYS_QNUM1_1 0x11cUL
+#define UCM_REGISTERS_STOP_EVNT_ID 0xacUL
+#define UCM_REGISTERS_STORM_LENGTH_MIS 0x154UL
+#define UCM_REGISTERS_STORM_UCM_IFEN 0x10UL
+#define UCM_REGISTERS_TM_INIT_CRD 0x21cUL
+#define UCM_REGISTERS_TM_INIT_CRD_SIZE 1
+#define UCM_REGISTERS_TM_UCM_HDR 0x9cUL
+#define UCM_REGISTERS_TM_UCM_IFEN 0x1cUL
+#define UCM_REGISTERS_TSEM_IFEN 0x24UL
+#define UCM_REGISTERS_TSEM_LENGTH_MIS 0x15cUL
+#define UCM_REGISTERS_TSEM_WEIGHT 0xb4UL
+#define UCM_REGISTERS_UCM_CFC_IFEN 0x44UL
+#define UCM_REGISTERS_UCM_INT_STS 0x1c8UL
+#define UCM_REGISTERS_UCM_INT_STS_CLR 0x1ccUL
+#define UCM_REGISTERS_UCM_INT_STS_WR 0x1d0UL
+#define UCM_REGISTERS_UCM_REG0_SZ 0xdcUL
+#define UCM_REGISTERS_UCM_STORM0_IFEN 0x4UL
+#define UCM_REGISTERS_UCM_STORM1_IFEN 0x8UL
+#define UCM_REGISTERS_UCM_TM_IFEN 0x20UL
+#define UCM_REGISTERS_UCM_UQM_IFEN 0xcUL
+#define UCM_REGISTERS_UCM_UQM_USE_Q 0xd8UL
+#define UCM_REGISTERS_UQM_INIT_CRD 0x220UL
+#define UCM_REGISTERS_UQM_INIT_CRD_SIZE 1
+#define UCM_REGISTERS_UQM_P_WEIGHT 0xccUL
+#define UCM_REGISTERS_UQM_UCM_HDR_P 0x94UL
+#define UCM_REGISTERS_UQM_UCM_HDR_S 0x98UL
+#define UCM_REGISTERS_UQM_UCM_IFEN 0x14UL
+#define UCM_REGISTERS_USDM_IFEN 0x18UL
+#define UCM_REGISTERS_USDM_LENGTH_MIS 0x158UL
+#define UCM_REGISTERS_XSEM_IFEN 0x2cUL
+#define UCM_REGISTERS_XSEM_LENGTH_MIS 0x164UL
+#define UCM_REGISTERS_XX_DESCR_TABLE 0x280UL
+#define UCM_REGISTERS_XX_DESCR_TABLE_SIZE 32
+#define UCM_REGISTERS_XX_INIT_CRD 0x224UL
+#define UCM_REGISTERS_XX_INIT_CRD_SIZE 1
+#define UCM_REGISTERS_XX_MSG_NUM 0x228UL
+#define UCM_REGISTERS_XX_MSG_NUM_SIZE 1
+#define UCM_REGISTERS_XX_OVFL_EVNT_ID 0x4cUL
+#define UCM_REGISTERS_XX_TABLE 0x300UL
+#define UCM_REGISTERS_XX_TABLE_SIZE 18
+#define USDM_REGISTERS_AGG_INT_EVENT_0 0x38UL
+#define USDM_REGISTERS_AGG_INT_EVENT_1 0x3cUL
+#define USDM_REGISTERS_AGG_INT_EVENT_10 0x60UL
+#define USDM_REGISTERS_AGG_INT_EVENT_11 0x64UL
+#define USDM_REGISTERS_AGG_INT_EVENT_12 0x68UL
+#define USDM_REGISTERS_AGG_INT_EVENT_13 0x6cUL
+#define USDM_REGISTERS_AGG_INT_EVENT_14 0x70UL
+#define USDM_REGISTERS_AGG_INT_EVENT_15 0x74UL
+#define USDM_REGISTERS_AGG_INT_EVENT_16 0x78UL
+#define USDM_REGISTERS_AGG_INT_EVENT_17 0x7cUL
+#define USDM_REGISTERS_AGG_INT_EVENT_18 0x80UL
+#define USDM_REGISTERS_AGG_INT_EVENT_19 0x84UL
+#define USDM_REGISTERS_AGG_INT_EVENT_10 0x60UL
+#define USDM_REGISTERS_AGG_INT_EVENT_11 0x64UL
+#define USDM_REGISTERS_AGG_INT_EVENT_12 0x68UL
+#define USDM_REGISTERS_AGG_INT_EVENT_13 0x6cUL
+#define USDM_REGISTERS_AGG_INT_EVENT_14 0x70UL
+#define USDM_REGISTERS_AGG_INT_EVENT_15 0x74UL
+#define USDM_REGISTERS_AGG_INT_EVENT_16 0x78UL
+#define USDM_REGISTERS_AGG_INT_EVENT_17 0x7cUL
+#define USDM_REGISTERS_AGG_INT_EVENT_18 0x80UL
+#define USDM_REGISTERS_AGG_INT_EVENT_19 0x84UL
+#define USDM_REGISTERS_AGG_INT_EVENT_2 0x40UL
+#define USDM_REGISTERS_AGG_INT_EVENT_20 0x88UL
+#define USDM_REGISTERS_AGG_INT_EVENT_21 0x8cUL
+#define USDM_REGISTERS_AGG_INT_EVENT_22 0x90UL
+#define USDM_REGISTERS_AGG_INT_EVENT_23 0x94UL
+#define USDM_REGISTERS_AGG_INT_EVENT_24 0x98UL
+#define USDM_REGISTERS_AGG_INT_EVENT_25 0x9cUL
+#define USDM_REGISTERS_AGG_INT_EVENT_26 0xa0UL
+#define USDM_REGISTERS_AGG_INT_EVENT_27 0xa4UL
+#define USDM_REGISTERS_AGG_INT_EVENT_28 0xa8UL
+#define USDM_REGISTERS_AGG_INT_EVENT_29 0xacUL
+#define USDM_REGISTERS_AGG_INT_EVENT_20 0x88UL
+#define USDM_REGISTERS_AGG_INT_EVENT_21 0x8cUL
+#define USDM_REGISTERS_AGG_INT_EVENT_22 0x90UL
+#define USDM_REGISTERS_AGG_INT_EVENT_23 0x94UL
+#define USDM_REGISTERS_AGG_INT_EVENT_24 0x98UL
+#define USDM_REGISTERS_AGG_INT_EVENT_25 0x9cUL
+#define USDM_REGISTERS_AGG_INT_EVENT_26 0xa0UL
+#define USDM_REGISTERS_AGG_INT_EVENT_27 0xa4UL
+#define USDM_REGISTERS_AGG_INT_EVENT_28 0xa8UL
+#define USDM_REGISTERS_AGG_INT_EVENT_29 0xacUL
+#define USDM_REGISTERS_AGG_INT_EVENT_3 0x44UL
+#define USDM_REGISTERS_AGG_INT_EVENT_30 0xb0UL
+#define USDM_REGISTERS_AGG_INT_EVENT_31 0xb4UL
+#define USDM_REGISTERS_AGG_INT_EVENT_30 0xb0UL
+#define USDM_REGISTERS_AGG_INT_EVENT_31 0xb4UL
+#define USDM_REGISTERS_AGG_INT_EVENT_4 0x48UL
+#define USDM_REGISTERS_AGG_INT_EVENT_5 0x4cUL
+#define USDM_REGISTERS_AGG_INT_EVENT_6 0x50UL
+#define USDM_REGISTERS_AGG_INT_EVENT_7 0x54UL
+#define USDM_REGISTERS_AGG_INT_EVENT_8 0x58UL
+#define USDM_REGISTERS_AGG_INT_EVENT_9 0x5cUL
+#define USDM_REGISTERS_AGG_INT_FIC_0 0x138UL
+#define USDM_REGISTERS_AGG_INT_FIC_1 0x13cUL
+#define USDM_REGISTERS_AGG_INT_FIC_10 0x160UL
+#define USDM_REGISTERS_AGG_INT_FIC_11 0x164UL
+#define USDM_REGISTERS_AGG_INT_FIC_12 0x168UL
+#define USDM_REGISTERS_AGG_INT_FIC_13 0x16cUL
+#define USDM_REGISTERS_AGG_INT_FIC_14 0x170UL
+#define USDM_REGISTERS_AGG_INT_FIC_15 0x174UL
+#define USDM_REGISTERS_AGG_INT_FIC_16 0x178UL
+#define USDM_REGISTERS_AGG_INT_FIC_17 0x17cUL
+#define USDM_REGISTERS_AGG_INT_FIC_18 0x180UL
+#define USDM_REGISTERS_AGG_INT_FIC_19 0x184UL
+#define USDM_REGISTERS_AGG_INT_FIC_10 0x160UL
+#define USDM_REGISTERS_AGG_INT_FIC_11 0x164UL
+#define USDM_REGISTERS_AGG_INT_FIC_12 0x168UL
+#define USDM_REGISTERS_AGG_INT_FIC_13 0x16cUL
+#define USDM_REGISTERS_AGG_INT_FIC_14 0x170UL
+#define USDM_REGISTERS_AGG_INT_FIC_15 0x174UL
+#define USDM_REGISTERS_AGG_INT_FIC_16 0x178UL
+#define USDM_REGISTERS_AGG_INT_FIC_17 0x17cUL
+#define USDM_REGISTERS_AGG_INT_FIC_18 0x180UL
+#define USDM_REGISTERS_AGG_INT_FIC_19 0x184UL
+#define USDM_REGISTERS_AGG_INT_FIC_2 0x140UL
+#define USDM_REGISTERS_AGG_INT_FIC_20 0x188UL
+#define USDM_REGISTERS_AGG_INT_FIC_21 0x18cUL
+#define USDM_REGISTERS_AGG_INT_FIC_22 0x190UL
+#define USDM_REGISTERS_AGG_INT_FIC_23 0x194UL
+#define USDM_REGISTERS_AGG_INT_FIC_24 0x198UL
+#define USDM_REGISTERS_AGG_INT_FIC_25 0x19cUL
+#define USDM_REGISTERS_AGG_INT_FIC_26 0x1a0UL
+#define USDM_REGISTERS_AGG_INT_FIC_27 0x1a4UL
+#define USDM_REGISTERS_AGG_INT_FIC_28 0x1a8UL
+#define USDM_REGISTERS_AGG_INT_FIC_29 0x1acUL
+#define USDM_REGISTERS_AGG_INT_FIC_20 0x188UL
+#define USDM_REGISTERS_AGG_INT_FIC_21 0x18cUL
+#define USDM_REGISTERS_AGG_INT_FIC_22 0x190UL
+#define USDM_REGISTERS_AGG_INT_FIC_23 0x194UL
+#define USDM_REGISTERS_AGG_INT_FIC_24 0x198UL
+#define USDM_REGISTERS_AGG_INT_FIC_25 0x19cUL
+#define USDM_REGISTERS_AGG_INT_FIC_26 0x1a0UL
+#define USDM_REGISTERS_AGG_INT_FIC_27 0x1a4UL
+#define USDM_REGISTERS_AGG_INT_FIC_28 0x1a8UL
+#define USDM_REGISTERS_AGG_INT_FIC_29 0x1acUL
+#define USDM_REGISTERS_AGG_INT_FIC_3 0x144UL
+#define USDM_REGISTERS_AGG_INT_FIC_30 0x1b0UL
+#define USDM_REGISTERS_AGG_INT_FIC_31 0x1b4UL
+#define USDM_REGISTERS_AGG_INT_FIC_30 0x1b0UL
+#define USDM_REGISTERS_AGG_INT_FIC_31 0x1b4UL
+#define USDM_REGISTERS_AGG_INT_FIC_4 0x148UL
+#define USDM_REGISTERS_AGG_INT_FIC_5 0x14cUL
+#define USDM_REGISTERS_AGG_INT_FIC_6 0x150UL
+#define USDM_REGISTERS_AGG_INT_FIC_7 0x154UL
+#define USDM_REGISTERS_AGG_INT_FIC_8 0x158UL
+#define USDM_REGISTERS_AGG_INT_FIC_9 0x15cUL
+#define USDM_REGISTERS_AGG_INT_MODE_0 0x1b8UL
+#define USDM_REGISTERS_AGG_INT_MODE_1 0x1bcUL
+#define USDM_REGISTERS_AGG_INT_MODE_10 0x1e0UL
+#define USDM_REGISTERS_AGG_INT_MODE_11 0x1e4UL
+#define USDM_REGISTERS_AGG_INT_MODE_12 0x1e8UL
+#define USDM_REGISTERS_AGG_INT_MODE_13 0x1ecUL
+#define USDM_REGISTERS_AGG_INT_MODE_14 0x1f0UL
+#define USDM_REGISTERS_AGG_INT_MODE_15 0x1f4UL
+#define USDM_REGISTERS_AGG_INT_MODE_16 0x1f8UL
+#define USDM_REGISTERS_AGG_INT_MODE_17 0x1fcUL
+#define USDM_REGISTERS_AGG_INT_MODE_18 0x200UL
+#define USDM_REGISTERS_AGG_INT_MODE_19 0x204UL
+#define USDM_REGISTERS_AGG_INT_MODE_10 0x1e0UL
+#define USDM_REGISTERS_AGG_INT_MODE_11 0x1e4UL
+#define USDM_REGISTERS_AGG_INT_MODE_12 0x1e8UL
+#define USDM_REGISTERS_AGG_INT_MODE_13 0x1ecUL
+#define USDM_REGISTERS_AGG_INT_MODE_14 0x1f0UL
+#define USDM_REGISTERS_AGG_INT_MODE_15 0x1f4UL
+#define USDM_REGISTERS_AGG_INT_MODE_16 0x1f8UL
+#define USDM_REGISTERS_AGG_INT_MODE_17 0x1fcUL
+#define USDM_REGISTERS_AGG_INT_MODE_18 0x200UL
+#define USDM_REGISTERS_AGG_INT_MODE_19 0x204UL
+#define USDM_REGISTERS_AGG_INT_MODE_2 0x1c0UL
+#define USDM_REGISTERS_AGG_INT_MODE_20 0x208UL
+#define USDM_REGISTERS_AGG_INT_MODE_21 0x20cUL
+#define USDM_REGISTERS_AGG_INT_MODE_22 0x210UL
+#define USDM_REGISTERS_AGG_INT_MODE_23 0x214UL
+#define USDM_REGISTERS_AGG_INT_MODE_24 0x218UL
+#define USDM_REGISTERS_AGG_INT_MODE_25 0x21cUL
+#define USDM_REGISTERS_AGG_INT_MODE_26 0x220UL
+#define USDM_REGISTERS_AGG_INT_MODE_27 0x224UL
+#define USDM_REGISTERS_AGG_INT_MODE_28 0x228UL
+#define USDM_REGISTERS_AGG_INT_MODE_29 0x22cUL
+#define USDM_REGISTERS_AGG_INT_MODE_20 0x208UL
+#define USDM_REGISTERS_AGG_INT_MODE_21 0x20cUL
+#define USDM_REGISTERS_AGG_INT_MODE_22 0x210UL
+#define USDM_REGISTERS_AGG_INT_MODE_23 0x214UL
+#define USDM_REGISTERS_AGG_INT_MODE_24 0x218UL
+#define USDM_REGISTERS_AGG_INT_MODE_25 0x21cUL
+#define USDM_REGISTERS_AGG_INT_MODE_26 0x220UL
+#define USDM_REGISTERS_AGG_INT_MODE_27 0x224UL
+#define USDM_REGISTERS_AGG_INT_MODE_28 0x228UL
+#define USDM_REGISTERS_AGG_INT_MODE_29 0x22cUL
+#define USDM_REGISTERS_AGG_INT_MODE_3 0x1c4UL
+#define USDM_REGISTERS_AGG_INT_MODE_30 0x230UL
+#define USDM_REGISTERS_AGG_INT_MODE_31 0x234UL
+#define USDM_REGISTERS_AGG_INT_MODE_30 0x230UL
+#define USDM_REGISTERS_AGG_INT_MODE_31 0x234UL
+#define USDM_REGISTERS_AGG_INT_MODE_4 0x1c8UL
+#define USDM_REGISTERS_AGG_INT_MODE_5 0x1ccUL
+#define USDM_REGISTERS_AGG_INT_MODE_6 0x1d0UL
+#define USDM_REGISTERS_AGG_INT_MODE_7 0x1d4UL
+#define USDM_REGISTERS_AGG_INT_MODE_8 0x1d8UL
+#define USDM_REGISTERS_AGG_INT_MODE_9 0x1dcUL
+#define USDM_REGISTERS_AGG_INT_T_0 0xb8UL
+#define USDM_REGISTERS_AGG_INT_T_1 0xbcUL
+#define USDM_REGISTERS_AGG_INT_T_10 0xe0UL
+#define USDM_REGISTERS_AGG_INT_T_11 0xe4UL
+#define USDM_REGISTERS_AGG_INT_T_12 0xe8UL
+#define USDM_REGISTERS_AGG_INT_T_13 0xecUL
+#define USDM_REGISTERS_AGG_INT_T_14 0xf0UL
+#define USDM_REGISTERS_AGG_INT_T_15 0xf4UL
+#define USDM_REGISTERS_AGG_INT_T_16 0xf8UL
+#define USDM_REGISTERS_AGG_INT_T_17 0xfcUL
+#define USDM_REGISTERS_AGG_INT_T_18 0x100UL
+#define USDM_REGISTERS_AGG_INT_T_19 0x104UL
+#define USDM_REGISTERS_AGG_INT_T_10 0xe0UL
+#define USDM_REGISTERS_AGG_INT_T_11 0xe4UL
+#define USDM_REGISTERS_AGG_INT_T_12 0xe8UL
+#define USDM_REGISTERS_AGG_INT_T_13 0xecUL
+#define USDM_REGISTERS_AGG_INT_T_14 0xf0UL
+#define USDM_REGISTERS_AGG_INT_T_15 0xf4UL
+#define USDM_REGISTERS_AGG_INT_T_16 0xf8UL
+#define USDM_REGISTERS_AGG_INT_T_17 0xfcUL
+#define USDM_REGISTERS_AGG_INT_T_18 0x100UL
+#define USDM_REGISTERS_AGG_INT_T_19 0x104UL
+#define USDM_REGISTERS_AGG_INT_T_2 0xc0UL
+#define USDM_REGISTERS_AGG_INT_T_20 0x108UL
+#define USDM_REGISTERS_AGG_INT_T_21 0x10cUL
+#define USDM_REGISTERS_AGG_INT_T_22 0x110UL
+#define USDM_REGISTERS_AGG_INT_T_23 0x114UL
+#define USDM_REGISTERS_AGG_INT_T_24 0x118UL
+#define USDM_REGISTERS_AGG_INT_T_25 0x11cUL
+#define USDM_REGISTERS_AGG_INT_T_26 0x120UL
+#define USDM_REGISTERS_AGG_INT_T_27 0x124UL
+#define USDM_REGISTERS_AGG_INT_T_28 0x128UL
+#define USDM_REGISTERS_AGG_INT_T_29 0x12cUL
+#define USDM_REGISTERS_AGG_INT_T_20 0x108UL
+#define USDM_REGISTERS_AGG_INT_T_21 0x10cUL
+#define USDM_REGISTERS_AGG_INT_T_22 0x110UL
+#define USDM_REGISTERS_AGG_INT_T_23 0x114UL
+#define USDM_REGISTERS_AGG_INT_T_24 0x118UL
+#define USDM_REGISTERS_AGG_INT_T_25 0x11cUL
+#define USDM_REGISTERS_AGG_INT_T_26 0x120UL
+#define USDM_REGISTERS_AGG_INT_T_27 0x124UL
+#define USDM_REGISTERS_AGG_INT_T_28 0x128UL
+#define USDM_REGISTERS_AGG_INT_T_29 0x12cUL
+#define USDM_REGISTERS_AGG_INT_T_3 0xc4UL
+#define USDM_REGISTERS_AGG_INT_T_30 0x130UL
+#define USDM_REGISTERS_AGG_INT_T_31 0x134UL
+#define USDM_REGISTERS_AGG_INT_T_30 0x130UL
+#define USDM_REGISTERS_AGG_INT_T_31 0x134UL
+#define USDM_REGISTERS_AGG_INT_T_4 0xc8UL
+#define USDM_REGISTERS_AGG_INT_T_5 0xccUL
+#define USDM_REGISTERS_AGG_INT_T_6 0xd0UL
+#define USDM_REGISTERS_AGG_INT_T_7 0xd4UL
+#define USDM_REGISTERS_AGG_INT_T_8 0xd8UL
+#define USDM_REGISTERS_AGG_INT_T_9 0xdcUL
+#define USDM_REGISTERS_CFC_RSP_START_ADDR 0x8UL
+#define USDM_REGISTERS_CMP_COUNTER_MAX0 0x1cUL
+#define USDM_REGISTERS_CMP_COUNTER_MAX1 0x20UL
+#define USDM_REGISTERS_CMP_COUNTER_MAX2 0x24UL
+#define USDM_REGISTERS_CMP_COUNTER_MAX3 0x28UL
+#define USDM_REGISTERS_CMP_COUNTER_START_ADDR 0xcUL
+#define USDM_REGISTERS_ENABLE_IN1 0x238UL
+#define USDM_REGISTERS_ENABLE_IN2 0x23cUL
+#define USDM_REGISTERS_ENABLE_OUT1 0x240UL
+#define USDM_REGISTERS_ENABLE_OUT2 0x244UL
+#define USDM_REGISTERS_NUM_OF_ACK_AFTER_PLACE 0x280UL
+#define USDM_REGISTERS_NUM_OF_PKT_END_MSG 0x278UL
+#define USDM_REGISTERS_NUM_OF_PXP_ASYNC_REQ 0x27cUL
+#define USDM_REGISTERS_NUM_OF_Q0_CMD 0x248UL
+#define USDM_REGISTERS_NUM_OF_Q10_CMD 0x270UL
+#define USDM_REGISTERS_NUM_OF_Q11_CMD 0x274UL
+#define USDM_REGISTERS_NUM_OF_Q1_CMD 0x24cUL
+#define USDM_REGISTERS_NUM_OF_Q2_CMD 0x250UL
+#define USDM_REGISTERS_NUM_OF_Q3_CMD 0x254UL
+#define USDM_REGISTERS_NUM_OF_Q4_CMD 0x258UL
+#define USDM_REGISTERS_NUM_OF_Q5_CMD 0x25cUL
+#define USDM_REGISTERS_NUM_OF_Q6_CMD 0x260UL
+#define USDM_REGISTERS_NUM_OF_Q7_CMD 0x264UL
+#define USDM_REGISTERS_NUM_OF_Q8_CMD 0x268UL
+#define USDM_REGISTERS_NUM_OF_Q9_CMD 0x26cUL
+#define USDM_REGISTERS_PCK_END_MSG_START_ADDR 0x14UL
+#define USDM_REGISTERS_Q_COUNTER_START_ADDR 0x10UL
+#define USDM_REGISTERS_RSP_PXP_CTRL_RDATA_EMPTY 0x550UL
+#define USDM_REGISTERS_RSP_PXP_CTRL_RDATA_EMPTY_SIZE 1
+#define USDM_REGISTERS_SYNC_PARSER_EMPTY 0x558UL
+#define USDM_REGISTERS_SYNC_PARSER_EMPTY_SIZE 1
+#define USDM_REGISTERS_SYNC_SYNC_EMPTY 0x560UL
+#define USDM_REGISTERS_SYNC_SYNC_EMPTY_SIZE 1
+#define USDM_REGISTERS_TIMER_TICK 0x0UL
+#define USEM_REGISTERS_ARB_CYCLE_SIZE 0x34UL
+#define USEM_REGISTERS_ARB_ELEMENT0 0x20UL
+#define USEM_REGISTERS_ARB_ELEMENT1 0x24UL
+#define USEM_REGISTERS_ARB_ELEMENT2 0x28UL
+#define USEM_REGISTERS_ARB_ELEMENT3 0x2cUL
+#define USEM_REGISTERS_ARB_ELEMENT4 0x30UL
+#define USEM_REGISTERS_ENABLE_IN 0xa4UL
+#define USEM_REGISTERS_ENABLE_OUT 0xa8UL
+#define USEM_REGISTERS_FAST_MEMORY 0x20000UL
+#define USEM_REGISTERS_FAST_MEMORY_SIZE 32768
+#define USEM_REGISTERS_FIC0_DISABLE 0x224UL
+#define USEM_REGISTERS_FIC0_DISABLE_SIZE 1
+#define USEM_REGISTERS_FIC1_DISABLE 0x234UL
+#define USEM_REGISTERS_FIC1_DISABLE_SIZE 1
+#define USEM_REGISTERS_INT_TABLE_TM 0xd4UL
+#define USEM_REGISTERS_INT_TABLE 0x400UL
+#define USEM_REGISTERS_INT_TABLE_SIZE 256
+#define USEM_REGISTERS_MSG_NUM_FIC0 0x0UL
+#define USEM_REGISTERS_MSG_NUM_FIC1 0x4UL
+#define USEM_REGISTERS_MSG_NUM_FOC0 0x8UL
+#define USEM_REGISTERS_MSG_NUM_FOC1 0xcUL
+#define USEM_REGISTERS_MSG_NUM_FOC2 0x10UL
+#define USEM_REGISTERS_MSG_NUM_FOC3 0x14UL
+#define USEM_REGISTERS_PAS_DISABLE 0x24cUL
+#define USEM_REGISTERS_PAS_DISABLE_SIZE 1
+#define USEM_REGISTERS_PASSIVE_BUFFER 0x2000UL
+#define USEM_REGISTERS_PASSIVE_BUFFER_SIZE 2048
+#define USEM_REGISTERS_PRAM 0x40000UL
+#define USEM_REGISTERS_PRAM_SIZE 65536
+#define USEM_REGISTERS_SLEEP_THREADS_VALID 0x26cUL
+#define USEM_REGISTERS_SLEEP_THREADS_VALID_SIZE 1
+#define USEM_REGISTERS_SLOW_EXT_STORE_EMPTY 0x2a0UL
+#define USEM_REGISTERS_SLOW_EXT_STORE_EMPTY_SIZE 1
+#define USEM_REGISTERS_THREADS_LIST 0x2e4UL
+#define USEM_REGISTERS_THREADS_LIST_SIZE 1
+#define USEM_REGISTERS_TS_0_AS 0x38UL
+#define USEM_REGISTERS_TS_10_AS 0x60UL
+#define USEM_REGISTERS_TS_11_AS 0x64UL
+#define USEM_REGISTERS_TS_12_AS 0x68UL
+#define USEM_REGISTERS_TS_13_AS 0x6cUL
+#define USEM_REGISTERS_TS_14_AS 0x70UL
+#define USEM_REGISTERS_TS_15_AS 0x74UL
+#define USEM_REGISTERS_TS_16_AS 0x78UL
+#define USEM_REGISTERS_TS_17_AS 0x7cUL
+#define USEM_REGISTERS_TS_18_AS 0x80UL
+#define USEM_REGISTERS_TS_19_AS 0x84UL
+#define USEM_REGISTERS_TS_1_AS 0x3cUL
+#define USEM_REGISTERS_TS_2_AS 0x40UL
+#define USEM_REGISTERS_TS_3_AS 0x44UL
+#define USEM_REGISTERS_TS_4_AS 0x48UL
+#define USEM_REGISTERS_TS_5_AS 0x4cUL
+#define USEM_REGISTERS_TS_6_AS 0x50UL
+#define USEM_REGISTERS_TS_7_AS 0x54UL
+#define USEM_REGISTERS_TS_8_AS 0x58UL
+#define USEM_REGISTERS_TS_9_AS 0x5cUL
+#define XCM_REGISTERS_AUX1_Q 0x134UL
+#define XCM_REGISTERS_AUX_CNT_FLG_Q_19 0x1b0UL
+#define XCM_REGISTERS_CAM_OCCUP 0x244UL
+#define XCM_REGISTERS_CAM_OCCUP_ST 0x400UL
+#define XCM_REGISTERS_CAM_OCCUP_ST_SIZE 1
+#define XCM_REGISTERS_CDU_AG_RD_IFEN 0x44UL
+#define XCM_REGISTERS_CDU_AG_WR_IFEN 0x40UL
+#define XCM_REGISTERS_CDU_SM_RD_IFEN 0x4cUL
+#define XCM_REGISTERS_CDU_SM_WR_IFEN 0x48UL
+#define XCM_REGISTERS_CFC_INIT_CRD 0x404UL
+#define XCM_REGISTERS_CFC_INIT_CRD_SIZE 1
+#define XCM_REGISTERS_CP_WEIGHT 0xdcUL
+#define XCM_REGISTERS_CSEM_IFEN 0x28UL
+#define XCM_REGISTERS_CSEM_LENGTH_MIS 0x228UL
+#define XCM_REGISTERS_CSEM_WEIGHT 0xc4UL
+#define XCM_REGISTERS_DORQ_IFEN 0x30UL
+#define XCM_REGISTERS_DORQ_LENGTH_MIS 0x230UL
+#define XCM_REGISTERS_ERR_EVNT_ID 0xb0UL
+#define XCM_REGISTERS_ERR_XCM_HDR 0xacUL
+#define XCM_REGISTERS_EXPR_EVNT_ID 0xb4UL
+#define XCM_REGISTERS_FIC0_INIT_CRD 0x40cUL
+#define XCM_REGISTERS_FIC0_INIT_CRD_SIZE 1
+#define XCM_REGISTERS_FIC1_INIT_CRD 0x410UL
+#define XCM_REGISTERS_FIC1_INIT_CRD_SIZE 1
+#define XCM_REGISTERS_GLB_DEL_ACK_MAX_CNT_0 0x118UL
+#define XCM_REGISTERS_GLB_DEL_ACK_MAX_CNT_1 0x11cUL
+#define XCM_REGISTERS_GLB_DEL_ACK_TMR_VAL_0 0x108UL
+#define XCM_REGISTERS_GLB_DEL_ACK_TMR_VAL_1 0x10cUL
+#define XCM_REGISTERS_GR_ARB_TYPE 0x20cUL
+#define XCM_REGISTERS_GR_LD0_PR 0x214UL
+#define XCM_REGISTERS_GR_LD1_PR 0x218UL
+#define XCM_REGISTERS_NIG0_IFEN 0x38UL
+#define XCM_REGISTERS_NIG0_LENGTH_MIS 0x238UL
+#define XCM_REGISTERS_NIG1_IFEN 0x3cUL
+#define XCM_REGISTERS_NIG1_LENGTH_MIS 0x23cUL
+#define XCM_REGISTERS_NIG1_WEIGHT 0xd8UL
+#define XCM_REGISTERS_N_SM_CTX_LD_0 0x60UL
+#define XCM_REGISTERS_N_SM_CTX_LD_1 0x64UL
+#define XCM_REGISTERS_N_SM_CTX_LD_10 0x88UL
+#define XCM_REGISTERS_N_SM_CTX_LD_11 0x8cUL
+#define XCM_REGISTERS_N_SM_CTX_LD_12 0x90UL
+#define XCM_REGISTERS_N_SM_CTX_LD_13 0x94UL
+#define XCM_REGISTERS_N_SM_CTX_LD_14 0x98UL
+#define XCM_REGISTERS_N_SM_CTX_LD_15 0x9cUL
+#define XCM_REGISTERS_N_SM_CTX_LD_2 0x68UL
+#define XCM_REGISTERS_N_SM_CTX_LD_3 0x6cUL
+#define XCM_REGISTERS_N_SM_CTX_LD_4 0x70UL
+#define XCM_REGISTERS_N_SM_CTX_LD_5 0x74UL
+#define XCM_REGISTERS_N_SM_CTX_LD_6 0x78UL
+#define XCM_REGISTERS_N_SM_CTX_LD_7 0x7cUL
+#define XCM_REGISTERS_PBF_IFEN 0x34UL
+#define XCM_REGISTERS_PBF_LENGTH_MIS 0x234UL
+#define XCM_REGISTERS_PBF_WEIGHT 0xd0UL
+#define XCM_REGISTERS_STOP_EVNT_ID 0xb8UL
+#define XCM_REGISTERS_STORM_LENGTH_MIS 0x21cUL
+#define XCM_REGISTERS_STORM_WEIGHT 0xbcUL
+#define XCM_REGISTERS_STORM_XCM_IFEN 0x10UL
+#define XCM_REGISTERS_TM_INIT_CRD 0x41cUL
+#define XCM_REGISTERS_TM_INIT_CRD_SIZE 1
+#define XCM_REGISTERS_TM_XCM_HDR 0xa8UL
+#define XCM_REGISTERS_TM_XCM_IFEN 0x1cUL
+#define XCM_REGISTERS_TSEM_IFEN 0x24UL
+#define XCM_REGISTERS_TSEM_LENGTH_MIS 0x224UL
+#define XCM_REGISTERS_TSEM_WEIGHT 0xc0UL
+#define XCM_REGISTERS_UNA_GT_NXT_Q 0x120UL
+#define XCM_REGISTERS_USEM_IFEN 0x2cUL
+#define XCM_REGISTERS_USEM_LENGTH_MIS 0x22cUL
+#define XCM_REGISTERS_USEM_WEIGHT 0xc8UL
+#define XCM_REGISTERS_WU_DA_CNT_CMD00 0x1d4UL
+#define XCM_REGISTERS_WU_DA_CNT_CMD01 0x1d8UL
+#define XCM_REGISTERS_WU_DA_CNT_CMD10 0x1dcUL
+#define XCM_REGISTERS_WU_DA_CNT_CMD11 0x1e0UL
+#define XCM_REGISTERS_WU_DA_CNT_UPD_VAL00 0x1e4UL
+#define XCM_REGISTERS_WU_DA_CNT_UPD_VAL01 0x1e8UL
+#define XCM_REGISTERS_WU_DA_CNT_UPD_VAL10 0x1ecUL
+#define XCM_REGISTERS_WU_DA_CNT_UPD_VAL11 0x1f0UL
+#define XCM_REGISTERS_WU_DA_SET_TMR_CNT_FLG_CMD00 0x1c4UL
+#define XCM_REGISTERS_WU_DA_SET_TMR_CNT_FLG_CMD01 0x1c8UL
+#define XCM_REGISTERS_WU_DA_SET_TMR_CNT_FLG_CMD10 0x1ccUL
+#define XCM_REGISTERS_WU_DA_SET_TMR_CNT_FLG_CMD11 0x1d0UL
+#define XCM_REGISTERS_XCM_CFC_IFEN 0x50UL
+#define XCM_REGISTERS_XCM_INT_STS 0x2a8UL
+#define XCM_REGISTERS_XCM_INT_STS_CLR 0x2acUL
+#define XCM_REGISTERS_XCM_INT_STS_WR 0x2b0UL
+#define XCM_REGISTERS_XCM_REG0_SZ 0xf4UL
+#define XCM_REGISTERS_XCM_STORM0_IFEN 0x4UL
+#define XCM_REGISTERS_XCM_STORM1_IFEN 0x8UL
+#define XCM_REGISTERS_XCM_TM_IFEN 0x20UL
+#define XCM_REGISTERS_XCM_XQM_IFEN 0xcUL
+#define XCM_REGISTERS_XCM_XQM_USE_Q 0xf0UL
+#define XCM_REGISTERS_XQM_BYP_ACT_UPD 0xfcUL
+#define XCM_REGISTERS_XQM_INIT_CRD 0x420UL
+#define XCM_REGISTERS_XQM_INIT_CRD_SIZE 1
+#define XCM_REGISTERS_XQM_P_WEIGHT 0xe4UL
+#define XCM_REGISTERS_XQM_XCM_HDR_P 0xa0UL
+#define XCM_REGISTERS_XQM_XCM_HDR_S 0xa4UL
+#define XCM_REGISTERS_XQM_XCM_IFEN 0x14UL
+#define XCM_REGISTERS_XSDM_IFEN 0x18UL
+#define XCM_REGISTERS_XSDM_LENGTH_MIS 0x220UL
+#define XCM_REGISTERS_XSDM_WEIGHT 0xe0UL
+#define XCM_REGISTERS_XX_DESCR_TABLE 0x480UL
+#define XCM_REGISTERS_XX_DESCR_TABLE_SIZE 32
+#define XCM_REGISTERS_XX_INIT_CRD 0x424UL
+#define XCM_REGISTERS_XX_INIT_CRD_SIZE 1
+#define XCM_REGISTERS_XX_MSG_NUM 0x428UL
+#define XCM_REGISTERS_XX_MSG_NUM_SIZE 1
+#define XCM_REGISTERS_XX_OVFL_EVNT_ID 0x58UL
+#define XCM_REGISTERS_XX_TABLE 0x500UL
+#define XCM_REGISTERS_XX_TABLE_SIZE 18
+#define XSDM_REGISTERS_AGG_INT_EVENT_0 0x38UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_1 0x3cUL
+#define XSDM_REGISTERS_AGG_INT_EVENT_10 0x60UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_11 0x64UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_12 0x68UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_13 0x6cUL
+#define XSDM_REGISTERS_AGG_INT_EVENT_14 0x70UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_15 0x74UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_16 0x78UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_17 0x7cUL
+#define XSDM_REGISTERS_AGG_INT_EVENT_18 0x80UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_19 0x84UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_10 0x60UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_11 0x64UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_12 0x68UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_13 0x6cUL
+#define XSDM_REGISTERS_AGG_INT_EVENT_14 0x70UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_15 0x74UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_16 0x78UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_17 0x7cUL
+#define XSDM_REGISTERS_AGG_INT_EVENT_18 0x80UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_19 0x84UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_2 0x40UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_20 0x88UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_21 0x8cUL
+#define XSDM_REGISTERS_AGG_INT_EVENT_22 0x90UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_23 0x94UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_24 0x98UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_25 0x9cUL
+#define XSDM_REGISTERS_AGG_INT_EVENT_26 0xa0UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_27 0xa4UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_28 0xa8UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_29 0xacUL
+#define XSDM_REGISTERS_AGG_INT_EVENT_20 0x88UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_21 0x8cUL
+#define XSDM_REGISTERS_AGG_INT_EVENT_22 0x90UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_23 0x94UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_24 0x98UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_25 0x9cUL
+#define XSDM_REGISTERS_AGG_INT_EVENT_26 0xa0UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_27 0xa4UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_28 0xa8UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_29 0xacUL
+#define XSDM_REGISTERS_AGG_INT_EVENT_3 0x44UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_30 0xb0UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_31 0xb4UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_30 0xb0UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_31 0xb4UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_4 0x48UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_5 0x4cUL
+#define XSDM_REGISTERS_AGG_INT_EVENT_6 0x50UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_7 0x54UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_8 0x58UL
+#define XSDM_REGISTERS_AGG_INT_EVENT_9 0x5cUL
+#define XSDM_REGISTERS_AGG_INT_FIC_0 0x138UL
+#define XSDM_REGISTERS_AGG_INT_FIC_1 0x13cUL
+#define XSDM_REGISTERS_AGG_INT_FIC_10 0x160UL
+#define XSDM_REGISTERS_AGG_INT_FIC_11 0x164UL
+#define XSDM_REGISTERS_AGG_INT_FIC_12 0x168UL
+#define XSDM_REGISTERS_AGG_INT_FIC_13 0x16cUL
+#define XSDM_REGISTERS_AGG_INT_FIC_14 0x170UL
+#define XSDM_REGISTERS_AGG_INT_FIC_15 0x174UL
+#define XSDM_REGISTERS_AGG_INT_FIC_16 0x178UL
+#define XSDM_REGISTERS_AGG_INT_FIC_17 0x17cUL
+#define XSDM_REGISTERS_AGG_INT_FIC_18 0x180UL
+#define XSDM_REGISTERS_AGG_INT_FIC_19 0x184UL
+#define XSDM_REGISTERS_AGG_INT_FIC_10 0x160UL
+#define XSDM_REGISTERS_AGG_INT_FIC_11 0x164UL
+#define XSDM_REGISTERS_AGG_INT_FIC_12 0x168UL
+#define XSDM_REGISTERS_AGG_INT_FIC_13 0x16cUL
+#define XSDM_REGISTERS_AGG_INT_FIC_14 0x170UL
+#define XSDM_REGISTERS_AGG_INT_FIC_15 0x174UL
+#define XSDM_REGISTERS_AGG_INT_FIC_16 0x178UL
+#define XSDM_REGISTERS_AGG_INT_FIC_17 0x17cUL
+#define XSDM_REGISTERS_AGG_INT_FIC_18 0x180UL
+#define XSDM_REGISTERS_AGG_INT_FIC_19 0x184UL
+#define XSDM_REGISTERS_AGG_INT_FIC_2 0x140UL
+#define XSDM_REGISTERS_AGG_INT_FIC_20 0x188UL
+#define XSDM_REGISTERS_AGG_INT_FIC_21 0x18cUL
+#define XSDM_REGISTERS_AGG_INT_FIC_22 0x190UL
+#define XSDM_REGISTERS_AGG_INT_FIC_23 0x194UL
+#define XSDM_REGISTERS_AGG_INT_FIC_24 0x198UL
+#define XSDM_REGISTERS_AGG_INT_FIC_25 0x19cUL
+#define XSDM_REGISTERS_AGG_INT_FIC_26 0x1a0UL
+#define XSDM_REGISTERS_AGG_INT_FIC_27 0x1a4UL
+#define XSDM_REGISTERS_AGG_INT_FIC_28 0x1a8UL
+#define XSDM_REGISTERS_AGG_INT_FIC_29 0x1acUL
+#define XSDM_REGISTERS_AGG_INT_FIC_20 0x188UL
+#define XSDM_REGISTERS_AGG_INT_FIC_21 0x18cUL
+#define XSDM_REGISTERS_AGG_INT_FIC_22 0x190UL
+#define XSDM_REGISTERS_AGG_INT_FIC_23 0x194UL
+#define XSDM_REGISTERS_AGG_INT_FIC_24 0x198UL
+#define XSDM_REGISTERS_AGG_INT_FIC_25 0x19cUL
+#define XSDM_REGISTERS_AGG_INT_FIC_26 0x1a0UL
+#define XSDM_REGISTERS_AGG_INT_FIC_27 0x1a4UL
+#define XSDM_REGISTERS_AGG_INT_FIC_28 0x1a8UL
+#define XSDM_REGISTERS_AGG_INT_FIC_29 0x1acUL
+#define XSDM_REGISTERS_AGG_INT_FIC_3 0x144UL
+#define XSDM_REGISTERS_AGG_INT_FIC_30 0x1b0UL
+#define XSDM_REGISTERS_AGG_INT_FIC_31 0x1b4UL
+#define XSDM_REGISTERS_AGG_INT_FIC_30 0x1b0UL
+#define XSDM_REGISTERS_AGG_INT_FIC_31 0x1b4UL
+#define XSDM_REGISTERS_AGG_INT_FIC_4 0x148UL
+#define XSDM_REGISTERS_AGG_INT_FIC_5 0x14cUL
+#define XSDM_REGISTERS_AGG_INT_FIC_6 0x150UL
+#define XSDM_REGISTERS_AGG_INT_FIC_7 0x154UL
+#define XSDM_REGISTERS_AGG_INT_FIC_8 0x158UL
+#define XSDM_REGISTERS_AGG_INT_FIC_9 0x15cUL
+#define XSDM_REGISTERS_AGG_INT_MODE_0 0x1b8UL
+#define XSDM_REGISTERS_AGG_INT_MODE_1 0x1bcUL
+#define XSDM_REGISTERS_AGG_INT_MODE_10 0x1e0UL
+#define XSDM_REGISTERS_AGG_INT_MODE_11 0x1e4UL
+#define XSDM_REGISTERS_AGG_INT_MODE_12 0x1e8UL
+#define XSDM_REGISTERS_AGG_INT_MODE_13 0x1ecUL
+#define XSDM_REGISTERS_AGG_INT_MODE_14 0x1f0UL
+#define XSDM_REGISTERS_AGG_INT_MODE_15 0x1f4UL
+#define XSDM_REGISTERS_AGG_INT_MODE_16 0x1f8UL
+#define XSDM_REGISTERS_AGG_INT_MODE_17 0x1fcUL
+#define XSDM_REGISTERS_AGG_INT_MODE_18 0x200UL
+#define XSDM_REGISTERS_AGG_INT_MODE_19 0x204UL
+#define XSDM_REGISTERS_AGG_INT_MODE_10 0x1e0UL
+#define XSDM_REGISTERS_AGG_INT_MODE_11 0x1e4UL
+#define XSDM_REGISTERS_AGG_INT_MODE_12 0x1e8UL
+#define XSDM_REGISTERS_AGG_INT_MODE_13 0x1ecUL
+#define XSDM_REGISTERS_AGG_INT_MODE_14 0x1f0UL
+#define XSDM_REGISTERS_AGG_INT_MODE_15 0x1f4UL
+#define XSDM_REGISTERS_AGG_INT_MODE_16 0x1f8UL
+#define XSDM_REGISTERS_AGG_INT_MODE_17 0x1fcUL
+#define XSDM_REGISTERS_AGG_INT_MODE_18 0x200UL
+#define XSDM_REGISTERS_AGG_INT_MODE_19 0x204UL
+#define XSDM_REGISTERS_AGG_INT_MODE_2 0x1c0UL
+#define XSDM_REGISTERS_AGG_INT_MODE_20 0x208UL
+#define XSDM_REGISTERS_AGG_INT_MODE_21 0x20cUL
+#define XSDM_REGISTERS_AGG_INT_MODE_22 0x210UL
+#define XSDM_REGISTERS_AGG_INT_MODE_23 0x214UL
+#define XSDM_REGISTERS_AGG_INT_MODE_24 0x218UL
+#define XSDM_REGISTERS_AGG_INT_MODE_25 0x21cUL
+#define XSDM_REGISTERS_AGG_INT_MODE_26 0x220UL
+#define XSDM_REGISTERS_AGG_INT_MODE_27 0x224UL
+#define XSDM_REGISTERS_AGG_INT_MODE_28 0x228UL
+#define XSDM_REGISTERS_AGG_INT_MODE_29 0x22cUL
+#define XSDM_REGISTERS_AGG_INT_MODE_20 0x208UL
+#define XSDM_REGISTERS_AGG_INT_MODE_21 0x20cUL
+#define XSDM_REGISTERS_AGG_INT_MODE_22 0x210UL
+#define XSDM_REGISTERS_AGG_INT_MODE_23 0x214UL
+#define XSDM_REGISTERS_AGG_INT_MODE_24 0x218UL
+#define XSDM_REGISTERS_AGG_INT_MODE_25 0x21cUL
+#define XSDM_REGISTERS_AGG_INT_MODE_26 0x220UL
+#define XSDM_REGISTERS_AGG_INT_MODE_27 0x224UL
+#define XSDM_REGISTERS_AGG_INT_MODE_28 0x228UL
+#define XSDM_REGISTERS_AGG_INT_MODE_29 0x22cUL
+#define XSDM_REGISTERS_AGG_INT_MODE_3 0x1c4UL
+#define XSDM_REGISTERS_AGG_INT_MODE_30 0x230UL
+#define XSDM_REGISTERS_AGG_INT_MODE_31 0x234UL
+#define XSDM_REGISTERS_AGG_INT_MODE_30 0x230UL
+#define XSDM_REGISTERS_AGG_INT_MODE_31 0x234UL
+#define XSDM_REGISTERS_AGG_INT_MODE_4 0x1c8UL
+#define XSDM_REGISTERS_AGG_INT_MODE_5 0x1ccUL
+#define XSDM_REGISTERS_AGG_INT_MODE_6 0x1d0UL
+#define XSDM_REGISTERS_AGG_INT_MODE_7 0x1d4UL
+#define XSDM_REGISTERS_AGG_INT_MODE_8 0x1d8UL
+#define XSDM_REGISTERS_AGG_INT_MODE_9 0x1dcUL
+#define XSDM_REGISTERS_AGG_INT_T_0 0xb8UL
+#define XSDM_REGISTERS_AGG_INT_T_1 0xbcUL
+#define XSDM_REGISTERS_AGG_INT_T_10 0xe0UL
+#define XSDM_REGISTERS_AGG_INT_T_11 0xe4UL
+#define XSDM_REGISTERS_AGG_INT_T_12 0xe8UL
+#define XSDM_REGISTERS_AGG_INT_T_13 0xecUL
+#define XSDM_REGISTERS_AGG_INT_T_14 0xf0UL
+#define XSDM_REGISTERS_AGG_INT_T_15 0xf4UL
+#define XSDM_REGISTERS_AGG_INT_T_16 0xf8UL
+#define XSDM_REGISTERS_AGG_INT_T_17 0xfcUL
+#define XSDM_REGISTERS_AGG_INT_T_18 0x100UL
+#define XSDM_REGISTERS_AGG_INT_T_19 0x104UL
+#define XSDM_REGISTERS_AGG_INT_T_10 0xe0UL
+#define XSDM_REGISTERS_AGG_INT_T_11 0xe4UL
+#define XSDM_REGISTERS_AGG_INT_T_12 0xe8UL
+#define XSDM_REGISTERS_AGG_INT_T_13 0xecUL
+#define XSDM_REGISTERS_AGG_INT_T_14 0xf0UL
+#define XSDM_REGISTERS_AGG_INT_T_15 0xf4UL
+#define XSDM_REGISTERS_AGG_INT_T_16 0xf8UL
+#define XSDM_REGISTERS_AGG_INT_T_17 0xfcUL
+#define XSDM_REGISTERS_AGG_INT_T_18 0x100UL
+#define XSDM_REGISTERS_AGG_INT_T_19 0x104UL
+#define XSDM_REGISTERS_AGG_INT_T_2 0xc0UL
+#define XSDM_REGISTERS_AGG_INT_T_20 0x108UL
+#define XSDM_REGISTERS_AGG_INT_T_21 0x10cUL
+#define XSDM_REGISTERS_AGG_INT_T_22 0x110UL
+#define XSDM_REGISTERS_AGG_INT_T_23 0x114UL
+#define XSDM_REGISTERS_AGG_INT_T_24 0x118UL
+#define XSDM_REGISTERS_AGG_INT_T_25 0x11cUL
+#define XSDM_REGISTERS_AGG_INT_T_26 0x120UL
+#define XSDM_REGISTERS_AGG_INT_T_27 0x124UL
+#define XSDM_REGISTERS_AGG_INT_T_28 0x128UL
+#define XSDM_REGISTERS_AGG_INT_T_29 0x12cUL
+#define XSDM_REGISTERS_AGG_INT_T_20 0x108UL
+#define XSDM_REGISTERS_AGG_INT_T_21 0x10cUL
+#define XSDM_REGISTERS_AGG_INT_T_22 0x110UL
+#define XSDM_REGISTERS_AGG_INT_T_23 0x114UL
+#define XSDM_REGISTERS_AGG_INT_T_24 0x118UL
+#define XSDM_REGISTERS_AGG_INT_T_25 0x11cUL
+#define XSDM_REGISTERS_AGG_INT_T_26 0x120UL
+#define XSDM_REGISTERS_AGG_INT_T_27 0x124UL
+#define XSDM_REGISTERS_AGG_INT_T_28 0x128UL
+#define XSDM_REGISTERS_AGG_INT_T_29 0x12cUL
+#define XSDM_REGISTERS_AGG_INT_T_3 0xc4UL
+#define XSDM_REGISTERS_AGG_INT_T_30 0x130UL
+#define XSDM_REGISTERS_AGG_INT_T_31 0x134UL
+#define XSDM_REGISTERS_AGG_INT_T_30 0x130UL
+#define XSDM_REGISTERS_AGG_INT_T_31 0x134UL
+#define XSDM_REGISTERS_AGG_INT_T_4 0xc8UL
+#define XSDM_REGISTERS_AGG_INT_T_5 0xccUL
+#define XSDM_REGISTERS_AGG_INT_T_6 0xd0UL
+#define XSDM_REGISTERS_AGG_INT_T_7 0xd4UL
+#define XSDM_REGISTERS_AGG_INT_T_8 0xd8UL
+#define XSDM_REGISTERS_AGG_INT_T_9 0xdcUL
+#define XSDM_REGISTERS_CFC_RSP_START_ADDR 0x8UL
+#define XSDM_REGISTERS_CMP_COUNTER_MAX0 0x1cUL
+#define XSDM_REGISTERS_CMP_COUNTER_MAX1 0x20UL
+#define XSDM_REGISTERS_CMP_COUNTER_MAX2 0x24UL
+#define XSDM_REGISTERS_CMP_COUNTER_MAX3 0x28UL
+#define XSDM_REGISTERS_CMP_COUNTER_START_ADDR 0xcUL
+#define XSDM_REGISTERS_ENABLE_IN1 0x238UL
+#define XSDM_REGISTERS_ENABLE_IN2 0x23cUL
+#define XSDM_REGISTERS_ENABLE_OUT1 0x240UL
+#define XSDM_REGISTERS_ENABLE_OUT2 0x244UL
+#define XSDM_REGISTERS_NUM_OF_ACK_AFTER_PLACE 0x27cUL
+#define XSDM_REGISTERS_NUM_OF_PKT_END_MSG 0x274UL
+#define XSDM_REGISTERS_NUM_OF_PXP_ASYNC_REQ 0x278UL
+#define XSDM_REGISTERS_NUM_OF_Q0_CMD 0x248UL
+#define XSDM_REGISTERS_NUM_OF_Q10_CMD 0x26cUL
+#define XSDM_REGISTERS_NUM_OF_Q11_CMD 0x270UL
+#define XSDM_REGISTERS_NUM_OF_Q1_CMD 0x24cUL
+#define XSDM_REGISTERS_NUM_OF_Q3_CMD 0x250UL
+#define XSDM_REGISTERS_NUM_OF_Q4_CMD 0x254UL
+#define XSDM_REGISTERS_NUM_OF_Q5_CMD 0x258UL
+#define XSDM_REGISTERS_NUM_OF_Q6_CMD 0x25cUL
+#define XSDM_REGISTERS_NUM_OF_Q7_CMD 0x260UL
+#define XSDM_REGISTERS_NUM_OF_Q8_CMD 0x264UL
+#define XSDM_REGISTERS_NUM_OF_Q9_CMD 0x268UL
+#define XSDM_REGISTERS_Q_COUNTER_START_ADDR 0x10UL
+#define XSDM_REGISTERS_RSP_PXP_CTRL_RDATA_EMPTY 0x548UL
+#define XSDM_REGISTERS_RSP_PXP_CTRL_RDATA_EMPTY_SIZE 1
+#define XSDM_REGISTERS_SYNC_PARSER_EMPTY 0x550UL
+#define XSDM_REGISTERS_SYNC_PARSER_EMPTY_SIZE 1
+#define XSDM_REGISTERS_SYNC_SYNC_EMPTY 0x558UL
+#define XSDM_REGISTERS_SYNC_SYNC_EMPTY_SIZE 1
+#define XSDM_REGISTERS_TIMER_TICK 0x0UL
+#define XSEM_REGISTERS_ARB_CYCLE_SIZE 0x34UL
+#define XSEM_REGISTERS_ARB_ELEMENT0 0x20UL
+#define XSEM_REGISTERS_ARB_ELEMENT1 0x24UL
+#define XSEM_REGISTERS_ARB_ELEMENT2 0x28UL
+#define XSEM_REGISTERS_ARB_ELEMENT3 0x2cUL
+#define XSEM_REGISTERS_ARB_ELEMENT4 0x30UL
+#define XSEM_REGISTERS_ENABLE_IN 0xa4UL
+#define XSEM_REGISTERS_ENABLE_OUT 0xa8UL
+#define XSEM_REGISTERS_FAST_MEMORY 0x20000UL
+#define XSEM_REGISTERS_FAST_MEMORY_SIZE 32768
+#define XSEM_REGISTERS_FIC0_DISABLE 0x224UL
+#define XSEM_REGISTERS_FIC0_DISABLE_SIZE 1
+#define XSEM_REGISTERS_FIC1_DISABLE 0x234UL
+#define XSEM_REGISTERS_FIC1_DISABLE_SIZE 1
+#define XSEM_REGISTERS_INT_TABLE_TM 0xd4UL
+#define XSEM_REGISTERS_INT_TABLE 0x400UL
+#define XSEM_REGISTERS_INT_TABLE_SIZE 256
+#define XSEM_REGISTERS_MSG_NUM_FIC0 0x0UL
+#define XSEM_REGISTERS_MSG_NUM_FIC1 0x4UL
+#define XSEM_REGISTERS_MSG_NUM_FOC0 0x8UL
+#define XSEM_REGISTERS_MSG_NUM_FOC1 0xcUL
+#define XSEM_REGISTERS_MSG_NUM_FOC2 0x10UL
+#define XSEM_REGISTERS_MSG_NUM_FOC3 0x14UL
+#define XSEM_REGISTERS_PAS_DISABLE 0x24cUL
+#define XSEM_REGISTERS_PAS_DISABLE_SIZE 1
+#define XSEM_REGISTERS_PASSIVE_BUFFER 0x2000UL
+#define XSEM_REGISTERS_PASSIVE_BUFFER_SIZE 2048
+#define XSEM_REGISTERS_PRAM 0x40000UL
+#define XSEM_REGISTERS_PRAM_SIZE 65536
+#define XSEM_REGISTERS_SLEEP_THREADS_VALID 0x26cUL
+#define XSEM_REGISTERS_SLEEP_THREADS_VALID_SIZE 1
+#define XSEM_REGISTERS_SLOW_EXT_STORE_EMPTY 0x2a0UL
+#define XSEM_REGISTERS_SLOW_EXT_STORE_EMPTY_SIZE 1
+#define XSEM_REGISTERS_THREADS_LIST 0x2e4UL
+#define XSEM_REGISTERS_THREADS_LIST_SIZE 1
+#define XSEM_REGISTERS_TS_0_AS 0x38UL
+#define XSEM_REGISTERS_TS_10_AS 0x60UL
+#define XSEM_REGISTERS_TS_11_AS 0x64UL
+#define XSEM_REGISTERS_TS_12_AS 0x68UL
+#define XSEM_REGISTERS_TS_13_AS 0x6cUL
+#define XSEM_REGISTERS_TS_14_AS 0x70UL
+#define XSEM_REGISTERS_TS_15_AS 0x74UL
+#define XSEM_REGISTERS_TS_16_AS 0x78UL
+#define XSEM_REGISTERS_TS_17_AS 0x7cUL
+#define XSEM_REGISTERS_TS_18_AS 0x80UL
+#define XSEM_REGISTERS_TS_19_AS 0x84UL
+#define XSEM_REGISTERS_TS_1_AS 0x3cUL
+#define XSEM_REGISTERS_TS_2_AS 0x40UL
+#define XSEM_REGISTERS_TS_3_AS 0x44UL
+#define XSEM_REGISTERS_TS_4_AS 0x48UL
+#define XSEM_REGISTERS_TS_5_AS 0x4cUL
+#define XSEM_REGISTERS_TS_6_AS 0x50UL
+#define XSEM_REGISTERS_TS_7_AS 0x54UL
+#define XSEM_REGISTERS_TS_8_AS 0x58UL
+#define XSEM_REGISTERS_TS_9_AS 0x5cUL
+#define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3)
+#define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
+#define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)
+#define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)
+#define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)
+#define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)
+#define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)
+#define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)
+#define BIGMAC_REGISTER_TX_CONTROL (0x07<<3)
+#define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3)
+#define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3)
+#define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
+#define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
+#define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
+#ifndef EMAC_REG_H
+#define EMAC_REG_H
+#define EMAC_REG_EMAC_MODE 0x0
+#define EMAC_MODE_RESET (1L<<0)
+#define EMAC_MODE_RESET_BITSHIFT 0
+#define EMAC_MODE_HALF_DUPLEX (1L<<1)
+#define EMAC_MODE_HALF_DUPLEX_BITSHIFT 1
+#define EMAC_MODE_PORT (0x3L<<2)
+#define EMAC_MODE_PORT_BITSHIFT 2
+#define EMAC_MODE_PORT_NONE (0L<<2)
+#define EMAC_MODE_PORT_NONE_BITSHIFT 2
+#define EMAC_MODE_PORT_MII (1L<<2)
+#define EMAC_MODE_PORT_MII_BITSHIFT 2
+#define EMAC_MODE_PORT_GMII (2L<<2)
+#define EMAC_MODE_PORT_GMII_BITSHIFT 2
+#define EMAC_MODE_PORT_MII_10M (3L<<2)
+#define EMAC_MODE_PORT_MII_10M_BITSHIFT 2
+#define EMAC_MODE_MAC_LOOP (1L<<4)
+#define EMAC_MODE_MAC_LOOP_BITSHIFT 4
+#define EMAC_MODE_25G_MODE (1L<<5)
+#define EMAC_MODE_25G_MODE_BITSHIFT 5
+#define EMAC_MODE_TAGGED_MAC_CTL (1L<<7)
+#define EMAC_MODE_TAGGED_MAC_CTL_BITSHIFT 7
+#define EMAC_MODE_TX_BURST (1L<<8)
+#define EMAC_MODE_TX_BURST_BITSHIFT 8
+#define EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9)
+#define EMAC_MODE_MAX_DEFER_DROP_ENA_BITSHIFT 9
+#define EMAC_MODE_EXT_LINK_POL (1L<<10)
+#define EMAC_MODE_EXT_LINK_POL_BITSHIFT 10
+#define EMAC_MODE_FORCE_LINK (1L<<11)
+#define EMAC_MODE_FORCE_LINK_BITSHIFT 11
+#define EMAC_MODE_MPKT (1L<<18)
+#define EMAC_MODE_MPKT_BITSHIFT 18
+#define EMAC_MODE_MPKT_RCVD (1L<<19)
+#define EMAC_MODE_MPKT_RCVD_BITSHIFT 19
+#define EMAC_MODE_ACPI_RCVD (1L<<20)
+#define EMAC_MODE_ACPI_RCVD_BITSHIFT 20
+#define EMAC_REG_EMAC_STATUS 0x4
+#define EMAC_STATUS_LINK (1L<<11)
+#define EMAC_STATUS_LINK_BITSHIFT 11
+#define EMAC_STATUS_LINK_CHANGE (1L<<12)
+#define EMAC_STATUS_LINK_CHANGE_BITSHIFT 12
+#define EMAC_STATUS_SERDES_AUTONEG_COMPLETE (1L<<13)
+#define EMAC_STATUS_SERDES_AUTONEG_COMPLETE_BITSHIFT 13
+#define EMAC_STATUS_SERDES_AUTONEG_CHANGE (1L<<14)
+#define EMAC_STATUS_SERDES_AUTONEG_CHANGE_BITSHIFT 14
+#define EMAC_STATUS_SERDES_NXT_PG_CHANGE (1L<<16)
+#define EMAC_STATUS_SERDES_NXT_PG_CHANGE_BITSHIFT 16
+#define EMAC_STATUS_SERDES_RX_CONFIG_IS_0 (1L<<17)
+#define EMAC_STATUS_SERDES_RX_CONFIG_IS_0_BITSHIFT 17
+#define EMAC_STATUS_SERDES_RX_CONFIG_IS_0_CHANGE (1L<<18)
+#define EMAC_STATUS_SERDES_RX_CONFIG_IS_0_CHANGE_BITSHIFT 18
+#define EMAC_STATUS_MI_COMPLETE (1L<<22)
+#define EMAC_STATUS_MI_COMPLETE_BITSHIFT 22
+#define EMAC_STATUS_MI_INT (1L<<23)
+#define EMAC_STATUS_MI_INT_BITSHIFT 23
+#define EMAC_STATUS_AP_ERROR (1L<<24)
+#define EMAC_STATUS_AP_ERROR_BITSHIFT 24
+#define EMAC_STATUS_PARITY_ERROR_STATE (1L<<31)
+#define EMAC_STATUS_PARITY_ERROR_STATE_BITSHIFT 31
+#define EMAC_REG_EMAC_ATTENTION_ENA 0x8
+#define EMAC_ATTENTION_ENA_LINK (1L<<11)
+#define EMAC_ATTENTION_ENA_LINK_BITSHIFT 11
+#define EMAC_ATTENTION_ENA_AUTONEG_CHANGE (1L<<14)
+#define EMAC_ATTENTION_ENA_AUTONEG_CHANGE_BITSHIFT 14
+#define EMAC_ATTENTION_ENA_NXT_PG_CHANGE (1L<<16)
+#define EMAC_ATTENTION_ENA_NXT_PG_CHANGE_BITSHIFT 16
+#define EMAC_ATTENTION_ENA_SERDES_RX_CONFIG_IS_0_CHANGE (1L<<18)
+#define EMAC_ATTENTION_ENA_SERDES_RX_CONFIG_IS_0_CHANGE_BITSHIFT 18
+#define EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22)
+#define EMAC_ATTENTION_ENA_MI_COMPLETE_BITSHIFT 22
+#define EMAC_ATTENTION_ENA_MI_INT (1L<<23)
+#define EMAC_ATTENTION_ENA_MI_INT_BITSHIFT 23
+#define EMAC_ATTENTION_ENA_AP_ERROR (1L<<24)
+#define EMAC_ATTENTION_ENA_AP_ERROR_BITSHIFT 24
+#define EMAC_REG_EMAC_LED 0xc
+#define EMAC_LED_OVERRIDE (1L<<0)
+#define EMAC_LED_OVERRIDE_BITSHIFT 0
+#define EMAC_LED_1000MB_OVERRIDE (1L<<1)
+#define EMAC_LED_1000MB_OVERRIDE_BITSHIFT 1
+#define EMAC_LED_100MB_OVERRIDE (1L<<2)
+#define EMAC_LED_100MB_OVERRIDE_BITSHIFT 2
+#define EMAC_LED_10MB_OVERRIDE (1L<<3)
+#define EMAC_LED_10MB_OVERRIDE_BITSHIFT 3
+#define EMAC_LED_TRAFFIC_OVERRIDE (1L<<4)
+#define EMAC_LED_TRAFFIC_OVERRIDE_BITSHIFT 4
+#define EMAC_LED_BLNK_TRAFFIC (1L<<5)
+#define EMAC_LED_BLNK_TRAFFIC_BITSHIFT 5
+#define EMAC_LED_TRAFFIC (1L<<6)
+#define EMAC_LED_TRAFFIC_BITSHIFT 6
+#define EMAC_LED_1000MB (1L<<7)
+#define EMAC_LED_1000MB_BITSHIFT 7
+#define EMAC_LED_100MB (1L<<8)
+#define EMAC_LED_100MB_BITSHIFT 8
+#define EMAC_LED_10MB (1L<<9)
+#define EMAC_LED_10MB_BITSHIFT 9
+#define EMAC_LED_TRAFFIC_STAT (1L<<10)
+#define EMAC_LED_TRAFFIC_STAT_BITSHIFT 10
+#define EMAC_LED_2500MB (1L<<11)
+#define EMAC_LED_2500MB_BITSHIFT 11
+#define EMAC_LED_2500MB_OVERRIDE (1L<<12)
+#define EMAC_LED_2500MB_OVERRIDE_BITSHIFT 12
+#define EMAC_LED_ACTIVITY_SEL (0x3L<<17)
+#define EMAC_LED_ACTIVITY_SEL_BITSHIFT 17
+#define EMAC_LED_ACTIVITY_SEL_0 (0L<<17)
+#define EMAC_LED_ACTIVITY_SEL_0_BITSHIFT 17
+#define EMAC_LED_ACTIVITY_SEL_1 (1L<<17)
+#define EMAC_LED_ACTIVITY_SEL_1_BITSHIFT 17
+#define EMAC_LED_ACTIVITY_SEL_2 (2L<<17)
+#define EMAC_LED_ACTIVITY_SEL_2_BITSHIFT 17
+#define EMAC_LED_ACTIVITY_SEL_3 (3L<<17)
+#define EMAC_LED_ACTIVITY_SEL_3_BITSHIFT 17
+#define EMAC_LED_BLNK_RATE (0xfffL<<19)
+#define EMAC_LED_BLNK_RATE_BITSHIFT 19
+#define EMAC_LED_BLNK_RATE_ENA (1L<<31)
+#define EMAC_LED_BLNK_RATE_ENA_BITSHIFT 31
+#define EMAC_REG_EMAC_MAC_MATCH 0x10
+#define EMAC_REG_EMAC_MAC_MATCH_COUNT 32
+#define EMAC_REG_EMAC_UNUSED1 0x90
+#define EMAC_REG_EMAC_UNUSED1_COUNT 2
+#define EMAC_REG_EMAC_BACKOFF_SEED 0x98
+#define EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED (0x3ffL<<0)
+#define EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED_BITSHIFT 0
+#define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
+#define EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffL<<0)
+#define EMAC_RX_MTU_SIZE_MTU_SIZE_BITSHIFT 0
+#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
+#define EMAC_RX_MTU_SIZE_JUMBO_ENA_BITSHIFT 31
+#define EMAC_REG_EMAC_UNUSED2 0xa0
+#define EMAC_REG_EMAC_UNUSED2_COUNT 3
+#define EMAC_REG_EMAC_MDIO_COMM 0xac
+#define EMAC_MDIO_COMM_DATA (0xffffL<<0)
+#define EMAC_MDIO_COMM_DATA_BITSHIFT 0
+#define EMAC_MDIO_COMM_REG_ADDR (0x1fL<<16)
+#define EMAC_MDIO_COMM_REG_ADDR_BITSHIFT 16
+#define EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21)
+#define EMAC_MDIO_COMM_PHY_ADDR_BITSHIFT 21
+#define EMAC_MDIO_COMM_COMMAND (0x3L<<26)
+#define EMAC_MDIO_COMM_COMMAND_BITSHIFT 26
+#define EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26)
+#define EMAC_MDIO_COMM_COMMAND_UNDEFINED_0_BITSHIFT 26
+#define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
+#define EMAC_MDIO_COMM_COMMAND_ADDRESS_BITSHIFT 26
+#define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26)
+#define EMAC_MDIO_COMM_COMMAND_WRITE_22_BITSHIFT 26
+#define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
+#define EMAC_MDIO_COMM_COMMAND_WRITE_45_BITSHIFT 26
+#define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26)
+#define EMAC_MDIO_COMM_COMMAND_READ_22_BITSHIFT 26
+#define EMAC_MDIO_COMM_COMMAND_READ_INC_45 (2L<<26)
+#define EMAC_MDIO_COMM_COMMAND_READ_INC_45_BITSHIFT 26
+#define EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26)
+#define EMAC_MDIO_COMM_COMMAND_UNDEFINED_3_BITSHIFT 26
+#define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
+#define EMAC_MDIO_COMM_COMMAND_READ_45_BITSHIFT 26
+#define EMAC_MDIO_COMM_FAIL (1L<<28)
+#define EMAC_MDIO_COMM_FAIL_BITSHIFT 28
+#define EMAC_MDIO_COMM_START_BUSY (1L<<29)
+#define EMAC_MDIO_COMM_START_BUSY_BITSHIFT 29
+#define EMAC_REG_EMAC_MDIO_STATUS 0xb0
+#define EMAC_MDIO_STATUS_LINK (1L<<0)
+#define EMAC_MDIO_STATUS_LINK_BITSHIFT 0
+#define EMAC_MDIO_STATUS_10MB (1L<<1)
+#define EMAC_MDIO_STATUS_10MB_BITSHIFT 1
+#define EMAC_REG_EMAC_MDIO_MODE 0xb4
+#define EMAC_MDIO_MODE_SHORT_PREAMBLE (1L<<1)
+#define EMAC_MDIO_MODE_SHORT_PREAMBLE_BITSHIFT 1
+#define EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
+#define EMAC_MDIO_MODE_AUTO_POLL_BITSHIFT 4
+#define EMAC_MDIO_MODE_BIT_BANG (1L<<8)
+#define EMAC_MDIO_MODE_BIT_BANG_BITSHIFT 8
+#define EMAC_MDIO_MODE_MDIO (1L<<9)
+#define EMAC_MDIO_MODE_MDIO_BITSHIFT 9
+#define EMAC_MDIO_MODE_MDIO_OE (1L<<10)
+#define EMAC_MDIO_MODE_MDIO_OE_BITSHIFT 10
+#define EMAC_MDIO_MODE_MDC (1L<<11)
+#define EMAC_MDIO_MODE_MDC_BITSHIFT 11
+#define EMAC_MDIO_MODE_MDINT (1L<<12)
+#define EMAC_MDIO_MODE_MDINT_BITSHIFT 12
+#define EMAC_MDIO_MODE_EXT_MDINT (1L<<13)
+#define EMAC_MDIO_MODE_EXT_MDINT_BITSHIFT 13
+#define EMAC_MDIO_MODE_CLOCK_CNT (0x3fL<<16)
+#define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
+#define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31)
+#define EMAC_MDIO_MODE_CLAUSE_45_BITSHIFT 31
+#define EMAC_REG_EMAC_MDIO_AUTO_STATUS 0xb8
+#define EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0)
+#define EMAC_MDIO_AUTO_STATUS_AUTO_ERR_BITSHIFT 0
+#define EMAC_REG_EMAC_TX_MODE 0xbc
+#define EMAC_TX_MODE_RESET (1L<<0)
+#define EMAC_TX_MODE_RESET_BITSHIFT 0
+#define EMAC_TX_MODE_CS16_TEST (1L<<2)
+#define EMAC_TX_MODE_CS16_TEST_BITSHIFT 2
+#define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
+#define EMAC_TX_MODE_EXT_PAUSE_EN_BITSHIFT 3
+#define EMAC_TX_MODE_FLOW_EN (1L<<4)
+#define EMAC_TX_MODE_FLOW_EN_BITSHIFT 4
+#define EMAC_TX_MODE_BIG_BACKOFF (1L<<5)
+#define EMAC_TX_MODE_BIG_BACKOFF_BITSHIFT 5
+#define EMAC_TX_MODE_LONG_PAUSE (1L<<6)
+#define EMAC_TX_MODE_LONG_PAUSE_BITSHIFT 6
+#define EMAC_TX_MODE_LINK_AWARE (1L<<7)
+#define EMAC_TX_MODE_LINK_AWARE_BITSHIFT 7
+#define EMAC_REG_EMAC_TX_STATUS 0xc0
+#define EMAC_TX_STATUS_XOFFED (1L<<0)
+#define EMAC_TX_STATUS_XOFFED_BITSHIFT 0
+#define EMAC_TX_STATUS_XOFF_SENT (1L<<1)
+#define EMAC_TX_STATUS_XOFF_SENT_BITSHIFT 1
+#define EMAC_TX_STATUS_XON_SENT (1L<<2)
+#define EMAC_TX_STATUS_XON_SENT_BITSHIFT 2
+#define EMAC_TX_STATUS_LINK_UP (1L<<3)
+#define EMAC_TX_STATUS_LINK_UP_BITSHIFT 3
+#define EMAC_TX_STATUS_UNDERRUN (1L<<4)
+#define EMAC_TX_STATUS_UNDERRUN_BITSHIFT 4
+#define EMAC_TX_STATUS_CS16_ERROR (1L<<5)
+#define EMAC_TX_STATUS_CS16_ERROR_BITSHIFT 5
+#define EMAC_REG_EMAC_TX_LENGTHS 0xc4
+#define EMAC_TX_LENGTHS_SLOT (0xffL<<0)
+#define EMAC_TX_LENGTHS_SLOT_BITSHIFT 0
+#define EMAC_TX_LENGTHS_IPG (0xfL<<8)
+#define EMAC_TX_LENGTHS_IPG_BITSHIFT 8
+#define EMAC_TX_LENGTHS_IPG_CRS (0x3L<<12)
+#define EMAC_TX_LENGTHS_IPG_CRS_BITSHIFT 12
+#define EMAC_REG_EMAC_RX_MODE 0xc8
+#define EMAC_RX_MODE_RESET (1L<<0)
+#define EMAC_RX_MODE_RESET_BITSHIFT 0
+#define EMAC_RX_MODE_FLOW_EN (1L<<2)
+#define EMAC_RX_MODE_FLOW_EN_BITSHIFT 2
+#define EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)
+#define EMAC_RX_MODE_KEEP_MAC_CONTROL_BITSHIFT 3
+#define EMAC_RX_MODE_KEEP_PAUSE (1L<<4)
+#define EMAC_RX_MODE_KEEP_PAUSE_BITSHIFT 4
+#define EMAC_RX_MODE_ACCEPT_OVERSIZE (1L<<5)
+#define EMAC_RX_MODE_ACCEPT_OVERSIZE_BITSHIFT 5
+#define EMAC_RX_MODE_ACCEPT_RUNTS (1L<<6)
+#define EMAC_RX_MODE_ACCEPT_RUNTS_BITSHIFT 6
+#define EMAC_RX_MODE_LLC_CHK (1L<<7)
+#define EMAC_RX_MODE_LLC_CHK_BITSHIFT 7
+#define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
+#define EMAC_RX_MODE_PROMISCUOUS_BITSHIFT 8
+#define EMAC_RX_MODE_NO_CRC_CHK (1L<<9)
+#define EMAC_RX_MODE_NO_CRC_CHK_BITSHIFT 9
+#define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
+#define EMAC_RX_MODE_KEEP_VLAN_TAG_BITSHIFT 10
+#define EMAC_RX_MODE_FILT_BROADCAST (1L<<11)
+#define EMAC_RX_MODE_FILT_BROADCAST_BITSHIFT 11
+#define EMAC_RX_MODE_SORT_MODE (1L<<12)
+#define EMAC_RX_MODE_SORT_MODE_BITSHIFT 12
+#define EMAC_REG_EMAC_RX_STATUS 0xcc
+#define EMAC_RX_STATUS_FFED (1L<<0)
+#define EMAC_RX_STATUS_FFED_BITSHIFT 0
+#define EMAC_RX_STATUS_FF_RECEIVED (1L<<1)
+#define EMAC_RX_STATUS_FF_RECEIVED_BITSHIFT 1
+#define EMAC_RX_STATUS_N_RECEIVED (1L<<2)
+#define EMAC_RX_STATUS_N_RECEIVED_BITSHIFT 2
+#define EMAC_REG_EMAC_MULTICAST_HASH 0xd0
+#define EMAC_REG_EMAC_MULTICAST_HASH_COUNT 8
+#define EMAC_REG_EMAC_CKSUM_ERROR_STATUS 0xf0
+#define EMAC_CKSUM_ERROR_STATUS_CALCULATED (0xffffL<<0)
+#define EMAC_CKSUM_ERROR_STATUS_CALCULATED_BITSHIFT 0
+#define EMAC_CKSUM_ERROR_STATUS_EXPECTED (0xffffL<<16)
+#define EMAC_CKSUM_ERROR_STATUS_EXPECTED_BITSHIFT 16
+#define EMAC_REG_EMAC_UNUSED3 0xf4
+#define EMAC_REG_EMAC_UNUSED3_COUNT 3
+#define EMAC_REG_EMAC_RX_STAT_IFHCINOCTETS 0x100
+#define EMAC_REG_EMAC_RX_STAT_IFHCINBADOCTETS 0x104
+#define EMAC_REG_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x108
+#define EMAC_REG_EMAC_RX_STAT_IFHCINUCASTPKTS 0x10c
+#define EMAC_REG_EMAC_RX_STAT_IFHCINMULTICASTPKTS 0x110
+#define EMAC_REG_EMAC_RX_STAT_IFHCINBROADCASTPKTS 0x114
+#define EMAC_REG_EMAC_RX_STAT_DOT3STATSFCSERRORS 0x118
+#define EMAC_REG_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS 0x11c
+#define EMAC_REG_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS 0x120
+#define EMAC_REG_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED 0x124
+#define EMAC_REG_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED 0x128
+#define EMAC_REG_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED 0x12c
+#define EMAC_REG_EMAC_RX_STAT_XOFFSTATEENTERED 0x130
+#define EMAC_REG_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG 0x134
+#define EMAC_REG_EMAC_RX_STAT_ETHERSTATSJABBERS 0x138
+#define EMAC_REG_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS 0x13c
+#define EMAC_REG_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS 0x140
+#define EMAC_REG_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x144
+#define EMAC_REG_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x148
+#define EMAC_REG_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x14c
+#define EMAC_REG_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x150
+#define EMAC_REG_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS0x154
+#define EMAC_REG_EMAC_RX_STAT_ETHERSTATSPKTSOVER1522OCTETS 0x158
+#define EMAC_REG_EMAC_RXMAC_DEBUG0 0x15c
+#define EMAC_REG_EMAC_RXMAC_DEBUG1 0x160
+#define EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0)
+#define EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE (1L<<1)
+#define EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE_BITSHIFT 1
+#define EMAC_RXMAC_DEBUG1_BAD_CRC (1L<<2)
+#define EMAC_RXMAC_DEBUG1_BAD_CRC_BITSHIFT 2
+#define EMAC_RXMAC_DEBUG1_RX_ERROR (1L<<3)
+#define EMAC_RXMAC_DEBUG1_RX_ERROR_BITSHIFT 3
+#define EMAC_RXMAC_DEBUG1_ALIGN_ERROR (1L<<4)
+#define EMAC_RXMAC_DEBUG1_ALIGN_ERROR_BITSHIFT 4
+#define EMAC_RXMAC_DEBUG1_LAST_DATA (1L<<5)
+#define EMAC_RXMAC_DEBUG1_LAST_DATA_BITSHIFT 5
+#define EMAC_RXMAC_DEBUG1_ODD_BYTE_START (1L<<6)
+#define EMAC_RXMAC_DEBUG1_ODD_BYTE_START_BITSHIFT 6
+#define EMAC_RXMAC_DEBUG1_BYTE_COUNT (0xffffL<<7)
+#define EMAC_RXMAC_DEBUG1_BYTE_COUNT_BITSHIFT 7
+#define EMAC_RXMAC_DEBUG1_SLOT_TIME (0xffL<<23)
+#define EMAC_RXMAC_DEBUG1_SLOT_TIME_BITSHIFT 23
+#define EMAC_REG_EMAC_RXMAC_DEBUG2 0x164
+#define EMAC_RXMAC_DEBUG2_SM_STATE (0x7L<<0)
+#define EMAC_RXMAC_DEBUG2_SM_STATE_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG2_SM_STATE_IDLE (0L<<0)
+#define EMAC_RXMAC_DEBUG2_SM_STATE_IDLE_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG2_SM_STATE_SFD (1L<<0)
+#define EMAC_RXMAC_DEBUG2_SM_STATE_SFD_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG2_SM_STATE_DATA (2L<<0)
+#define EMAC_RXMAC_DEBUG2_SM_STATE_DATA_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP (3L<<0)
+#define EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG2_SM_STATE_EXT (4L<<0)
+#define EMAC_RXMAC_DEBUG2_SM_STATE_EXT_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG2_SM_STATE_DROP (5L<<0)
+#define EMAC_RXMAC_DEBUG2_SM_STATE_DROP_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG2_SM_STATE_SDROP (6L<<0)
+#define EMAC_RXMAC_DEBUG2_SM_STATE_SDROP_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG2_SM_STATE_FC (7L<<0)
+#define EMAC_RXMAC_DEBUG2_SM_STATE_FC_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG2_IDI_STATE (0xfL<<3)
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_BITSHIFT 3
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE (0L<<3)
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE_BITSHIFT 3
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0 (1L<<3)
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0_BITSHIFT 3
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1 (2L<<3)
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1_BITSHIFT 3
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2 (3L<<3)
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2_BITSHIFT 3
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3 (4L<<3)
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3_BITSHIFT 3
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT (5L<<3)
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT_BITSHIFT 3
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT (6L<<3)
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT_BITSHIFT 3
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS (7L<<3)
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS_BITSHIFT 3
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_LAST (8L<<3)
+#define EMAC_RXMAC_DEBUG2_IDI_STATE_LAST_BITSHIFT 3
+#define EMAC_RXMAC_DEBUG2_BYTE_IN (0xffL<<7)
+#define EMAC_RXMAC_DEBUG2_BYTE_IN_BITSHIFT 7
+#define EMAC_RXMAC_DEBUG2_FALSEC (1L<<15)
+#define EMAC_RXMAC_DEBUG2_FALSEC_BITSHIFT 15
+#define EMAC_RXMAC_DEBUG2_TAGGED (1L<<16)
+#define EMAC_RXMAC_DEBUG2_TAGGED_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG2_PAUSE_STATE (1L<<18)
+#define EMAC_RXMAC_DEBUG2_PAUSE_STATE_BITSHIFT 18
+#define EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0L<<18)
+#define EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE_BITSHIFT 18
+#define EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1L<<18)
+#define EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED_BITSHIFT 18
+#define EMAC_RXMAC_DEBUG2_SE_COUNTER (0xfL<<19)
+#define EMAC_RXMAC_DEBUG2_SE_COUNTER_BITSHIFT 19
+#define EMAC_RXMAC_DEBUG2_QUANTA (0x1fL<<23)
+#define EMAC_RXMAC_DEBUG2_QUANTA_BITSHIFT 23
+#define EMAC_REG_EMAC_RXMAC_DEBUG3 0x168
+#define EMAC_RXMAC_DEBUG3_PAUSE_CTR (0xffffL<<0)
+#define EMAC_RXMAC_DEBUG3_PAUSE_CTR_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR (0xffffL<<16)
+#define EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR_BITSHIFT 16
+#define EMAC_REG_EMAC_RXMAC_DEBUG4 0x16c
+#define EMAC_RXMAC_DEBUG4_TYPE_FIELD (0xffffL<<0)
+#define EMAC_RXMAC_DEBUG4_TYPE_FIELD_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG4_FILT_STATE (0x3fL<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE (0L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (1L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (2L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (3L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_UNI_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (5L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (6L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (7L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (7L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (8L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (9L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MC2_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MC3 (10L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MC3_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1 (14L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2 (15L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK (16L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MC (17L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MC_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_BC2 (18L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_BC2_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_BC3 (19L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_BC3_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1 (20L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2 (21L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3 (22L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE (23L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_BC (24L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_BC_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE (25L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_CMD (26L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_CMD_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MAC (27L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MAC_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH (28L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF (29L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_XON (30L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_XON_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED (31L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED (32L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE (33L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL (34L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_USA1 (35L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_USA1_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_USA2 (36L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_USA2_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_USA3 (37L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_USA3_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE (38L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE (39L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL (40L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE (41L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_DROP (42L<<16)
+#define EMAC_RXMAC_DEBUG4_FILT_STATE_DROP_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG4_DROP_PKT (1L<<22)
+#define EMAC_RXMAC_DEBUG4_DROP_PKT_BITSHIFT 22
+#define EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23)
+#define EMAC_RXMAC_DEBUG4_SLOT_FILLED_BITSHIFT 23
+#define EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24)
+#define EMAC_RXMAC_DEBUG4_FALSE_CARRIER_BITSHIFT 24
+#define EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25)
+#define EMAC_RXMAC_DEBUG4_LAST_DATA_BITSHIFT 25
+#define EMAC_RXMAC_DEBUG4_SFD_FOUND (1L<<26)
+#define EMAC_RXMAC_DEBUG4_SFD_FOUND_BITSHIFT 26
+#define EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27)
+#define EMAC_RXMAC_DEBUG4_ADVANCE_BITSHIFT 27
+#define EMAC_RXMAC_DEBUG4_START (1L<<28)
+#define EMAC_RXMAC_DEBUG4_START_BITSHIFT 28
+#define EMAC_REG_EMAC_RXMAC_DEBUG5 0x170
+#define EMAC_RXMAC_DEBUG5_PS_IDISM (0x7L<<0)
+#define EMAC_RXMAC_DEBUG5_PS_IDISM_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0L<<0)
+#define EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1L<<0)
+#define EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2L<<0)
+#define EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3L<<0)
+#define EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4L<<0)
+#define EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5L<<0)
+#define EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6L<<0)
+#define EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT_BITSHIFT 0
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF1 (0x7L<<4)
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF1_BITSHIFT 4
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW (0L<<4)
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW_BITSHIFT 4
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT (1L<<4)
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT_BITSHIFT 4
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF (2L<<4)
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF_BITSHIFT 4
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF (3L<<4)
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF_BITSHIFT 4
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF (4L<<4)
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF_BITSHIFT 4
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF (6L<<4)
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF_BITSHIFT 4
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF (7L<<4)
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF_BITSHIFT 4
+#define EMAC_RXMAC_DEBUG5_EOF_DETECTED (1L<<7)
+#define EMAC_RXMAC_DEBUG5_EOF_DETECTED_BITSHIFT 7
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF0 (0x7L<<8)
+#define EMAC_RXMAC_DEBUG5_CCODE_BUF0_BITSHIFT 8
+#define EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL (1L<<11)
+#define EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL_BITSHIFT 11
+#define EMAC_RXMAC_DEBUG5_LOAD_CCODE (1L<<12)
+#define EMAC_RXMAC_DEBUG5_LOAD_CCODE_BITSHIFT 12
+#define EMAC_RXMAC_DEBUG5_LOAD_DATA (1L<<13)
+#define EMAC_RXMAC_DEBUG5_LOAD_DATA_BITSHIFT 13
+#define EMAC_RXMAC_DEBUG5_LOAD_STAT (1L<<14)
+#define EMAC_RXMAC_DEBUG5_LOAD_STAT_BITSHIFT 14
+#define EMAC_RXMAC_DEBUG5_CLR_STAT (1L<<15)
+#define EMAC_RXMAC_DEBUG5_CLR_STAT_BITSHIFT 15
+#define EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE (0x3L<<16)
+#define EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE_BITSHIFT 16
+#define EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19)
+#define EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT_BITSHIFT 19
+#define EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20)
+#define EMAC_RXMAC_DEBUG5_FMLEN_BITSHIFT 20
+#define EMAC_REG_EMAC_RX_STAT_FALSECARRIERERRORS 0x174
+#define EMAC_REG_EMAC_UNUSED4 0x178
+#define EMAC_REG_EMAC_UNUSED4_COUNT 2
+#define EMAC_REG_EMAC_RX_STAT_AC 0x180
+#define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
+#define EMAC_REG_EMAC_RXMAC_SUC_DBG_OVERRUNVEC 0x1dc
+#define EMAC_REG_EMAC_UNUSED5 0x1e0
+#define EMAC_REG_EMAC_UNUSED5_COUNT 5
+#define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
+#define EMAC_REG_EMAC_UNUSED9 0x1f8
+#define EMAC_REG_EMAC_UNUSED9_COUNT 2
+#define EMAC_REG_EMAC_TX_STAT_IFHCOUTOCTETS 0x200
+#define EMAC_REG_EMAC_TX_STAT_IFHCOUTBADOCTETS 0x204
+#define EMAC_REG_EMAC_TX_STAT_ETHERSTATSCOLLISIONS 0x208
+#define EMAC_REG_EMAC_TX_STAT_OUTXONSENT 0x20c
+#define EMAC_REG_EMAC_TX_STAT_OUTXOFFSENT 0x210
+#define EMAC_REG_EMAC_TX_STAT_FLOWCONTROLDONE 0x214
+#define EMAC_REG_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES 0x218
+#define EMAC_REG_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES 0x21c
+#define EMAC_REG_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS 0x220
+#define EMAC_REG_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS 0x224
+#define EMAC_REG_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS 0x228
+#define EMAC_REG_EMAC_TX_STAT_IFHCOUTUCASTPKTS 0x22c
+#define EMAC_REG_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS 0x230
+#define EMAC_REG_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS 0x234
+#define EMAC_REG_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS 0x238
+#define EMAC_REG_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x23c
+#define EMAC_REG_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x240
+#define EMAC_REG_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x244
+#define EMAC_REG_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x248
+#define EMAC_REG_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS0x24c
+#define EMAC_REG_EMAC_TX_STAT_ETHERSTATSPKTSOVER1522OCTETS 0x250
+#define EMAC_REG_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS 0x254
+#define EMAC_REG_EMAC_TXMAC_DEBUG0 0x258
+#define EMAC_REG_EMAC_TXMAC_DEBUG1 0x25c
+#define EMAC_TXMAC_DEBUG1_ODI_STATE (0xfL<<0)
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE (0L<<0)
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_START0 (1L<<0)
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_START0_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0 (4L<<0)
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1 (5L<<0)
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2 (6L<<0)
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3 (7L<<0)
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0 (8L<<0)
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1 (9L<<0)
+#define EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG1_CRS_ENABLE (1L<<4)
+#define EMAC_TXMAC_DEBUG1_CRS_ENABLE_BITSHIFT 4
+#define EMAC_TXMAC_DEBUG1_BAD_CRC (1L<<5)
+#define EMAC_TXMAC_DEBUG1_BAD_CRC_BITSHIFT 5
+#define EMAC_TXMAC_DEBUG1_SE_COUNTER (0xfL<<6)
+#define EMAC_TXMAC_DEBUG1_SE_COUNTER_BITSHIFT 6
+#define EMAC_TXMAC_DEBUG1_SEND_PAUSE (1L<<10)
+#define EMAC_TXMAC_DEBUG1_SEND_PAUSE_BITSHIFT 10
+#define EMAC_TXMAC_DEBUG1_LATE_COLLISION (1L<<11)
+#define EMAC_TXMAC_DEBUG1_LATE_COLLISION_BITSHIFT 11
+#define EMAC_TXMAC_DEBUG1_MAX_DEFER (1L<<12)
+#define EMAC_TXMAC_DEBUG1_MAX_DEFER_BITSHIFT 12
+#define EMAC_TXMAC_DEBUG1_DEFERRED (1L<<13)
+#define EMAC_TXMAC_DEBUG1_DEFERRED_BITSHIFT 13
+#define EMAC_TXMAC_DEBUG1_ONE_BYTE (1L<<14)
+#define EMAC_TXMAC_DEBUG1_ONE_BYTE_BITSHIFT 14
+#define EMAC_TXMAC_DEBUG1_IPG_TIME (0xfL<<15)
+#define EMAC_TXMAC_DEBUG1_IPG_TIME_BITSHIFT 15
+#define EMAC_TXMAC_DEBUG1_SLOT_TIME (0xffL<<19)
+#define EMAC_TXMAC_DEBUG1_SLOT_TIME_BITSHIFT 19
+#define EMAC_REG_EMAC_TXMAC_DEBUG2 0x260
+#define EMAC_TXMAC_DEBUG2_BACK_OFF (0x3ffL<<0)
+#define EMAC_TXMAC_DEBUG2_BACK_OFF_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG2_BYTE_COUNT (0xffffL<<10)
+#define EMAC_TXMAC_DEBUG2_BYTE_COUNT_BITSHIFT 10
+#define EMAC_TXMAC_DEBUG2_COL_COUNT (0x1fL<<26)
+#define EMAC_TXMAC_DEBUG2_COL_COUNT_BITSHIFT 26
+#define EMAC_TXMAC_DEBUG2_COL_BIT (1L<<31)
+#define EMAC_TXMAC_DEBUG2_COL_BIT_BITSHIFT 31
+#define EMAC_REG_EMAC_TXMAC_DEBUG3 0x264
+#define EMAC_TXMAC_DEBUG3_SM_STATE (0xfL<<0)
+#define EMAC_TXMAC_DEBUG3_SM_STATE_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG3_SM_STATE_IDLE (0L<<0)
+#define EMAC_TXMAC_DEBUG3_SM_STATE_IDLE_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG3_SM_STATE_PRE1 (1L<<0)
+#define EMAC_TXMAC_DEBUG3_SM_STATE_PRE1_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG3_SM_STATE_PRE2 (2L<<0)
+#define EMAC_TXMAC_DEBUG3_SM_STATE_PRE2_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG3_SM_STATE_SFD (3L<<0)
+#define EMAC_TXMAC_DEBUG3_SM_STATE_SFD_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG3_SM_STATE_DATA (4L<<0)
+#define EMAC_TXMAC_DEBUG3_SM_STATE_DATA_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG3_SM_STATE_CRC1 (5L<<0)
+#define EMAC_TXMAC_DEBUG3_SM_STATE_CRC1_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG3_SM_STATE_CRC2 (6L<<0)
+#define EMAC_TXMAC_DEBUG3_SM_STATE_CRC2_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG3_SM_STATE_EXT (7L<<0)
+#define EMAC_TXMAC_DEBUG3_SM_STATE_EXT_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG3_SM_STATE_STATB (8L<<0)
+#define EMAC_TXMAC_DEBUG3_SM_STATE_STATB_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG3_SM_STATE_STATG (9L<<0)
+#define EMAC_TXMAC_DEBUG3_SM_STATE_STATG_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG3_SM_STATE_JAM (10L<<0)
+#define EMAC_TXMAC_DEBUG3_SM_STATE_JAM_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG3_SM_STATE_EJAM (11L<<0)
+#define EMAC_TXMAC_DEBUG3_SM_STATE_EJAM_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG3_SM_STATE_BJAM (12L<<0)
+#define EMAC_TXMAC_DEBUG3_SM_STATE_BJAM_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT (13L<<0)
+#define EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF (14L<<0)
+#define EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG3_FILT_STATE (0x7L<<4)
+#define EMAC_TXMAC_DEBUG3_FILT_STATE_BITSHIFT 4
+#define EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE (0L<<4)
+#define EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE_BITSHIFT 4
+#define EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT (1L<<4)
+#define EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT_BITSHIFT 4
+#define EMAC_TXMAC_DEBUG3_FILT_STATE_UNI (2L<<4)
+#define EMAC_TXMAC_DEBUG3_FILT_STATE_UNI_BITSHIFT 4
+#define EMAC_TXMAC_DEBUG3_FILT_STATE_MC (3L<<4)
+#define EMAC_TXMAC_DEBUG3_FILT_STATE_MC_BITSHIFT 4
+#define EMAC_TXMAC_DEBUG3_FILT_STATE_BC2 (4L<<4)
+#define EMAC_TXMAC_DEBUG3_FILT_STATE_BC2_BITSHIFT 4
+#define EMAC_TXMAC_DEBUG3_FILT_STATE_BC3 (5L<<4)
+#define EMAC_TXMAC_DEBUG3_FILT_STATE_BC3_BITSHIFT 4
+#define EMAC_TXMAC_DEBUG3_FILT_STATE_BC (6L<<4)
+#define EMAC_TXMAC_DEBUG3_FILT_STATE_BC_BITSHIFT 4
+#define EMAC_TXMAC_DEBUG3_CRS_DONE (1L<<7)
+#define EMAC_TXMAC_DEBUG3_CRS_DONE_BITSHIFT 7
+#define EMAC_TXMAC_DEBUG3_XOFF (1L<<8)
+#define EMAC_TXMAC_DEBUG3_XOFF_BITSHIFT 8
+#define EMAC_TXMAC_DEBUG3_SE_COUNTER (0xfL<<9)
+#define EMAC_TXMAC_DEBUG3_SE_COUNTER_BITSHIFT 9
+#define EMAC_TXMAC_DEBUG3_QUANTA_COUNTER (0x1fL<<13)
+#define EMAC_TXMAC_DEBUG3_QUANTA_COUNTER_BITSHIFT 13
+#define EMAC_REG_EMAC_TXMAC_DEBUG4 0x268
+#define EMAC_TXMAC_DEBUG4_PAUSE_COUNTER (0xffffL<<0)
+#define EMAC_TXMAC_DEBUG4_PAUSE_COUNTER_BITSHIFT 0
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE (0xfL<<16)
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_BITSHIFT 16
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0L<<16)
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE_BITSHIFT 16
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (2L<<16)
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1_BITSHIFT 16
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (3L<<16)
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2_BITSHIFT 16
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (4L<<16)
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3_BITSHIFT 16
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (5L<<16)
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2_BITSHIFT 16
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (6L<<16)
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3_BITSHIFT 16
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (7L<<16)
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1_BITSHIFT 16
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (8L<<16)
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1_BITSHIFT 16
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (9L<<16)
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2_BITSHIFT 16
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (10L<<16)
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME_BITSHIFT 16
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (12L<<16)
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE_BITSHIFT 16
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (13L<<16)
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT_BITSHIFT 16
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (14L<<16)
+#define EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD_BITSHIFT 16
+#define EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20)
+#define EMAC_TXMAC_DEBUG4_STATS0_VALID_BITSHIFT 20
+#define EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21)
+#define EMAC_TXMAC_DEBUG4_APPEND_CRC_BITSHIFT 21
+#define EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22)
+#define EMAC_TXMAC_DEBUG4_SLOT_FILLED_BITSHIFT 22
+#define EMAC_TXMAC_DEBUG4_MAX_DEFER (1L<<23)
+#define EMAC_TXMAC_DEBUG4_MAX_DEFER_BITSHIFT 23
+#define EMAC_TXMAC_DEBUG4_SEND_EXTEND (1L<<24)
+#define EMAC_TXMAC_DEBUG4_SEND_EXTEND_BITSHIFT 24
+#define EMAC_TXMAC_DEBUG4_SEND_PADDING (1L<<25)
+#define EMAC_TXMAC_DEBUG4_SEND_PADDING_BITSHIFT 25
+#define EMAC_TXMAC_DEBUG4_EOF_LOC (1L<<26)
+#define EMAC_TXMAC_DEBUG4_EOF_LOC_BITSHIFT 26
+#define EMAC_TXMAC_DEBUG4_COLLIDING (1L<<27)
+#define EMAC_TXMAC_DEBUG4_COLLIDING_BITSHIFT 27
+#define EMAC_TXMAC_DEBUG4_COL_IN (1L<<28)
+#define EMAC_TXMAC_DEBUG4_COL_IN_BITSHIFT 28
+#define EMAC_TXMAC_DEBUG4_BURSTING (1L<<29)
+#define EMAC_TXMAC_DEBUG4_BURSTING_BITSHIFT 29
+#define EMAC_TXMAC_DEBUG4_ADVANCE (1L<<30)
+#define EMAC_TXMAC_DEBUG4_ADVANCE_BITSHIFT 30
+#define EMAC_TXMAC_DEBUG4_GO (1L<<31)
+#define EMAC_TXMAC_DEBUG4_GO_BITSHIFT 31
+#define EMAC_REG_EMAC_UNUSED6 0x26c
+#define EMAC_REG_EMAC_UNUSED6_COUNT 5
+#define EMAC_REG_EMAC_TX_STAT_AC 0x280
+#define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
+#define EMAC_REG_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x2d8
+#define EMAC_REG_EMAC_UNUSED7 0x2dc
+#define EMAC_REG_EMAC_UNUSED7_COUNT 8
+#define EMAC_REG_EMAC_TX_RATE_LIMIT_CTRL 0x2fc
+#define EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_INC (0x7fL<<0)
+#define EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_INC_BITSHIFT 0
+#define EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_NUM (0x7fL<<16)
+#define EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_NUM_BITSHIFT 16
+#define EMAC_TX_RATE_LIMIT_CTRL_RATE_LIMITER_EN (1L<<31)
+#define EMAC_TX_RATE_LIMIT_CTRL_RATE_LIMITER_EN_BITSHIFT 31
+#define EMAC_REG_EMAC_UNUSED8 0x300
+#define EMAC_REG_EMAC_UNUSED8_COUNT 64
+#endif
+#define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
+#define EMAC_MDIO_COMM_COMMAND_ADDRESS_BITSHIFT 26
+#define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26)
+#define EMAC_MDIO_COMM_COMMAND_READ_22_BITSHIFT 26
+#define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
+#define EMAC_MDIO_COMM_COMMAND_READ_45_BITSHIFT 26
+#define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26)
+#define EMAC_MDIO_COMM_COMMAND_WRITE_22_BITSHIFT 26
+#define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
+#define EMAC_MDIO_COMM_COMMAND_WRITE_45_BITSHIFT 26
+#define EMAC_MDIO_COMM_DATA (0xffffL<<0)
+#define EMAC_MDIO_COMM_DATA_BITSHIFT 0
+#define EMAC_MDIO_COMM_START_BUSY (1L<<29)
+#define EMAC_MDIO_COMM_START_BUSY_BITSHIFT 29
+#define EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
+#define EMAC_MDIO_MODE_AUTO_POLL_BITSHIFT 4
+#define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31)
+#define EMAC_MDIO_MODE_CLAUSE_45_BITSHIFT 31
+#define EMAC_MODE_25G_MODE (1L<<5)
+#define EMAC_MODE_25G_MODE_BITSHIFT 5
+#define EMAC_MODE_ACPI_RCVD (1L<<20)
+#define EMAC_MODE_ACPI_RCVD_BITSHIFT 20
+#define EMAC_MODE_HALF_DUPLEX (1L<<1)
+#define EMAC_MODE_HALF_DUPLEX_BITSHIFT 1
+#define EMAC_MODE_MPKT (1L<<18)
+#define EMAC_MODE_MPKT_BITSHIFT 18
+#define EMAC_MODE_MPKT_RCVD (1L<<19)
+#define EMAC_MODE_MPKT_RCVD_BITSHIFT 19
+#define EMAC_MODE_MPKT_RCVD (1L<<19)
+#define EMAC_MODE_MPKT_RCVD_BITSHIFT 19
+#define EMAC_MODE_PORT_GMII (2L<<2)
+#define EMAC_MODE_PORT_GMII_BITSHIFT 2
+#define EMAC_MODE_PORT_MII (1L<<2)
+#define EMAC_MODE_PORT_MII_BITSHIFT 2
+#define EMAC_MODE_PORT_MII_10M (3L<<2)
+#define EMAC_MODE_PORT_MII_10M_BITSHIFT 2
+#define EMAC_MODE_PORT_MII_10M (3L<<2)
+#define EMAC_MODE_PORT_MII_10M_BITSHIFT 2
+#define EMAC_MODE_RESET (1L<<0)
+#define EMAC_MODE_RESET_BITSHIFT 0
+#define EMAC_REG_EMAC_MAC_MATCH 0x10
+#define EMAC_REG_EMAC_MAC_MATCH_COUNT 32
+#define EMAC_REG_EMAC_MDIO_COMM 0xac
+#define EMAC_REG_EMAC_MDIO_MODE 0xb4
+#define EMAC_REG_EMAC_MODE 0x0
+#define EMAC_REG_EMAC_RX_MODE 0xc8
+#define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
+#define EMAC_REG_EMAC_RX_STAT_AC 0x180
+#define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
+#define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
+#define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
+#define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
+#define EMAC_REG_EMAC_TX_MODE 0xbc
+#define EMAC_REG_EMAC_TX_STAT_AC 0x280
+#define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
+#define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
+#define EMAC_RX_MODE_FLOW_EN (1L<<2)
+#define EMAC_RX_MODE_FLOW_EN_BITSHIFT 2
+#define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
+#define EMAC_RX_MODE_KEEP_VLAN_TAG_BITSHIFT 10
+#define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
+#define EMAC_RX_MODE_PROMISCUOUS_BITSHIFT 8
+#define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
+#define EMAC_RX_MTU_SIZE_JUMBO_ENA_BITSHIFT 31
+#define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
+#define EMAC_TX_MODE_EXT_PAUSE_EN_BITSHIFT 3
+#define EMAC_TX_MODE_RESET (1L<<0)
+#define EMAC_TX_MODE_RESET_BITSHIFT 0
+#define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x6424
+#define MCP_REG_MCPR_NVM_ADDR 0x640c
+#define MCP_REG_MCPR_NVM_CFG4 0x642c
+#define MCP_REG_MCPR_NVM_COMMAND 0x6400
+#define MCP_REG_MCPR_NVM_READ 0x6410
+#define MCP_REG_MCPR_NVM_SW_ARB 0x6420
+#define MCP_REG_MCPR_NVM_WRITE 0x6408
+#define MCP_REG_MCPR_NVM_WRITE1 0x6428
+#define MCP_REG_MCPR_SCRATCH 0x20000
+#define MCP_REG_MCPR_SCRATCH_COUNT 16384
+#define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)
+#define MCPR_NVM_ACCESS_ENABLE_EN_BITSHIFT 0
+#define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
+#define MCPR_NVM_ACCESS_ENABLE_WR_EN_BITSHIFT 1
+#define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
+#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_BITSHIFT 0
+#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0)
+#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG_BITSHIFT 0
+#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_SI (1L<<0)
+#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_SI_BITSHIFT 0
+#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_SO (2L<<0)
+#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_SO_BITSHIFT 0
+#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_CS_B (4L<<0)
+#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_CS_B_BITSHIFT 0
+#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_SCLK (8L<<0)
+#define MCPR_NVM_ADDR_NVM_ADDR_VALUE_SCLK_BITSHIFT 0
+#define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0)
+#define MCPR_NVM_CFG4_FLASH_SIZE_BITSHIFT 0
+#define MCPR_NVM_CFG4_FLASH_SIZE_1MBIT (0L<<0)
+#define MCPR_NVM_CFG4_FLASH_SIZE_1MBIT_BITSHIFT 0
+#define MCPR_NVM_CFG4_FLASH_SIZE_2MBIT (1L<<0)
+#define MCPR_NVM_CFG4_FLASH_SIZE_2MBIT_BITSHIFT 0
+#define MCPR_NVM_CFG4_FLASH_SIZE_4MBIT (2L<<0)
+#define MCPR_NVM_CFG4_FLASH_SIZE_4MBIT_BITSHIFT 0
+#define MCPR_NVM_CFG4_FLASH_SIZE_8MBIT (3L<<0)
+#define MCPR_NVM_CFG4_FLASH_SIZE_8MBIT_BITSHIFT 0
+#define MCPR_NVM_CFG4_FLASH_SIZE_16MBIT (4L<<0)
+#define MCPR_NVM_CFG4_FLASH_SIZE_16MBIT_BITSHIFT 0
+#define MCPR_NVM_CFG4_FLASH_SIZE_32MBIT (5L<<0)
+#define MCPR_NVM_CFG4_FLASH_SIZE_32MBIT_BITSHIFT 0
+#define MCPR_NVM_CFG4_FLASH_SIZE_64MBIT (6L<<0)
+#define MCPR_NVM_CFG4_FLASH_SIZE_64MBIT_BITSHIFT 0
+#define MCPR_NVM_CFG4_FLASH_SIZE_128MBIT (7L<<0)
+#define MCPR_NVM_CFG4_FLASH_SIZE_128MBIT_BITSHIFT 0
+#define MCPR_NVM_COMMAND_DOIT (1L<<4)
+#define MCPR_NVM_COMMAND_DOIT_BITSHIFT 4
+#define MCPR_NVM_COMMAND_DONE (1L<<3)
+#define MCPR_NVM_COMMAND_DONE_BITSHIFT 3
+#define MCPR_NVM_COMMAND_FIRST (1L<<7)
+#define MCPR_NVM_COMMAND_FIRST_BITSHIFT 7
+#define MCPR_NVM_COMMAND_LAST (1L<<8)
+#define MCPR_NVM_COMMAND_LAST_BITSHIFT 8
+#define MCPR_NVM_COMMAND_WR (1L<<5)
+#define MCPR_NVM_COMMAND_WR_BITSHIFT 5
+#define MCPR_NVM_COMMAND_WREN (1L<<16)
+#define MCPR_NVM_COMMAND_WREN_BITSHIFT 16
+#define MCPR_NVM_COMMAND_WRDI (1L<<17)
+#define MCPR_NVM_COMMAND_WRDI_BITSHIFT 17
+#define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9)
+#define MCPR_NVM_SW_ARB_ARB_ARB1_BITSHIFT 9
+#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
+#define MCPR_NVM_SW_ARB_ARB_REQ_CLR1_BITSHIFT 5
+#define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
+#define MCPR_NVM_SW_ARB_ARB_REQ_SET1_BITSHIFT 1
+#define MISC_REGISTERS_RESET_REG_1_SET MISC_REGISTERS_RESET_REG_1+4
+#define MISC_REGISTERS_RESET_REG_1_CLEAR MISC_REGISTERS_RESET_REG_1+8
+#define MISC_REGISTERS_RESET_REG_1_RST_BRB1 (0x1<<0)
+#define MISC_REGISTERS_RESET_REG_1_RST_PRS (0x1<<1)
+#define MISC_REGISTERS_RESET_REG_1_RST_SRC (0x1<<2)
+#define MISC_REGISTERS_RESET_REG_1_RST_TSDM (0x1<<3)
+#define MISC_REGISTERS_RESET_REG_1_RST_TSEM (0x1<<4)
+#define MISC_REGISTERS_RESET_REG_1_RST_TCM (0x1<<5)
+#define MISC_REGISTERS_RESET_REG_1_RST_RBCR (0x1<<6)
+#define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7)
+#define MISC_REGISTERS_RESET_REG_1_RST_USDM (0x1<<8)
+#define MISC_REGISTERS_RESET_REG_1_RST_UCM (0x1<<9)
+#define MISC_REGISTERS_RESET_REG_1_RST_USEM (0x1<<10)
+#define MISC_REGISTERS_RESET_REG_1_RST_UPB (0x1<<11)
+#define MISC_REGISTERS_RESET_REG_1_RST_CCM (0x1<<12)
+#define MISC_REGISTERS_RESET_REG_1_RST_CSEM (0x1<<13)
+#define MISC_REGISTERS_RESET_REG_1_RST_CSDM (0x1<<14)
+#define MISC_REGISTERS_RESET_REG_1_RST_RBCU (0x1<<15)
+#define MISC_REGISTERS_RESET_REG_1_RST_PBF (0x1<<16)
+#define MISC_REGISTERS_RESET_REG_1_RST_QM (0x1<<17)
+#define MISC_REGISTERS_RESET_REG_1_RST_TM (0x1<<18)
+#define MISC_REGISTERS_RESET_REG_1_RST_DORQ (0x1<<19)
+#define MISC_REGISTERS_RESET_REG_1_RST_XCM (0x1<<20)
+#define MISC_REGISTERS_RESET_REG_1_RST_XSDM (0x1<<21)
+#define MISC_REGISTERS_RESET_REG_1_RST_XSEM (0x1<<22)
+#define MISC_REGISTERS_RESET_REG_1_RST_RBCT (0x1<<23)
+#define MISC_REGISTERS_RESET_REG_1_RST_CDU (0x1<<24)
+#define MISC_REGISTERS_RESET_REG_1_RST_CFC (0x1<<25)
+#define MISC_REGISTERS_RESET_REG_1_RST_PXP (0x1<<26)
+#define MISC_REGISTERS_RESET_REG_1_RST_PXPV (0x1<<27)
+#define MISC_REGISTERS_RESET_REG_1_RST_RBCP (0x1<<28)
+#define MISC_REGISTERS_RESET_REG_1_RST_HC (0x1<<29)
+#define MISC_REGISTERS_RESET_REG_1_RST_DMAE (0x1<<30)
+#define MISC_REGISTERS_RESET_REG_1_RST_SEMI_RTC (0x1<<31)
+#define MISC_REGISTERS_RESET_REG_2_SET MISC_REGISTERS_RESET_REG_2+4
+#define MISC_REGISTERS_RESET_REG_2_CLEAR MISC_REGISTERS_RESET_REG_2+8
+#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
+#define MISC_REGISTERS_RESET_REG_2_RST_BMAC1 (0x1<<1)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0 (0x1<<2)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1 (0x1<<3)
+#define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1<<7)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1<<8)
+#define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9)
+#define MISC_REGISTERS_RESET_REG_2_RST_DBG (0x1<<10)
+#define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE (0x1<<11)
+#define MISC_REGISTERS_RESET_REG_2_RST_DBUE (0x1<<12)
+#define MISC_REGISTERS_RESET_REG_2_RST_MDIO (0x1<<13)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE (0x1<<15)
+#define MISC_REGISTERS_RESET_REG_3_SET MISC_REGISTERS_RESET_REG_3+4
+#define MISC_REGISTERS_RESET_REG_3_CLEAR MISC_REGISTERS_RESET_REG_3+8
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB 
(0x1<<8)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES1_RSTB_HW (0x1<<16)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES1_IDDQ (0x1<<17)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES1_PWRDWN (0x1<<18)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES1_PWRDWN_SD (0x1<<19)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS1_RSTB_HW (0x1<<20)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS1_IDDQ (0x1<<21)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS1_PWRDWN (0x1<<22)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS1_PWRDWN_SD (0x1<<23)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS1_TXD_FIFO_RSTB 
(0x1<<24)
+#define MISC_REGISTERS_RESET_REG_1_SET MISC_REGISTERS_RESET_REG_1+4
+#define MISC_REGISTERS_RESET_REG_1_CLEAR MISC_REGISTERS_RESET_REG_1+8
+#define MISC_REGISTERS_RESET_REG_1_RST_BRB1 (0x1<<0)
+#define MISC_REGISTERS_RESET_REG_1_RST_PRS (0x1<<1)
+#define MISC_REGISTERS_RESET_REG_1_RST_SRC (0x1<<2)
+#define MISC_REGISTERS_RESET_REG_1_RST_TSDM (0x1<<3)
+#define MISC_REGISTERS_RESET_REG_1_RST_TSEM (0x1<<4)
+#define MISC_REGISTERS_RESET_REG_1_RST_TCM (0x1<<5)
+#define MISC_REGISTERS_RESET_REG_1_RST_RBCR (0x1<<6)
+#define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7)
+#define MISC_REGISTERS_RESET_REG_1_RST_USDM (0x1<<8)
+#define MISC_REGISTERS_RESET_REG_1_RST_UCM (0x1<<9)
+#define MISC_REGISTERS_RESET_REG_1_RST_USEM (0x1<<10)
+#define MISC_REGISTERS_RESET_REG_1_RST_UPB (0x1<<11)
+#define MISC_REGISTERS_RESET_REG_1_RST_CCM (0x1<<12)
+#define MISC_REGISTERS_RESET_REG_1_RST_CSEM (0x1<<13)
+#define MISC_REGISTERS_RESET_REG_1_RST_CSDM (0x1<<14)
+#define MISC_REGISTERS_RESET_REG_1_RST_RBCU (0x1<<15)
+#define MISC_REGISTERS_RESET_REG_1_RST_PBF (0x1<<16)
+#define MISC_REGISTERS_RESET_REG_1_RST_QM (0x1<<17)
+#define MISC_REGISTERS_RESET_REG_1_RST_TM (0x1<<18)
+#define MISC_REGISTERS_RESET_REG_1_RST_DORQ (0x1<<19)
+#define MISC_REGISTERS_RESET_REG_1_RST_XCM (0x1<<20)
+#define MISC_REGISTERS_RESET_REG_1_RST_XSDM (0x1<<21)
+#define MISC_REGISTERS_RESET_REG_1_RST_XSEM (0x1<<22)
+#define MISC_REGISTERS_RESET_REG_1_RST_RBCT (0x1<<23)
+#define MISC_REGISTERS_RESET_REG_1_RST_CDU (0x1<<24)
+#define MISC_REGISTERS_RESET_REG_1_RST_CFC (0x1<<25)
+#define MISC_REGISTERS_RESET_REG_1_RST_PXP (0x1<<26)
+#define MISC_REGISTERS_RESET_REG_1_RST_PXPV (0x1<<27)
+#define MISC_REGISTERS_RESET_REG_1_RST_RBCP (0x1<<28)
+#define MISC_REGISTERS_RESET_REG_1_RST_HC (0x1<<29)
+#define MISC_REGISTERS_RESET_REG_1_RST_DMAE (0x1<<30)
+#define MISC_REGISTERS_RESET_REG_1_RST_SEMI_RTC (0x1<<31)
+#define MISC_REGISTERS_RESET_REG_1_CLEAR MISC_REGISTERS_RESET_REG_1+8
+#define MISC_REGISTERS_RESET_REG_1_SET MISC_REGISTERS_RESET_REG_1+4
+#define MISC_REGISTERS_RESET_REG_2_SET MISC_REGISTERS_RESET_REG_2+4
+#define MISC_REGISTERS_RESET_REG_2_CLEAR MISC_REGISTERS_RESET_REG_2+8
+#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
+#define MISC_REGISTERS_RESET_REG_2_RST_BMAC1 (0x1<<1)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0 (0x1<<2)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1 (0x1<<3)
+#define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1<<7)
+#define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1<<8)
+#define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9)
+#define MISC_REGISTERS_RESET_REG_2_RST_DBG (0x1<<10)
+#define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE (0x1<<11)
+#define MISC_REGISTERS_RESET_REG_2_RST_DBUE (0x1<<12)
+#define MISC_REGISTERS_RESET_REG_2_RST_MDIO (0x1<<13)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE (0x1<<15)
+#define MISC_REGISTERS_RESET_REG_2_CLEAR MISC_REGISTERS_RESET_REG_2+8
+#define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
+#define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14)
+#define MISC_REGISTERS_RESET_REG_2_SET MISC_REGISTERS_RESET_REG_2+4
+#define MISC_REGISTERS_RESET_REG_3_CLEAR MISC_REGISTERS_RESET_REG_3+8
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4)
+#define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB 
(0x1<<8)
+#define MISC_REGISTERS_RESET_REG_3_SET MISC_REGISTERS_RESET_REG_3+4
+#define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (1<<13)
+#define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (1<<3)
+#ifndef __5710_INT_OFFSETS__
+#define __5710_INT_OFFSETS__
+
+#define TSTORM_PORT_COMMON_CONFIG_OFFSET(port) (0x1500 + (port * 0x28))
+#define TSTORM_MAC_FILTER_CONFIG_OFFSET(port) (0x1504 + (port * 0x28))
+#define TSTORM_RCQ_PROD_OFFSET(port, client_id) (0x15e0 + (port * 
0x1b0) + \
+(client_id * 0x18))
+#define TSTORM_RCQ_PROD_SIZE 0x2
+#define TSTORM_CLIENT_CONFIG_OFFSET(port, client_id) (0x15e8 + \
+(port * 0x1b0) + (client_id * 0x18))
+#define USTORM_BYTE_COUNTER_OFFSET(port, cpuID) (0x1d94 + \
+(port * 0x90) + (cpuID * 0x8))
+#define USTORM_BYTE_COUNTER_SIZE 0x4
+#define USTORM_DYNAMIC_HC_CONFIG_OFFSET(port) (0x1d80 + \
+(port * 0x90))
+#define USTORM_DYNAMIC_HC_CONFIG_SIZE 0x10
+#define USTORM_GRQ_CACHE_BD_LO_OFFSET(cpu_id, port, grq_bd_num) \
+(0x3000 + (cpu_id * 0x100) + (port * 0x80) + (grq_bd_num * 0x8))
+#define USTORM_GRQ_CACHE_BD_HI_OFFSET(cpu_id, port, grq_bd_num) \
+(0x3004 + (cpu_id * 0x100) + (port * 0x80) + (grq_bd_num * 0x8))
+#define COMMON_SB_HOST_SB_ADDR_SIZE 0x8
+#define COMMON_SB_HC_TIMEOUT_SIZE 0x1
+#define COMMON_SB_HC_DISABLE_SIZE 0x2
+#define COMMON_HC_BTR_SIZE 0x4
+#define COMMON_ASM_ASSERT_MSG_SIZE 0x10
+#define COMMON_ASM_ASSERT_INDEX_SIZE 0x8
+#define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
+#define XSTORM_SPQ_PAGE_BASE_OFFSET(port) (0x5328 + (port * 0x18))
+#define XSTORM_SPQ_PAGE_BASE_SIZE 0x8
+#define XSTORM_SPQ_PROD_OFFSET(port) (0x5330 + (port * 0x18))
+#define XSTORM_SPQ_PROD_SIZE 0x4
+#define XSTORM_VIRTUALIZATION_MODE_OFFSET 0x5120
+#define XSTORM_VIRTUALIZATION_MODE_SIZE 0x8
+#define XSTORM_JUMBO_SUPPORT_OFFSET(port) (0x5370 + (port * 0x4))
+#define XSTORM_JUMBO_SUPPORT_SIZE 0x1
+#define XSTORM_COMMON_IP_ID_MASK_OFFSET 0x5378
+#define XSTORM_COMMON_IP_ID_MASK_SIZE 0x2
+#define XSTORM_COMMON_RTC_PARAMS_OFFSET 0x5380
+#define XSTORM_COMMON_RTC_PARAMS_SIZE 0x8
+#define XSTORM_COMMON_RTC_RESOLUTION_OFFSET 0x5384
+#define XSTORM_COMMON_RTC_RESOLUTION_SIZE 0x2
+#define XSTORM_FW_VERSION_OFFSET 0x5428
+#define XSTORM_FW_VERSION_SIZE 0x8
+#define XSTORM_STATS_FLAGS_OFFSET(port) (0x53f8 + (port * 0x8))
+#define XSTORM_STATS_FLAGS_SIZE 0x8
+#define XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port) (0x5408 + (port * 0x8))
+#define XSTORM_ETH_STATS_QUERY_ADDR_SIZE 0x8
+#define XSTORM_CMNG_VARS_OFFSET(port) (0x5438 + (port * 0xc0))
+#define XSTORM_CMNG_VARS_SIZE 0xc0
+#define XSTORM_COS2PROTOCOL_OFFSET(port) (0x55b8 + (port * 0x10))
+#define XSTORM_COS2PROTOCOL_SIZE 0x10
+#define XSTORM_CON_NUMBER_OFFSET(port) (0x54f0 + (port * 0x438))
+#define XSTORM_CON_NUMBER_SIZE 0x4
+#define XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port) (0x1400 + (port * 0x28))
+#define XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(port) (0x1408 + (port * 
0x28))
+#define XSTORM_DEF_SB_STATUS_BLOCK_SIZE 0x10
+#define XSTORM_DEF_SB_HC_TIMEOUT_OFFSET(port, index) \
+(0x1418 + (port * 0x28) + (index * 0x4))
+#define XSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index) \
+(0x141a + (port * 0x28) + (index * 0x4))
+#define XSTORM_HC_BTR_OFFSET(port) (0x1454 + (port * 0x18))
+#define XSTORM_ASSERT_LIST_OFFSET(idx) (0x1020 + (idx * 0x10))
+#define XSTORM_ASSERT_LIST_INDEX_OFFSET 0x1000
+#define TSTORM_INDIRECTION_TABLE_OFFSET(port) (0x22c8 + (port * 0x80))
+#define TSTORM_INDIRECTION_TABLE_SIZE 0x80
+#define TSTORM_INDIRECTION_TABLE_ENTRY_SIZE 0x1
+#define TSTORM_STATISTICS_OFFSET(port) (0x4000 + (port * 0x540))
+#define TSTORM_STATISTICS_SIZE 0x540
+#define TSTORM_COMMON_RTC_PARAMS_OFFSET 0x26c8
+#define TSTORM_COMMON_RTC_PARAMS_SIZE 0x8
+#define TSTORM_STATS_FLAGS_OFFSET(port) (0x4aa0 + (port * 0x8))
+#define TSTORM_STATS_FLAGS_SIZE 0x8
+#define TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port) (0x4a80 + (port * 0x8))
+#define TSTORM_ETH_STATS_QUERY_ADDR_SIZE 0x8
+#define TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port) (0x1400 + (port * 0x28))
+#define TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(port) (0x1408 + (port * 
0x28))
+#define TSTORM_DEF_SB_STATUS_BLOCK_SIZE 0x10
+#define TSTORM_DEF_SB_HC_TIMEOUT_OFFSET(port, index) \
+(0x1418 + (port * 0x28) + (index * 0x4))
+#define TSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index) \
+(0x141a + (port * 0x28) + (index * 0x4))
+#define TSTORM_HC_BTR_OFFSET(port) (0x1454 + (port * 0x18))
+#define TSTORM_ASSERT_LIST_OFFSET(idx) (0x1020 + (idx * 0x10))
+#define TSTORM_ASSERT_LIST_INDEX_OFFSET 0x1000
+#define CSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port) (0x1900 + (port * 0x40))
+#define CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(port) (0x1908 + (port * 
0x40))
+#define CSTORM_DEF_SB_STATUS_BLOCK_SIZE 0x18
+#define CSTORM_DEF_SB_HC_TIMEOUT_OFFSET(port, index) \
+(0x1920 + (port * 0x40) + (index * 0x4))
+#define CSTORM_DEF_SB_HC_DISABLE_OFFSET(port, index) \
+(0x1922 + (port * 0x40) + (index * 0x4))
+#define CSTORM_HC_BTR_OFFSET(port) (0x1984 + (port * 0xc0))
+#define CSTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
+(0x1400 + (port * 0x280) + (cpu_id * 0x28))
+#define CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
+(0x1408 + (port * 0x280) + (cpu_id * 0x28))
+#define CSTORM_SB_STATUS_BLOCK_SIZE 0x18
+#define CSTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
+(0x1418 + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4))
+#define CSTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
+(0x141a + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4))
+#define CSTORM_ASSERT_LIST_OFFSET(idx) (0x1020 + (idx * 0x10))
+#define CSTORM_ASSERT_LIST_INDEX_OFFSET 0x1000
+#define CSTORM_STATS_FLAGS_OFFSET(port) (0x5108 + (port * 0x8))
+#define CSTORM_STATS_FLAGS_SIZE 0x8
+#define CSTORM_ETH_STATS_QUERY_ADDR_OFFSET(port) (0x5118 + (port * 0x8))
+#define CSTORM_ETH_STATS_QUERY_ADDR_SIZE 0x8
+#define USTORM_INDIRECTION_TABLE_OFFSET(port) (0x5308 + (port * 0x80))
+#define USTORM_INDIRECTION_TABLE_SIZE 0x80
+#define USTORM_INDIRECTION_TABLE_ENTRY_SIZE 0x1
+#define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET 0x5408
+#define USTORM_MEM_WORKAROUND_ADDRESS_SIZE 0x8
+#define USTORM_DEF_SB_HOST_SB_ADDR_OFFSET(port) (0x1900 + (port * 0x28))
+#define USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(port) (0x1908 + (port * 
0x28))
+#define USTORM_DEF_SB_STATUS_BLOCK_SIZE 0x10
+#define USTORM_DEF_SB_HC_TIMEOUT_OFFSET(port, index) \
+(0x1918 + (port * 0x28) + (index * 0x4))
+#define USTORM_DEF_SB_HC_DISABLE_OFFSET(port, index) \
+(0x191a + (port * 0x28) + (index * 0x4))
+#define USTORM_HC_BTR_OFFSET(port) (0x1954 + (port * 0xb8))
+#define USTORM_SB_HOST_SB_ADDR_OFFSET(port, cpu_id) \
+(0x1400 + (port * 0x280) + (cpu_id * 0x28))
+#define USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, cpu_id) \
+(0x1408 + (port * 0x280) + (cpu_id * 0x28))
+#define USTORM_SB_STATUS_BLOCK_SIZE 0x10
+#define USTORM_SB_HC_TIMEOUT_OFFSET(port, cpu_id, index) \
+(0x1418 + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4))
+#define USTORM_SB_HC_DISABLE_OFFSET(port, cpu_id, index) \
+(0x141a + (port * 0x280) + (cpu_id * 0x28) + (index * 0x4))
+#define USTORM_ASSERT_LIST_OFFSET(idx) (0x1020 + (idx * 0x10))
+#define USTORM_ASSERT_LIST_INDEX_OFFSET 0x1000
+
+#endif
+#ifndef __FW_DEFS_H__
+#define __FW_DEFS_H__
+
+#define BCM_5710_FW_MAJOR_VERSION 4
+#define BCM_5710_FW_MINOR_VERSION 0
+#define BCM_5710_FW_REVISION_VERSION 7
+#define BCM_5710_FW_COMPILE_FLAGS 1
+
+#endif
+/****************************************************************************
+* Copyright(c) 2001-2006 Broadcom Corporation, all rights reserved
+* Proprietary and Confidential Information.
+*
+* Name: mcp_shmem.h
+*
+* Description: MCP Sheared memory map
+*
+* Created: 05/03/2006 eilong
+*
+* $Date: 2007/10/02 $ $Revision: #44 $
+****************************************************************************/
+
+#ifndef MCP_SHMEM_H
+#define MCP_SHMEM_H
+
+
+#define FUNC_0 0
+#define FUNC_1 1
+#define FUNC_MAX 2
+
+
+/* This value (in milliseconds) determines the frequency of the driver
+* issuing the PULSE message code. The firmware monitors this periodic
+* pulse to determine when to switch to an OS-absent mode. */
+#define DRV_PULSE_PERIOD_MS 250
+
+/* This value (in milliseconds) determines how long the driver should
+* wait for an acknowledgement from the firmware before timing out. Once
+* the firmware has timed out, the driver will assume there is no firmware
+* running and there won't be any firmware-driver synchronization during a
+* driver reset. */
+#define FW_ACK_TIME_OUT_MS 5000
+
+#define FW_ACK_POLL_TIME_MS 1
+
+#define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
+
+
+/****************************************************************************
+* Driver <-> FW Mailbox *
+****************************************************************************/
+struct drv_fw_mb_t
+{
+u32 drv_mb_header;
+#define DRV_MSG_CODE_MASK 0xffff0000
+#define DRV_MSG_CODE_LOAD_REQ 0x10000000
+#define DRV_MSG_CODE_LOAD_DONE 0x11000000
+#define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
+#define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
+#define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
+#define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
+#define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
+#define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
+#define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
+#define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
+#define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
+#define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
+#define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
+
+#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
+
+u32 drv_mb_param;
+
+u32 fw_mb_header;
+#define FW_MSG_CODE_MASK 0xffff0000
+#define FW_MSG_CODE_DRV_LOAD_COMMON 0x11000000
+#define FW_MSG_CODE_DRV_LOAD_PORT 0x12000000
+#define FW_MSG_CODE_DRV_LOAD_REFUSED 0x13000000
+#define FW_MSG_CODE_DRV_LOAD_DONE 0x14000000
+#define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x21000000
+#define FW_MSG_CODE_DRV_UNLOAD_PORT 0x22000000
+#define FW_MSG_CODE_DRV_UNLOAD_DONE 0x23000000
+#define FW_MSG_CODE_DIAG_ENTER_DONE 0x50000000
+#define FW_MSG_CODE_DIAG_REFUSE 0x51000000
+#define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70000000
+#define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x71000000
+#define FW_MSG_CODE_GET_KEY_DONE 0x80000000
+#define FW_MSG_CODE_NO_KEY 0x8f000000
+#define FW_MSG_CODE_LIC_INFO_NOT_READY 0x8f800000
+#define FW_MSG_CODE_L2B_PRAM_LOADED 0x90000000
+#define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x91000000
+#define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x92000000
+#define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x93000000
+#define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x94000000
+
+#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
+
+u32 fw_mb_param;
+
+u32 link_status;
+
+#define LINK_STATUS_LINK_FLAG_MASK 0x00000001
+#define LINK_STATUS_LINK_UP 0x00000001
+
+#define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
+#define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD (11<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD (11<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD (12<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD (12<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD (13<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD (13<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD (14<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD (14<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD (15<<1)
+#define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD (15<<1)
+
+#define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
+#define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
+
+#define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
+#define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
+#define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
+
+#define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
+#define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
+#define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
+#define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
+#define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
+#define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
+#define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
+
+#define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
+#define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
+
+#define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
+#define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
+
+#define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
+#define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
+#define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)
+#define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)
+#define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)
+
+#define LINK_STATUS_SERDES_LINK 0x00100000
+
+#define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
+#define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
+#define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
+#define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE 0x01000000
+#define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE 0x02000000
+#define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE 0x04000000
+#define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE 0x08000000
+#define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE 0x10000000
+
+u32 drv_pulse_mb;
+#define DRV_PULSE_SEQ_MASK 0x00007fff
+#define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
+/* The system time is in the format of
+* (year-2001)*12*32 + month*32 + day. */
+#define DRV_PULSE_ALWAYS_ALIVE 0x00008000
+/* Indicate to the firmware not to go into the
+* OS-absent when it is not getting driver pulse.
+* This is used for debugging as well for PXE(MBA). */
+
+u32 mcp_pulse_mb;
+#define MCP_PULSE_SEQ_MASK 0x00007fff
+#define MCP_PULSE_ALWAYS_ALIVE 0x00008000
+/* Indicates to the driver not to assert due to lack
+* of MCP response */
+#define MCP_EVENT_MASK 0xffff0000
+#define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
+
+} drv_fw_mb_t;
+
+
+/****************************************************************************
+* Shared HW configuration *
+****************************************************************************/
+struct shared_hw_cfg_t
+{
+u8 part_num[16];
+
+u32 config;
+#define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001
+#define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
+#define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000
+#define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001
+
+#define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002
+
+#define SHARED_HW_CFG_PORT_SWAP 0x00000004
+
+#define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008
+
+#define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700
+#define SHARED_HW_CFG_MFW_SELECT_SHIFT 8
+#define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000
+#define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100
+#define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200
+#define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300
+#define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400
+#define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500
+#define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600
+
+#define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000
+#define SHARED_HW_CFG_LED_MODE_SHIFT 16
+#define SHARED_HW_CFG_LED_MAC1 0x00000000
+#define SHARED_HW_CFG_LED_PHY1 0x00010000
+#define SHARED_HW_CFG_LED_PHY2 0x00020000
+#define SHARED_HW_CFG_LED_PHY3 0x00030000
+#define SHARED_HW_CFG_LED_MAC2 0x00040000
+#define SHARED_HW_CFG_LED_PHY4 0x00050000
+#define SHARED_HW_CFG_LED_PHY5 0x00060000
+#define SHARED_HW_CFG_LED_PHY6 0x00070000
+#define SHARED_HW_CFG_LED_MAC3 0x00080000
+#define SHARED_HW_CFG_LED_PHY7 0x00090000
+#define SHARED_HW_CFG_LED_PHY9 0x000a0000
+#define SHARED_HW_CFG_LED_PHY11 0x000b0000
+#define SHARED_HW_CFG_LED_MAC4 0x000c0000
+#define SHARED_HW_CFG_LED_PHY8 0x000d0000
+
+#define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000
+#define SHARED_HW_CFG_AN_ENABLE_SHIFT 24
+#define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000
+#define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000
+#define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000
+#define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000
+#define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
+#define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000
+
+u32 config2;
+
+#define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff
+#define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0
+
+#define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100
+
+/* The default value for the core clock is 250MHz and it is
+achieved by setting the clock change to 4 */
+#define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00
+#define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9
+
+#define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
+#define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
+
+u32 power_dissipated;
+#define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000
+#define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24
+
+#define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000
+#define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16
+#define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000
+#define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000
+#define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000
+#define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000
+
+u32 ump_nc_si_config;
+#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
+#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
+#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000
+#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001
+#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000
+#define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002
+
+#define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00
+#define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8
+
+#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000
+#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16
+#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000
+#define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
+
+u32 board;
+#define SHARED_HW_CFG_BOARD_TYPE_MASK 0x0000ffff
+#define SHARED_HW_CFG_BOARD_TYPE_SHIFT 0
+#define SHARED_HW_CFG_BOARD_TYPE_NONE 0x00000000
+#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1000 0x00000001
+#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1001 0x00000002
+#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1002G 0x00000003
+#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1004G 0x00000004
+#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1007G 0x00000005
+#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1015G 0x00000006
+#define SHARED_HW_CFG_BOARD_TYPE_BCM957710A1020G 0x00000007
+#define SHARED_HW_CFG_BOARD_TYPE_BCM957710T1003G 0x00000008
+
+#define SHARED_HW_CFG_BOARD_VER_MASK 0xffff0000
+#define SHARED_HW_CFG_BOARD_VER_SHIFT 16
+#define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0xf0000000
+#define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 28
+#define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0x0f000000
+#define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 24
+#define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000
+#define SHARED_HW_CFG_BOARD_REV_SHIFT 16
+
+u32 reserved;
+
+};
+
+/****************************************************************************
+* Port HW configuration *
+****************************************************************************/
+struct port_hw_cfg_t
+{
+
+u32 pci_id;
+#define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000
+#define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff
+
+u32 pci_sub_id;
+#define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000
+#define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff
+
+u32 power_dissipated;
+#define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000
+#define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24
+#define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000
+#define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16
+#define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00
+#define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8
+#define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff
+#define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
+
+u32 power_consumed;
+#define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000
+#define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24
+#define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000
+#define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16
+#define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00
+#define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8
+#define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff
+#define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
+
+u32 mac_upper;
+#define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff
+#define PORT_HW_CFG_UPPERMAC_SHIFT 0
+u32 mac_lower;
+
+u32 iscsi_mac_upper;
+u32 iscsi_mac_lower;
+
+u32 rdma_mac_upper;
+u32 rdma_mac_lower;
+
+u32 serdes_config;
+
+#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0xffff0000
+#define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 16
+
+#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0x0000ffff
+#define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 0
+
+u16 serdes_tx_driver_pre_emphasis[16];
+u16 serdes_rx_driver_equalizer[16];
+
+u32 xgxs_config_lane0;
+u32 xgxs_config_lane1;
+u32 xgxs_config_lane2;
+u32 xgxs_config_lane3;
+
+#define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_MASK 0xffff0000
+#define PORT_HW_CFG_XGXS_TX_DRV_PRE_EMPHASIS_SHIFT 16
+
+#define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_MASK 0x0000ffff
+#define PORT_HW_CFG_XGXS_RX_DRV_EQUALIZER_SHIFT 0
+
+u16 xgxs_tx_driver_pre_emphasis_lane0[16];
+u16 xgxs_tx_driver_pre_emphasis_lane1[16];
+u16 xgxs_tx_driver_pre_emphasis_lane2[16];
+u16 xgxs_tx_driver_pre_emphasis_lane3[16];
+
+u16 xgxs_rx_driver_equalizer_lane0[16];
+u16 xgxs_rx_driver_equalizer_lane1[16];
+u16 xgxs_rx_driver_equalizer_lane2[16];
+u16 xgxs_rx_driver_equalizer_lane3[16];
+
+u32 lane_config;
+#define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff
+#define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
+#define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff
+#define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
+#define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00
+#define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
+#define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000
+#define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14
+#define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b
+#define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4
+#define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
+#define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
+
+u32 external_phy_config;
+#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000
+#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24
+#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000
+#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000
+#define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000
+
+#define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000
+#define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16
+
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8276 0x00000600
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
+#define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
+
+#define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff
+#define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
+
+u32 speed_capability_mask;
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_12G 0x00800000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_12_5G 0x01000000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_13G 0x02000000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_15G 0x04000000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_16G 0x08000000
+#define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000
+
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_12G 0x00000080
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_12_5G 0x00000100
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_13G 0x00000200
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_15G 0x00000400
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_16G 0x00000800
+#define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000
+
+u32 reserved[2];
+
+};
+
+/****************************************************************************
+* Shared Feature configuration *
+****************************************************************************/
+struct shared_feat_cfg_t
+{
+u32 bmc_common;
+#define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
+
+};
+
+
+/****************************************************************************
+* Port Feature configuration *
+****************************************************************************/
+struct port_feat_cfg_t
+{
+u32 config;
+#define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f
+#define PORT_FEATURE_BAR1_SIZE_SHIFT 0
+#define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000
+#define PORT_FEATURE_BAR1_SIZE_64K 0x00000001
+#define PORT_FEATURE_BAR1_SIZE_128K 0x00000002
+#define PORT_FEATURE_BAR1_SIZE_256K 0x00000003
+#define PORT_FEATURE_BAR1_SIZE_512K 0x00000004
+#define PORT_FEATURE_BAR1_SIZE_1M 0x00000005
+#define PORT_FEATURE_BAR1_SIZE_2M 0x00000006
+#define PORT_FEATURE_BAR1_SIZE_4M 0x00000007
+#define PORT_FEATURE_BAR1_SIZE_8M 0x00000008
+#define PORT_FEATURE_BAR1_SIZE_16M 0x00000009
+#define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a
+#define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b
+#define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c
+#define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d
+#define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e
+#define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f
+#define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0
+#define PORT_FEATURE_BAR2_SIZE_SHIFT 4
+#define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000
+#define PORT_FEATURE_BAR2_SIZE_64K 0x00000010
+#define PORT_FEATURE_BAR2_SIZE_128K 0x00000020
+#define PORT_FEATURE_BAR2_SIZE_256K 0x00000030
+#define PORT_FEATURE_BAR2_SIZE_512K 0x00000040
+#define PORT_FEATURE_BAR2_SIZE_1M 0x00000050
+#define PORT_FEATURE_BAR2_SIZE_2M 0x00000060
+#define PORT_FEATURE_BAR2_SIZE_4M 0x00000070
+#define PORT_FEATURE_BAR2_SIZE_8M 0x00000080
+#define PORT_FEATURE_BAR2_SIZE_16M 0x00000090
+#define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0
+#define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0
+#define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0
+#define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0
+#define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0
+#define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0
+#define PORT_FEATURE_EN_SIZE_MASK 0x07000000
+#define PORT_FEATURE_EN_SIZE_SHIFT 24
+#define PORT_FEATURE_WOL_ENABLED 0x01000000
+#define PORT_FEATURE_MBA_ENABLED 0x02000000
+#define PORT_FEATURE_MFW_ENABLED 0x04000000
+
+u32 wol_config;
+
+#define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003
+#define PORT_FEATURE_WOL_DEFAULT_SHIFT 0
+#define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000
+#define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001
+#define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002
+#define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003
+#define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004
+#define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008
+#define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010
+
+u32 mba_config;
+#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000003
+#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
+#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000
+#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001
+#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002
+#define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003
+#define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100
+#define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200
+#define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400
+#define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000
+#define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000
+#define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000
+#define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000
+#define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20
+#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000
+#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24
+#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000
+#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000
+#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000
+#define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000
+#define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000
+#define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26
+#define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000
+#define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000
+#define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000
+#define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000
+#define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000
+#define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000
+#define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000
+#define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000
+#define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KX4 0x20000000
+#define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KR 0x24000000
+#define PORT_FEATURE_MBA_LINK_SPEED_12GBPS 0x28000000
+#define PORT_FEATURE_MBA_LINK_SPEED_12_5GBPS 0x2c000000
+#define PORT_FEATURE_MBA_LINK_SPEED_13GBPS 0x30000000
+#define PORT_FEATURE_MBA_LINK_SPEED_15GBPS 0x34000000
+#define PORT_FEATURE_MBA_LINK_SPEED_16GBPS 0x38000000
+
+u32 bmc_config;
+#define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000
+#define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001
+
+u32 mba_vlan_cfg;
+#define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff
+#define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
+#define PORT_FEATURE_MBA_VLAN_EN 0x00010000
+
+u32 resource_cfg;
+#define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001
+#define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002
+#define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004
+#define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008
+#define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010
+
+u32 smbus_config;
+#define PORT_FEATURE_SMBUS_EN 0x00000001
+#define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
+#define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
+
+u32 iscsib_boot_cfg;
+#define PORT_FEATURE_ISCSIB_SKIP_TARGET_BOOT 0x00000001
+
+u32 link_config;
+#define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
+#define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24
+#define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000
+#define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000
+#define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000
+#define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000
+
+#define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000
+#define PORT_FEATURE_LINK_SPEED_SHIFT 16
+#define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
+#define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000
+#define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000
+#define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
+#define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
+#define PORT_FEATURE_LINK_SPEED_1G 0x00050000
+#define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000
+#define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000
+#define PORT_FEATURE_LINK_SPEED_10G_KX4 0x00080000
+#define PORT_FEATURE_LINK_SPEED_10G_KR 0x00090000
+#define PORT_FEATURE_LINK_SPEED_12G 0x000a0000
+#define PORT_FEATURE_LINK_SPEED_12_5G 0x000b0000
+#define PORT_FEATURE_LINK_SPEED_13G 0x000c0000
+#define PORT_FEATURE_LINK_SPEED_15G 0x000d0000
+#define PORT_FEATURE_LINK_SPEED_16G 0x000e0000
+
+#define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700
+#define PORT_FEATURE_FLOW_CONTROL_SHIFT 8
+#define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000
+#define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100
+#define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200
+#define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300
+#define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400
+
+
+u32 mfw_wol_link_cfg;
+
+u32 reserved[19];
+
+};
+
+
+/****************************************************************************
+* Device Information *
+****************************************************************************/
+struct dev_info_t
+{
+u32 bc_rev;
+
+struct shared_hw_cfg_t shared_hw_config;
+
+struct port_hw_cfg_t port_hw_config[FUNC_MAX];
+
+struct shared_feat_cfg_t shared_feature_config;
+
+struct port_feat_cfg_t port_feature_config[FUNC_MAX];
+
+};
+
+
+/****************************************************************************
+* Management firmware state *
+****************************************************************************/
+/* Allocate 320 bytes for management firmware: still not known exactly
+* how much IMD needs. */
+#define MGMTFW_STATE_WORD_SIZE 80
+
+struct mgmtfw_state_t
+{
+u32 opaque[MGMTFW_STATE_WORD_SIZE];
+
+};
+
+
+/****************************************************************************
+* Shared Memory Region *
+****************************************************************************/
+struct shmem_region_t
+{
+u32 validity_map[FUNC_MAX];
+#define SHR_MEM_VALIDITY_PCI_CFG 0x00000001
+#define SHR_MEM_VALIDITY_MB 0x00000002
+#define SHR_MEM_VALIDITY_DEV_INFO 0x00000004
+
+#define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
+#define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
+#define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
+#define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
+
+struct drv_fw_mb_t drv_fw_mb[FUNC_MAX];
+
+struct dev_info_t dev_info;
+
+#ifdef _LICENSE_H
+license_key_t drv_lic_key[FUNC_MAX];
+#else
+u8 reserved[64*FUNC_MAX];
+#endif
+
+
+u32 fw_info_fio_offset;
+struct mgmtfw_state_t mgmtfw_state;
+
+};
+
+
+#endif
+
+#ifndef __ETH_CONSTANTS_H_
+#define __ETH_CONSTANTS_H_
+
+/**
+* This file defines HSI constatnts for the ETH flow
+*/
+#ifdef _EVEREST_MICROCODE
+#include "microcode_constants.h"
+#include "eth_rx_bd.h"
+#include "eth_tx_bd.h"
+#include "eth_rx_cqe.h"
+#include "eth_rx_cqe_next_page.h"
+#endif
+
+
+#define DEFAULT_HASH_TYPE 0
+#define IPV4_HASH_TYPE 1
+#define TCP_IPV4_HASH_TYPE 2
+#define IPV6_HASH_TYPE 3
+#define TCP_IPV6_HASH_TYPE 4
+
+
+#define X_ETH_LOCAL_RING_SIZE 13
+#define FIRST_BD_IN_PKT 0
+#define PARSE_BD_INDEX 1
+#define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE) / (STRUCT_SIZE(eth_tx_bd)/8))
+
+
+
+#define U_ETH_LOCAL_BD_RING_SIZE (8)
+
+#define U_ETH_BDS_PER_PAGE_MASK ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))-1)
+#define U_ETH_CQE_PER_PAGE_MASK ((PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))-1)
+#define TU_ETH_CQES_PER_PAGE 
(PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe_next_page)/8))
+#define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))
+
+
+
+#define RAMROD_CMD_ID_ETH_PORT_SETUP (80)
+#define RAMROD_CMD_ID_ETH_CLIENT_SETUP (85)
+#define RAMROD_CMD_ID_ETH_STAT_QUERY (90)
+#define RAMROD_CMD_ID_ETH_UPDATE (100)
+#define RAMROD_CMD_ID_ETH_HALT (105)
+#define RAMROD_CMD_ID_ETH_SET_MAC (110)
+#define RAMROD_CMD_ID_ETH_CFC_DEL (115)
+#define RAMROD_CMD_ID_ETH_PORT_DEL (120)
+#define RAMROD_CMD_ID_ETH_FORWARD_SETUP (125)
+
+
+
+#define T_ETH_MAC_COMMAND_SET 0
+#define T_ETH_MAC_COMMAND_INVALIDATE 1
+
+#define T_ETH_INDIRECTION_TABLE_SIZE 128
+
+
+#define ETH_MAX_RX_CLIENTS (18)
+
+#endif
+
+#ifndef __MICROCODE_CONSTANTS_H_
+#define __MICROCODE_CONSTANTS_H_
+
+/**
+* This file defines HSI constatnts common to all microcode flows
+*/
+
+
+#define ETH_CONNECTION_TYPE 0
+#define TOE_CONNECTION_TYPE 1
+#define RDMA_CONNECTION_TYPE 2
+#define ISCSI_CONNECTION_TYPE 3
+#define RESERVED_CONNECTION_TYPE_0 4
+#define RESERVED_CONNECTION_TYPE_1 5
+#define RESERVED_CONNECTION_TYPE_2 6
+#define RESERVED_CONNECTION_TYPE_3 7
+#define NUM_OF_CONNECTION_TYPES 8
+
+
+
+#define PROTOCOL_STATE_BIT_OFFSET 6
+
+
+#define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
+#define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
+#define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
+#define ISCSI_STATE (ISCSI_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
+
+
+#define MC_PAGE_SIZE (4096)
+
+
+
+
+
+#define IGU_PORT_BASE 0x0400
+
+#define IGU_ADDR_MSIX 0x0000
+#define IGU_ADDR_INT_ACK 0x0200
+#define IGU_ADDR_PROD_UPD 0x0201
+#define IGU_ADDR_ATTN_BITS_UPD 0x0202
+#define IGU_ADDR_ATTN_BITS_SET 0x0203
+#define IGU_ADDR_ATTN_BITS_CLR 0x0204
+#define IGU_ADDR_COALESCE_NOW 0x0205
+#define IGU_ADDR_SIMD_MASK 0x0206
+#define IGU_ADDR_SIMD_NOMASK 0x0207
+#define IGU_ADDR_MSI_CTL 0x0210
+#define IGU_ADDR_MSI_ADDR_LO 0x0211
+#define IGU_ADDR_MSI_ADDR_HI 0x0212
+#define IGU_ADDR_MSI_DATA 0x0213
+
+#define IGU_INT_ENABLE 0
+#define IGU_INT_DISABLE 1
+#define IGU_INT_NOP 2
+#define IGU_INT_NOP2 3
+
+
+#define HC_USTORM_DEF_SB_NUM_INDICES 4
+#define HC_CSTORM_DEF_SB_NUM_INDICES 8
+#define HC_XSTORM_DEF_SB_NUM_INDICES 4
+#define HC_TSTORM_DEF_SB_NUM_INDICES 4
+#define HC_USTORM_SB_NUM_INDICES 4
+#define HC_CSTORM_SB_NUM_INDICES 4
+
+
+
+
+#define HC_INDEX_U_TOE_RX_CQ_CONS 0
+#define HC_INDEX_U_ETH_RX_CQ_CONS 1
+
+
+#define HC_INDEX_C_TOE_TX_CQ_CONS 0
+#define HC_INDEX_C_ETH_TX_CQ_CONS 1
+#define HC_INDEX_C_ISCSI_EQ_CONS 2
+
+
+#define HC_INDEX_DEF_X_SPQ_CONS 0
+
+
+#define HC_INDEX_DEF_C_RDMA_EQ_CONS 0
+#define HC_INDEX_DEF_C_RDMA_NAL_PROD 1
+#define HC_INDEX_DEF_C_ETH_FW_TX_CQ_CONS 2
+#define HC_INDEX_DEF_C_ETH_SLOW_PATH 3
+#define HC_INDEX_DEF_C_ETH_RDMA_CQ_CONS 4
+#define HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS 5
+
+
+#define HC_INDEX_DEF_U_ETH_RDMA_RX_CQ_CONS 0
+#define HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS 1
+
+
+
+#define USTORM_ID 0
+#define CSTORM_ID 1
+#define XSTORM_ID 2
+#define TSTORM_ID 3
+#define ATTENTION_ID 4
+
+
+#define MAX_RAMRODS_PER_PORT (8)
+
+
+#define RX_ETH_CQE_TYPE_ETH_FASTPATH (0)
+#define RX_ETH_CQE_TYPE_ETH_RAMROD (1)
+
+
+
+#define T_MAC_ADDRESS_LIST_SIZE (96)
+
+
+
+#define EMULATION_FREQUENCY_FACTOR (1600)
+#define FPGA_FREQUENCY_FACTOR (100)
+
+
+#define TIMERS_TICK_SIZE_CHIP 1e-3
+#define TIMERS_TICK_SIZE_EMUL \
+((TIMERS_TICK_SIZE_CHIP)/((EMULATION_FREQUENCY_FACTOR)))
+#define TIMERS_TICK_SIZE_FPGA \
+((TIMERS_TICK_SIZE_CHIP)/((FPGA_FREQUENCY_FACTOR)))
+
+
+#define TSEMI_CLK1_RESUL_CHIP 1e-3
+#define TSEMI_CLK1_RESUL_EMUL \
+((TSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
+#define TSEMI_CLK1_RESUL_FPGA \
+((TSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
+
+
+#define USEMI_CLK1_RESUL_CHIP \
+(TIMERS_TICK_SIZE_CHIP)
+#define USEMI_CLK1_RESUL_EMUL \
+(TIMERS_TICK_SIZE_EMUL)
+#define USEMI_CLK1_RESUL_FPGA \
+(TIMERS_TICK_SIZE_FPGA)
+
+
+#define XSEMI_CLK1_RESUL_CHIP 1e-3
+#define XSEMI_CLK1_RESUL_EMUL \
+((XSEMI_CLK1_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
+#define XSEMI_CLK1_RESUL_FPGA \
+((XSEMI_CLK1_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
+
+
+#define XSEMI_CLK2_RESUL_CHIP 1e-6
+#define XSEMI_CLK2_RESUL_EMUL \
+((XSEMI_CLK2_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
+#define XSEMI_CLK2_RESUL_FPGA \
+((XSEMI_CLK2_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
+
+
+#define SDM_TIMER_TICK_RESUL_CHIP (4*(1e-6))
+#define SDM_TIMER_TICK_RESUL_EMUL \
+((SDM_TIMER_TICK_RESUL_CHIP)/(EMULATION_FREQUENCY_FACTOR))
+#define SDM_TIMER_TICK_RESUL_FPGA \
+((SDM_TIMER_TICK_RESUL_CHIP)/(FPGA_FREQUENCY_FACTOR))
+
+
+
+#define XSTORM_IP_ID_ROLL_HALF 0x8000
+#define XSTORM_IP_ID_ROLL_ALL 0
+
+
+#define FW_LOG_LIST_SIZE (50)
+
+#define NUM_OF_PROTOCOLS 4
+#define MAX_COS_NUMBER 16
+#define MAX_T_STAT_COUNTER_ID 18
+
+
+#define T_FAIR 1
+#define FAIR_MEM 2
+#define RS_PERIODIC_TIMEOUT_IN_SDM_TICS 25
+
+#define UNKNOWN_ADDRESS 0
+#define UNICAST_ADDRESS 1
+#define MULTICAST_ADDRESS 2
+#define BROADCAST_ADDRESS 3
+
+#endif
+#ifndef __GENERAL_ATTEN_BITS_H
+#define __GENERAL_ATTEN_BITS_H
+
+
+
+#define RESERVED_GENERAL_ATTENTION_BIT_0 0
+
+
+#define EVEREST_GEN_ATTN_IN_USE_MASK 0x3e0
+
+#define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000
+
+
+#define RESERVED_GENERAL_ATTENTION_BIT_6 6
+#define RESERVED_GENERAL_ATTENTION_BIT_7 7
+#define RESERVED_GENERAL_ATTENTION_BIT_8 8
+#define RESERVED_GENERAL_ATTENTION_BIT_9 9
+#define RESERVED_GENERAL_ATTENTION_BIT_10 10
+#define RESERVED_GENERAL_ATTENTION_BIT_11 11
+#define RESERVED_GENERAL_ATTENTION_BIT_12 12
+#define RESERVED_GENERAL_ATTENTION_BIT_13 13
+#define RESERVED_GENERAL_ATTENTION_BIT_14 14
+#define RESERVED_GENERAL_ATTENTION_BIT_15 15
+#define RESERVED_GENERAL_ATTENTION_BIT_16 16
+#define RESERVED_GENERAL_ATTENTION_BIT_17 17
+#define RESERVED_GENERAL_ATTENTION_BIT_18 18
+#define RESERVED_GENERAL_ATTENTION_BIT_19 19
+#define RESERVED_GENERAL_ATTENTION_BIT_20 20
+#define RESERVED_GENERAL_ATTENTION_BIT_21 21
+
+
+#define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7
+#define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8
+#define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9
+#define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10
+
+
+#define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11
+
+
+#define LATCHED_ATTN_RBCR 23
+#define LATCHED_ATTN_RBCT 24
+#define LATCHED_ATTN_RBCN 25
+#define LATCHED_ATTN_RBCU 26
+#define LATCHED_ATTN_RBCP 27
+#define LATCHED_ATTN_TIMEOUT_GRC 28
+#define LATCHED_ATTN_RSVD_GRC 29
+#define LATCHED_ATTN_ROM_PARITY_MCP 30
+#define LATCHED_ATTN_UM_RX_PARITY_MCP 31
+#define LATCHED_ATTN_UM_TX_PARITY_MCP 32
+#define LATCHED_ATTN_SCPAD_PARITY_MCP 33
+
+
+#define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32)
+#define GENERAL_ATTEN_OFFSET(atten_name) (1 << ((94 + atten_name) % 32 ))
+
+#endif
+#ifndef _GRC_ADDR_H
+#define _GRC_ADRR_H
+/*
+* This file defines GRC base address for every block.
+* This file is included by chipsim, asm microcode and cpp microcode.
+* These values are used in Design.xml on regBase attribute
+* Use the base with the generated offsets of specific registers.
+*/
+
+#define GRCBASE_PXPCS 0x000000
+#define GRCBASE_PCICONFIG 0x002000
+#define GRCBASE_PCIREG 0x002400
+#define GRCBASE_EMAC0 0x008000
+#define GRCBASE_EMAC1 0x008400
+#define GRCBASE_DBU 0x008800
+#define GRCBASE_MISC 0x00A000
+#define GRCBASE_DBG 0x00C000
+#define GRCBASE_NIG 0x010000
+#define GRCBASE_XCM 0x020000
+#define GRCBASE_PRS 0x040000
+#define GRCBASE_SRCH 0x040400
+#define GRCBASE_TSDM 0x042000
+#define GRCBASE_TCM 0x050000
+#define GRCBASE_BRB1 0x060000
+#define GRCBASE_MCP 0x080000
+#define GRCBASE_UPB 0x0C1000
+#define GRCBASE_CSDM 0x0C2000
+#define GRCBASE_USDM 0x0C4000
+#define GRCBASE_CCM 0x0D0000
+#define GRCBASE_UCM 0x0E0000
+#define GRCBASE_CDU 0x101000
+#define GRCBASE_DMAE 0x102000
+#define GRCBASE_PXP 0x103000
+#define GRCBASE_CFC 0x104000
+#define GRCBASE_HC 0x108000
+#define GRCBASE_PXP2 0x120000
+#define GRCBASE_PBF 0x140000
+#define GRCBASE_XPB 0x161000
+#define GRCBASE_TIMERS 0x164000
+#define GRCBASE_XSDM 0x166000
+#define GRCBASE_QM 0x168000
+#define GRCBASE_DQ 0x170000
+#define GRCBASE_TSEM 0x180000
+#define GRCBASE_CSEM 0x200000
+#define GRCBASE_XSEM 0x280000
+#define GRCBASE_USEM 0x300000
+#define GRCBASE_MISC_AEU GRCBASE_MISC
+
+#endif
+
+
+#define PCICFG_OFFSET 0x2000
+#define PCICFG_VENDOR_ID_OFFSET 0x00
+#define PCICFG_DEVICE_ID_OFFSET 0x02
+#define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c
+#define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e
+#define PCICFG_INT_LINE 0x3c
+#define PCICFG_INT_PIN 0x3d
+#define PCICFG_CACHE_LINE_SIZE 0x0c
+#define PCICFG_LATENCY_TIMER 0x0d
+#define PCICFG_REVESION_ID 0x08
+#define PCICFG_BAR_1_LOW 0x10
+#define PCICFG_BAR_1_HIGH 0x14
+#define PCICFG_BAR_2_LOW 0x18
+#define PCICFG_BAR_2_HIGH 0x1c
+#define PCICFG_GRC_ADDRESS 0x78
+#define PCICFG_GRC_DATA 0x80
+#define PCICFG_DEVICE_CONTROL 0xb4
+#define PCICFG_LINK_CONTROL 0xbc
+
+#define BAR_USTRORM_INTMEM 0x400000
+#define BAR_CSTRORM_INTMEM 0x410000
+#define BAR_XSTRORM_INTMEM 0x420000
+#define BAR_TSTRORM_INTMEM 0x430000
+
+
+#define BAR_IGU_INTMEM 0x440000
+
+#define BAR_DOORBELL_OFFSET 0x800000
+
+#define BAR_ME_REGISTER 0x450000
+
+
+#define GRC_CONFIG_2_SIZE_REG 0x408
+#define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
+#define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
+#define PCI_CONFIG_2_BAR1_64ENA (1L<<4)
+#define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
+#define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
+#define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
+#define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8)
+#define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8)
+#define PCI_CONFIG_2_BAR_PREFETCH (1L<<16)
+#define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17)
+
+#define GRC_CONFIG_3_SIZE_REG (0x40c)
+#define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
+#define PCI_CONFIG_3_FORCE_PME (1L<<24)
+#define PCI_CONFIG_3_PME_STATUS (1L<<25)
+#define PCI_CONFIG_3_PME_ENABLE (1L<<26)
+#define PCI_CONFIG_3_PM_STATE (0x3L<<27)
+#define PCI_CONFIG_3_VAUX_PRESET (1L<<30)
+#define PCI_CONFIG_3_PCI_POWER (1L<<31)
+
+#define GRC_CONFIG_2_SIZE_REG 0x408
+
+#define GRC_BAR2_CONFIG 0x4e0
+#define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0)
+#define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0)
+#define PCI_CONFIG_2_BAR2_64ENA (1L<<4)
+
+#define PCI_PM_DATA_A (0x410)
+#define PCI_PM_DATA_B (0x414)
+#define PCI_ID_VAL1 (0x434)
+#define PCI_ID_VAL2 (0x438)
+/****************************************************************************
+* Copyright(c) 2001-2006 Broadcom Corporation, all rights reserved
+* Proprietary and Confidential Information.
+*
+* This source file is the property of Broadcom Corporation, and
+* may not be copied or distributed in any isomorphic form without
+* the prior written consent of Broadcom Corporation.
+*
+* Name: phy_reg.h
+*
+* Description: This file contains partial list of the PHY registers.
+* It was manually created according to the excel data sheet
+* of the UNICORE (XGXS and SerDes). Only relevant registers
+* were added.
+* It is recommended to replace this file with automatically
+* generated version of the UNICORE registers
+*
+* Created: 01/14/2007 eilong
+*
+* $Date: 2007/07/23 $ $Revision: #14 $
+****************************************************************************/
+#ifndef PHY_REG_H
+#define PHY_REG_H
+
+#define MDIO_REG_BANK_CL73_IEEEB0 0x0
+#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
+#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
+#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
+#define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
+
+#define MDIO_REG_BANK_CL73_IEEEB1 0x10
+#define MDIO_CL73_IEEEB1_AN_ADV2 0x01
+#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
+#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
+#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
+#define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
+
+#define MDIO_REG_BANK_RX0 0x80b0
+#define MDIO_RX0_RX_EQ_BOOST 0x1c
+#define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
+#define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
+
+#define MDIO_REG_BANK_RX1 0x80c0
+#define MDIO_RX1_RX_EQ_BOOST 0x1c
+#define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
+#define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
+
+#define MDIO_REG_BANK_RX2 0x80d0
+#define MDIO_RX2_RX_EQ_BOOST 0x1c
+#define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
+#define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
+
+#define MDIO_REG_BANK_RX3 0x80e0
+#define MDIO_RX3_RX_EQ_BOOST 0x1c
+#define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
+#define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
+
+#define MDIO_REG_BANK_RX_ALL 0x80f0
+#define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
+#define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
+#define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
+
+#define MDIO_REG_BANK_TX0 0x8060
+#define MDIO_TX0_TX_DRIVER 0x17
+#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
+#define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
+#define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
+#define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
+#define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
+#define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
+#define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
+#define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
+#define MDIO_TX0_TX_DRIVER_ICBUF1T 1
+
+#define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
+#define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
+#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
+#define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
+#define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
+#define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
+#define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
+
+#define MDIO_REG_BANK_GP_STATUS 0x8120
+#define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
+
+
+
+
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
+#define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
+
+
+#define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
+#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
+#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
+#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
+#define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
+
+#define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
+#define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
+#define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
+#define MDIO_SERDES_DIGITAL_MISC1 0x18
+#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
+#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
+#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
+#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
+#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
+#define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
+#define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
+
+#define MDIO_REG_BANK_OVER_1G 0x8320
+#define MDIO_OVER_1G_DIGCTL_3_4 0x14
+#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
+#define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
+#define MDIO_OVER_1G_UP1 0x19
+#define MDIO_OVER_1G_UP1_2_5G 0x0001
+#define MDIO_OVER_1G_UP1_5G 0x0002
+#define MDIO_OVER_1G_UP1_6G 0x0004
+#define MDIO_OVER_1G_UP1_10G 0x0010
+#define MDIO_OVER_1G_UP1_10GH 0x0008
+
+
+#define MDIO_OVER_1G_UP1_12G 0x0020
+#define MDIO_OVER_1G_UP1_12_5G 0x0040
+#define MDIO_OVER_1G_UP1_13G 0x0080
+#define MDIO_OVER_1G_UP1_15G 0x0100
+#define MDIO_OVER_1G_UP1_16G 0x0200
+#define MDIO_OVER_1G_UP2 0x1A
+#define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
+#define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
+#define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
+#define MDIO_OVER_1G_UP3 0x1B
+#define MDIO_OVER_1G_UP3_HIGIG2 0x0001
+#define MDIO_OVER_1G_LP_UP1 0x1C
+#define MDIO_OVER_1G_LP_UP2 0x1D
+#define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
+#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
+#define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
+#define MDIO_OVER_1G_LP_UP3 0x1E
+
+#define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
+#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
+#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
+#define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
+
+#define MDIO_REG_BANK_CL73_USERB0 0x8370
+#define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
+#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
+#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
+#define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
+#define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
+#define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
+
+#define MDIO_REG_BANK_AER_BLOCK 0xFFD0
+#define MDIO_AER_BLOCK_AER_REG 0x1E
+
+#define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
+#define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
+#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
+#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
+#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
+#define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
+#define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
+#define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
+#define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
+#define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
+#define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
+#define MDIO_COMBO_IEEE0_MII_STATUS 0x11
+#define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
+#define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
+#define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_SYMMETRIC 
0x0080
+#define 
MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_ASYMMETRIC 0x0100
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
+
+
+
+#define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
+
+
+
+#define EXT_PHY_OPT_PMA_PMD_DEVAD 0x1
+#define EXT_PHY_OPT_WIS_DEVAD 0x2
+#define EXT_PHY_OPT_PCS_DEVAD 0x3
+#define EXT_PHY_OPT_PHY_XS_DEVAD 0x4
+#define EXT_PHY_OPT_CNTL 0x0
+#define EXT_PHY_OPT_PMD_RX_SD 0xa
+#define EXT_PHY_OPT_PMD_MISC_CNTL 0xca0a
+#define EXT_PHY_OPT_PHY_IDENTIFIER 0xc800
+#define EXT_PHY_OPT_PMD_DIGITAL_CNT 0xc808
+#define EXT_PHY_OPT_PMD_DIGITAL_SATUS 0xc809
+#define EXT_PHY_OPT_CMU_PLL_BYPASS 0xca09
+#define EXT_PHY_OPT_LASI_CNTL 0x9002
+#define EXT_PHY_OPT_RX_ALARM 0x9003
+#define EXT_PHY_OPT_LASI_STATUS 0x9005
+#define EXT_PHY_OPT_PCS_STATUS 0x0020
+#define EXT_PHY_OPT_XGXS_LANE_STATUS 0x0018
+
+#endif
+#ifndef __5710_HSI_L2_LE__
+#define __5710_HSI_L2_LE__
+#pragma pack(push, 1)
+/*
+* attention bits
+*/
+struct atten_def_status_block {
+u32 attn_bits;
+u32 attn_bits_ack;
+#if defined(__BIG_ENDIAN)
+u16 attn_bits_index;
+u8 reserved0;
+u8 status_block_id;
+#elif defined(__LITTLE_ENDIAN)
+u8 status_block_id;
+u8 reserved0;
+u16 attn_bits_index;
+#endif
+u32 reserved1;
+};
+
+
+/*
+* common data for all protocols
+*/
+struct doorbell_hdr {
+u8 header;
+#define DOORBELL_HDR_RX (0x1<<0)
+#define DOORBELL_HDR_RX_SHIFT 0
+#define DOORBELL_HDR_DB_TYPE (0x1<<1)
+#define DOORBELL_HDR_DB_TYPE_SHIFT 1
+#define DOORBELL_HDR_DPM_SIZE (0x3<<2)
+#define DOORBELL_HDR_DPM_SIZE_SHIFT 2
+#define DOORBELL_HDR_CONN_TYPE (0xF<<4)
+#define DOORBELL_HDR_CONN_TYPE_SHIFT 4
+};
+
+/*
+* doorbell message send to the chip
+*/
+struct doorbell {
+#if defined(__BIG_ENDIAN)
+u16 zero_fill2;
+u8 zero_fill1;
+struct doorbell_hdr header;
+#elif defined(__LITTLE_ENDIAN)
+struct doorbell_hdr header;
+u8 zero_fill1;
+u16 zero_fill2;
+#endif
+};
+
+
+
+/*
+* IGU driver acknowlegement register
+*/
+struct igu_ack_register {
+#if defined(__BIG_ENDIAN)
+u16 sb_id_and_flags;
+#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
+#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
+#define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
+#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
+#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
+#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
+#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
+#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
+#define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
+#define IGU_ACK_REGISTER_RESERVED_SHIFT 11
+u16 status_block_index;
+#elif defined(__LITTLE_ENDIAN)
+u16 status_block_index;
+u16 sb_id_and_flags;
+#define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
+#define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
+#define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
+#define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
+#define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
+#define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
+#define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
+#define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
+#define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
+#define IGU_ACK_REGISTER_RESERVED_SHIFT 11
+#endif
+};
+
+
+/*
+* Parser parsing flags field
+*/
+struct parsing_flags {
+u16 flags;
+#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
+#define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
+#define PARSING_FLAGS_NUMBER_OF_NESTED_VLANS (0x3<<1)
+#define PARSING_FLAGS_NUMBER_OF_NESTED_VLANS_SHIFT 1
+#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
+#define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
+#define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
+#define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
+#define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
+#define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
+#define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
+#define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
+#define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
+#define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
+#define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
+#define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
+#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
+#define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
+#define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
+#define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
+#define PARSING_FLAGS_LLC_SNAP (0x1<<13)
+#define PARSING_FLAGS_LLC_SNAP_SHIFT 13
+#define PARSING_FLAGS_RESERVED0 (0x3<<14)
+#define PARSING_FLAGS_RESERVED0_SHIFT 14
+};
+
+
+/*
+* dmae command structure
+*/
+struct dmae_command {
+u32 opcode;
+#define DMAE_COMMAND_SRC (0x1<<0)
+#define DMAE_COMMAND_SRC_SHIFT 0
+#define DMAE_COMMAND_DST (0x3<<1)
+#define DMAE_COMMAND_DST_SHIFT 1
+#define DMAE_COMMAND_C_DST (0x1<<3)
+#define DMAE_COMMAND_C_DST_SHIFT 3
+#define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
+#define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
+#define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
+#define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
+#define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
+#define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
+#define DMAE_COMMAND_ENDIANITY (0x3<<9)
+#define DMAE_COMMAND_ENDIANITY_SHIFT 9
+#define DMAE_COMMAND_PORT (0x1<<11)
+#define DMAE_COMMAND_PORT_SHIFT 11
+#define DMAE_COMMAND_CRC_RESET (0x1<<12)
+#define DMAE_COMMAND_CRC_RESET_SHIFT 12
+#define DMAE_COMMAND_SRC_RESET (0x1<<13)
+#define DMAE_COMMAND_SRC_RESET_SHIFT 13
+#define DMAE_COMMAND_DST_RESET (0x1<<14)
+#define DMAE_COMMAND_DST_RESET_SHIFT 14
+#define DMAE_COMMAND_RESERVED0 (0x1FFFF<<15)
+#define DMAE_COMMAND_RESERVED0_SHIFT 15
+u32 src_addr_lo;
+u32 src_addr_hi;
+u32 dst_addr_lo;
+u32 dst_addr_hi;
+#if defined(__BIG_ENDIAN)
+u16 reserved1;
+u16 len;
+#elif defined(__LITTLE_ENDIAN)
+u16 len;
+u16 reserved1;
+#endif
+u32 comp_addr_lo;
+u32 comp_addr_hi;
+u32 comp_val;
+u32 crc32;
+u32 crc32_c;
+#if defined(__BIG_ENDIAN)
+u16 crc16_c;
+u16 crc16;
+#elif defined(__LITTLE_ENDIAN)
+u16 crc16;
+u16 crc16_c;
+#endif
+#if defined(__BIG_ENDIAN)
+u16 reserved2;
+u16 crc_t10;
+#elif defined(__LITTLE_ENDIAN)
+u16 crc_t10;
+u16 reserved2;
+#endif
+#if defined(__BIG_ENDIAN)
+u16 xsum8;
+u16 xsum16;
+#elif defined(__LITTLE_ENDIAN)
+u16 xsum16;
+u16 xsum8;
+#endif
+};
+
+
+struct double_regpair {
+u32 regpair0_lo;
+u32 regpair0_hi;
+u32 regpair1_lo;
+u32 regpair1_hi;
+};
+
+
+/*
+* The eth Rx Buffer Descriptor
+*/
+struct eth_rx_bd {
+u32 addr_lo;
+u32 addr_hi;
+u32 len;
+u32 reserved;
+};
+
+/*
+* The eth storm context of Ustorm
+*/
+struct ustorm_eth_st_context {
+#if defined(__BIG_ENDIAN)
+u8 sb_index_number;
+u8 status_block_id;
+u8 __local_rx_bd_cons;
+u8 __local_rx_bd_prod;
+#elif defined(__LITTLE_ENDIAN)
+u8 __local_rx_bd_prod;
+u8 __local_rx_bd_cons;
+u8 status_block_id;
+u8 sb_index_number;
+#endif
+#if defined(__BIG_ENDIAN)
+u16 rcq_cons;
+u16 rx_bd_cons;
+#elif defined(__LITTLE_ENDIAN)
+u16 rx_bd_cons;
+u16 rcq_cons;
+#endif
+u32 rx_bd_page_base_lo;
+u32 rx_bd_page_base_hi;
+u32 rcq_base_address_lo;
+u32 rcq_base_address_hi;
+#if defined(__BIG_ENDIAN)
+u8 __reserved1;
+u8 __current_dynamic_hc_timeout;
+u16 flags;
+#define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT (0x1<<0)
+#define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT_SHIFT 0
+#define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC (0x1<<1)
+#define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC_SHIFT 1
+#define __USTORM_ETH_ST_CONTEXT_RESERVED0 (0x3FFF<<2)
+#define __USTORM_ETH_ST_CONTEXT_RESERVED0_SHIFT 2
+#elif defined(__LITTLE_ENDIAN)
+u16 flags;
+#define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT (0x1<<0)
+#define USTORM_ETH_ST_CONTEXT_ENABLE_MC_ALIGNMENT_SHIFT 0
+#define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC (0x1<<1)
+#define USTORM_ETH_ST_CONTEXT_ENABLE_DYNAMIC_HC_SHIFT 1
+#define __USTORM_ETH_ST_CONTEXT_RESERVED0 (0x3FFF<<2)
+#define __USTORM_ETH_ST_CONTEXT_RESERVED0_SHIFT 2
+u8 __current_dynamic_hc_timeout;
+u8 __reserved1;
+#endif
+u32 mc_alignment_size;
+struct eth_rx_bd __local_bd_ring[8];
+};
+
+/*
+* The eth storm context of Tstorm
+*/
+struct tstorm_eth_st_context {
+u32 __reserved0[28];
+};
+
+/*
+* The eth aggregative context section of Xstorm
+*/
+struct xstorm_eth_extra_ag_context_section {
+#if defined(__BIG_ENDIAN)
+u8 __tcp_agg_vars1;
+u8 __reserved50;
+u16 __mss;
+#elif defined(__LITTLE_ENDIAN)
+u16 __mss;
+u8 __reserved50;
+u8 __tcp_agg_vars1;
+#endif
+u32 __snd_nxt;
+u32 __tx_wnd;
+u32 __snd_una;
+u32 __reserved53;
+#if defined(__BIG_ENDIAN)
+u8 __agg_val8_th;
+u8 __agg_val8;
+u16 __tcp_agg_vars2;
+#elif defined(__LITTLE_ENDIAN)
+u16 __tcp_agg_vars2;
+u8 __agg_val8;
+u8 __agg_val8_th;
+#endif
+u32 __reserved58;
+u32 __reserved59;
+u32 __reserved60;
+u32 __reserved61;
+#if defined(__BIG_ENDIAN)
+u16 __agg_val7_th;
+u16 __agg_val7;
+#elif defined(__LITTLE_ENDIAN)
+u16 __agg_val7;
+u16 __agg_val7_th;
+#endif
+#if defined(__BIG_ENDIAN)
+u8 __tcp_agg_vars4;
+u16 __tcp_agg_vars3;
+u8 __reserved62;
+#elif defined(__LITTLE_ENDIAN)
+u8 __reserved62;
+u16 __tcp_agg_vars3;
+u8 __tcp_agg_vars4;
+#endif
+u32 __tcp_agg_vars5;
+#if defined(__BIG_ENDIAN)
+u16 __agg_misc6;
+u16 __tcp_agg_vars6;
+#elif defined(__LITTLE_ENDIAN)
+u16 __tcp_agg_vars6;
+u16 __agg_misc6;
+#endif
+u32 __agg_val10;
+u32 __agg_val10_th;
+#if defined(__BIG_ENDIAN)
+u16 __reserved3;
+u8 __reserved2;
+u8 __agg_misc7;
+#elif defined(__LITTLE_ENDIAN)
+u8 __agg_misc7;
+u8 __reserved2;
+u16 __reserved3;
+#endif
+};
+
+/*
+* The eth aggregative context of Xstorm
+*/
+struct xstorm_eth_ag_context {
+#if defined(__BIG_ENDIAN)
+u16 __bd_prod;
+u8 __agg_vars1;
+u8 __state;
+#elif defined(__LITTLE_ENDIAN)
+u8 __state;
+u8 __agg_vars1;
+u16 __bd_prod;
+#endif
+#if defined(__BIG_ENDIAN)
+u8 cdu_reserved;
+u16 __agg_vars3;
+u8 __agg_vars2;
+#elif defined(__LITTLE_ENDIAN)
+u8 __agg_vars2;
+u16 __agg_vars3;
+u8 cdu_reserved;
+#endif
+u32 __more_packets_to_send;
+#if defined(__BIG_ENDIAN)
+u16 __agg_vars4;
+u16 __agg_val4_th;
+#elif defined(__LITTLE_ENDIAN)
+u16 __agg_val4_th;
+u16 __agg_vars4;
+#endif
+struct xstorm_eth_extra_ag_context_section __extra_section;
+#if defined(__BIG_ENDIAN)
+u16 __agg_vars7;
+u8 __agg_val3_th;
+u8 __agg_vars6;
+#elif defined(__LITTLE_ENDIAN)
+u8 __agg_vars6;
+u8 __agg_val3_th;
+u16 __agg_vars7;
+#endif
+#if defined(__BIG_ENDIAN)
+u16 __agg_val11_th;
+u16 __agg_val11;
+#elif defined(__LITTLE_ENDIAN)
+u16 __agg_val11;
+u16 __agg_val11_th;
+#endif
+#if defined(__BIG_ENDIAN)
+u8 __reserved1;
+u8 __agg_val6_th;
+u16 __agg_val9;
+#elif defined(__LITTLE_ENDIAN)
+u16 __agg_val9;
+u8 __agg_val6_th;
+u8 __reserved1;
+#endif
+#if defined(__BIG_ENDIAN)
+u16 __agg_val2_th;
+u16 __agg_val2;
+#elif defined(__LITTLE_ENDIAN)
+u16 __agg_val2;
+u16 __agg_val2_th;
+#endif
+u32 __agg_vars5;
+#if defined(__BIG_ENDIAN)
+u16 __agg_misc0;
+u16 __agg_val4;
+#elif defined(__LITTLE_ENDIAN)
+u16 __agg_val4;
+u16 __agg_misc0;
+#endif
+#if defined(__BIG_ENDIAN)
+u8 __agg_val3;
+u8 __agg_val6;
+u8 __agg_val5_th;
+u8 __agg_val5;
+#elif defined(__LITTLE_ENDIAN)
+u8 __agg_val5;
+u8 __agg_val5_th;
+u8 __agg_val6;
+u8 __agg_val3;
+#endif
+#if defined(__BIG_ENDIAN)
+u16 __agg_misc1;
+u16 __bd_ind_max_val;
+#elif defined(__LITTLE_ENDIAN)
+u16 __bd_ind_max_val;
+u16 __agg_misc1;
+#endif
+u32 __reserved57;
+u32 __agg_misc4;
+u32 __agg_misc5;
+};
+
+/*
+* The eth aggregative context section of Tstorm
+*/
+struct tstorm_eth_extra_ag_context_section {
+u32 __agg_val1;
+#if defined(__BIG_ENDIAN)
+u8 __tcp_agg_vars2;
+u8 __agg_val3;
+u16 __agg_val2;
+#elif defined(__LITTLE_ENDIAN)
+u16 __agg_val2;
+u8 __agg_val3;
+u8 __tcp_agg_vars2;
+#endif
+#if defined(__BIG_ENDIAN)
+u16 __agg_val5;
+u8 __agg_val6;
+u8 __tcp_agg_vars3;
+#elif defined(__LITTLE_ENDIAN)
+u8 __tcp_agg_vars3;
+u8 __agg_val6;
+u16 __agg_val5;
+#endif
+u32 __reserved63;
+u32 __reserved64;
+u32 __reserved65;
+u32 __reserved66;
+u32 __reserved67;
+u32 __tcp_agg_vars1;
+u32 __reserved61;
+u32 __reserved62;
+u32 __reserved2;
+};
+
+/*
+* The eth aggregative context of Tstorm
+*/
+struct tstorm_eth_ag_context {
+#if defined(__BIG_ENDIAN)
+u16 __reserved54;
+u8 agg_vars1;
+#define __TSTORM_ETH_AG_CONTEXT_RESERVED50 (0x1<<0)
+#define __TSTORM_ETH_AG_CONTEXT_RESERVED50_SHIFT 0
+#define __TSTORM_ETH_AG_CONTEXT_RESERVED51 (0x1<<1)
+#define __TSTORM_ETH_AG_CONTEXT_RESERVED51_SHIFT 1
+#define __TSTORM_ETH_AG_CONTEXT_RESERVED52 (0x1<<2)
+#define __TSTORM_ETH_AG_CONTEXT_RESERVED52_SHIFT 2
+#define __TSTORM_ETH_AG_CONTEXT_RESERVED53 (0x1<<3)
+#define __TSTORM_ETH_AG_CONTEXT_RESERVED53_SHIFT 3
+#define TSTORM_ETH_AG_CONTEXT_AUX3_CF (0x3<<4)
+#define TSTORM_ETH_AG_CONTEXT_AUX3_CF_SHIFT 4
+#define __TSTORM_ETH_AG_CONTEXT_AUX3_FLAG (0x1<<6)
+#define __TSTORM_ETH_AG_CONTEXT_AUX3_FLAG_SHIFT 6
+#define __TSTORM_ETH_AG_CONTEXT_AUX4_FLAG (0x1<<7)
+#define __TSTORM_ETH_AG_CONTEXT_AUX4_FLAG_SHIFT 7
+u8 __state;
+#elif defined(__LITTLE_ENDIAN)
+u8 __state;
+u8 agg_vars1;
+#define __TSTORM_ETH_AG_CONTEXT_RESERVED50 (0x1<<0)
+#define __TSTORM_ETH_AG_CONTEXT_RESERVED50_SHIFT 0
+#define __TSTORM_ETH_AG_CONTEXT_RESERVED51 (0x1<<1)
+#define __TSTORM_ETH_AG_CONTEXT_RESERVED51_SHIFT 1
+#define __TSTORM_ETH_AG_CONTEXT_RESERVED52 (0x1<<2)
+#define __TSTORM_ETH_AG_CONTEXT_RESERVED52_SHIFT 2
+#define __TSTORM_ETH_AG_CONTEXT_RESERVED53 (0x1<<3)
+#define __TSTORM_ETH_AG_CONTEXT_RESERVED53_SHIFT 3
+#define TSTORM_ETH_AG_CONTEXT_AUX3_CF (0x3<<4)
+#define TSTORM_ETH_AG_CONTEXT_AUX3_CF_SHIFT 4
+#define __TSTORM_ETH_AG_CONTEXT_AUX3_FLAG (0x1<<6)
+#define __TSTORM_ETH_AG_CONTEXT_AUX3_FLAG_SHIFT 6
+#define __TSTORM_ETH_AG_CONTEXT_AUX4_FLAG (0x1<<7)
+#define __TSTORM_ETH_AG_CONTEXT_AUX4_FLAG_SHIFT 7
+u16 __reserved54;
+#endif
+#if defined(__BIG_ENDIAN)
+u16 __agg_val4;
+u16 __agg_vars2;
+#elif defined(__LITTLE_ENDIAN)
+u16 __agg_vars2;
+u16 __agg_val4;
+#endif
+struct tstorm_eth_extra_ag_context_section __extra_section;
+};
+
+/*
+* The eth aggregative context of Cstorm
+*/
+struct cstorm_eth_ag_context {
+u32 __agg_vars1;
+#if defined(__BIG_ENDIAN)
+u8 __aux1_th;
+u8 __aux1_val;
+u16 __agg_vars2;
+#elif defined(__LITTLE_ENDIAN)
+u16 __agg_vars2;
+u8 __aux1_val;
+u8 __aux1_th;
+#endif
+u32 __num_of_treated_packet;
+u32 __last_packet_treated;
+#if defined(__BIG_ENDIAN)
+u16 __reserved58;
+u16 __reserved57;
+#elif defined(__LITTLE_ENDIAN)
+u16 __reserved57;
+u16 __reserved58;
+#endif
+#if defined(__BIG_ENDIAN)
+u8 __reserved62;
+u8 __reserved61;
+u8 __reserved60;
+u8 __reserved59;
+#elif defined(__LITTLE_ENDIAN)
+u8 __reserved59;
+u8 __reserved60;
+u8 __reserved61;
+u8 __reserved62;
+#endif
+#if defined(__BIG_ENDIAN)
+u16 __reserved64;
+u16 __reserved63;
+#elif defined(__LITTLE_ENDIAN)
+u16 __reserved63;
+u16 __reserved64;
+#endif
+u32 __reserved65;
+#if defined(__BIG_ENDIAN)
+u16 __agg_vars3;
+u16 __rq_inv_cnt;
+#elif defined(__LITTLE_ENDIAN)
+u16 __rq_inv_cnt;
+u16 __agg_vars3;
+#endif
+#if defined(__BIG_ENDIAN)
+u16 __packet_index_th;
+u16 __packet_index;
+#elif defined(__LITTLE_ENDIAN)
+u16 __packet_index;
+u16 __packet_index_th;
+#endif
+};
+
+/*
+* The eth aggregative context of Ustorm
+*/
+struct ustorm_eth_ag_context {
+#if defined(__BIG_ENDIAN)
+u8 __aux_counter_flags;
+u16 __agg_vars;
+u8 __state;
+#elif defined(__LITTLE_ENDIAN)
+u8 __state;
+u16 __agg_vars;
+u8 __aux_counter_flags;
+#endif
+#if defined(__BIG_ENDIAN)
+u8 cdu_usage;
+u8 __agg_misc2;
+u16 __agg_misc1;
+#elif defined(__LITTLE_ENDIAN)
+u16 __agg_misc1;
+u8 __agg_misc2;
+u8 cdu_usage;
+#endif
+u32 __agg_misc4;
+#if defined(__BIG_ENDIAN)
+u8 __agg_val3_th;
+u8 __agg_val3;
+u16 __agg_misc3;
+#elif defined(__LITTLE_ENDIAN)
+u16 __agg_misc3;
+u8 __agg_val3;
+u8 __agg_val3_th;
+#endif
+u32 __agg_val1;
+u32 __agg_misc4_th;
+#if defined(__BIG_ENDIAN)
+u16 __agg_val2_th;
+u16 __agg_val2;
+#elif defined(__LITTLE_ENDIAN)
+u16 __agg_val2;
+u16 __agg_val2_th;
+#endif
+#if defined(__BIG_ENDIAN)
+u16 __reserved2;
+u8 __decision_rules;
+u8 __decision_rule_enable_bits;
+#elif defined(__LITTLE_ENDIAN)
+u8 __decision_rule_enable_bits;
+u8 __decision_rules;
+u16 __reserved2;
+#endif
+};
+
+/*
+* Timers connection context
+*/
+struct timers_block_context {
+u32 __reserved_0;
+u32 __reserved_1;
+u32 __reserved_2;
+u32 reserved_flags;
+#define __TIMERS_BLOCK_CONTEXT_RESERVED_FLAG_0 (0x3<<0)
+#define __TIMERS_BLOCK_CONTEXT_RESERVED_FLAG_0_SHIFT 0
+#define TIMERS_BLOCK_CONTEXT_RESERVED_FLAG_1 (0x1<<2)
+#define TIMERS_BLOCK_CONTEXT_RESERVED_FLAG_1_SHIFT 2
+#define __TIMERS_BLOCK_CONTEXT_RESERVED_FLAG_2 (0x1FFFFFFF<<3)
+#define __TIMERS_BLOCK_CONTEXT_RESERVED_FLAG_2_SHIFT 3
+};
+
+/*
+* structure for easy accessability to assembler
+*/
+struct eth_tx_bd_flags {
+u8 as_bitfield;
+#define ETH_TX_BD_FLAGS_VLAN_TAG (0x1<<0)
+#define ETH_TX_BD_FLAGS_VLAN_TAG_SHIFT 0
+#define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<1)
+#define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 1
+#define ETH_TX_BD_FLAGS_TCP_CSUM (0x1<<2)
+#define ETH_TX_BD_FLAGS_TCP_CSUM_SHIFT 2
+#define ETH_TX_BD_FLAGS_END_BD (0x1<<3)
+#define ETH_TX_BD_FLAGS_END_BD_SHIFT 3
+#define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
+#define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
+#define ETH_TX_BD_FLAGS_HDR_POOL (0x1<<5)
+#define ETH_TX_BD_FLAGS_HDR_POOL_SHIFT 5
+#define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
+#define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
+#define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
+#define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
+};
+
+/*
+* The eth Tx Buffer Descriptor
+*/
+struct eth_tx_bd {
+u32 addr_lo;
+u32 addr_hi;
+#if defined(__BIG_ENDIAN)
+u16 nbytes;
+u16 nbd;
+#elif defined(__LITTLE_ENDIAN)
+u16 nbd;
+u16 nbytes;
+#endif
+#if defined(__BIG_ENDIAN)
+u8 general_data;
+#define ETH_TX_BD_HDR_NBDS (0x3F<<0)
+#define ETH_TX_BD_HDR_NBDS_SHIFT 0
+#define ETH_TX_BD_ETH_ADDR_TYPE (0x3<<6)
+#define ETH_TX_BD_ETH_ADDR_TYPE_SHIFT 6
+struct eth_tx_bd_flags bd_flags;
+u16 vlan;
+#elif defined(__LITTLE_ENDIAN)
+u16 vlan;
+struct eth_tx_bd_flags bd_flags;
+u8 general_data;
+#define ETH_TX_BD_HDR_NBDS (0x3F<<0)
+#define ETH_TX_BD_HDR_NBDS_SHIFT 0
+#define ETH_TX_BD_ETH_ADDR_TYPE (0x3<<6)
+#define ETH_TX_BD_ETH_ADDR_TYPE_SHIFT 6
+#endif
+};
+
+/*
+* Tx parsing BD structure for ETH, Relevant in START
+*/
+struct eth_tx_parse_bd {
+#if defined(__BIG_ENDIAN)
+u16 total_hlen;
+u8 ip_hlen;
+s8 cs_offset;
+u8 tcp_flags;
+#define ETH_TX_PARSE_BD_FIN_FLG (0x1<<0)
+#define ETH_TX_PARSE_BD_FIN_FLG_SHIFT 0
+#define ETH_TX_PARSE_BD_SYN_FLG (0x1<<1)
+#define ETH_TX_PARSE_BD_SYN_FLG_SHIFT 1
+#define ETH_TX_PARSE_BD_RST_FLG (0x1<<2)
+#define ETH_TX_PARSE_BD_RST_FLG_SHIFT 2
+#define ETH_TX_PARSE_BD_PSH_FLG (0x1<<3)
+#define ETH_TX_PARSE_BD_PSH_FLG_SHIFT 3
+#define ETH_TX_PARSE_BD_ACK_FLG (0x1<<4)
+#define ETH_TX_PARSE_BD_ACK_FLG_SHIFT 4
+#define ETH_TX_PARSE_BD_URG_FLG (0x1<<5)
+#define ETH_TX_PARSE_BD_URG_FLG_SHIFT 5
+#define ETH_TX_PARSE_BD_ECE_FLG (0x1<<6)
+#define ETH_TX_PARSE_BD_ECE_FLG_SHIFT 6
+#define ETH_TX_PARSE_BD_CWR_FLG (0x1<<7)
+#define ETH_TX_PARSE_BD_CWR_FLG_SHIFT 7
+u8 global_data;
+#define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET (0xF<<0)
+#define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET_SHIFT 0
+#define ETH_TX_PARSE_BD_CS_ANY_FLG (0x1<<4)
+#define ETH_TX_PARSE_BD_CS_ANY_FLG_SHIFT 4
+#define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
+#define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
+#define ETH_TX_PARSE_BD_LLC_SNAP_EN (0x1<<6)
+#define ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT 6
+#define ETH_TX_PARSE_BD_NS_FLG (0x1<<7)
+#define ETH_TX_PARSE_BD_NS_FLG_SHIFT 7
+#elif defined(__LITTLE_ENDIAN)
+u8 global_data;
+#define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET (0xF<<0)
+#define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET_SHIFT 0
+#define ETH_TX_PARSE_BD_CS_ANY_FLG (0x1<<4)
+#define ETH_TX_PARSE_BD_CS_ANY_FLG_SHIFT 4
+#define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
+#define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
+#define ETH_TX_PARSE_BD_LLC_SNAP_EN (0x1<<6)
+#define ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT 6
+#define ETH_TX_PARSE_BD_NS_FLG (0x1<<7)
+#define ETH_TX_PARSE_BD_NS_FLG_SHIFT 7
+u8 tcp_flags;
+#define ETH_TX_PARSE_BD_FIN_FLG (0x1<<0)
+#define ETH_TX_PARSE_BD_FIN_FLG_SHIFT 0
+#define ETH_TX_PARSE_BD_SYN_FLG (0x1<<1)
+#define ETH_TX_PARSE_BD_SYN_FLG_SHIFT 1
+#define ETH_TX_PARSE_BD_RST_FLG (0x1<<2)
+#define ETH_TX_PARSE_BD_RST_FLG_SHIFT 2
+#define ETH_TX_PARSE_BD_PSH_FLG (0x1<<3)
+#define ETH_TX_PARSE_BD_PSH_FLG_SHIFT 3
+#define ETH_TX_PARSE_BD_ACK_FLG (0x1<<4)
+#define ETH_TX_PARSE_BD_ACK_FLG_SHIFT 4
+#define ETH_TX_PARSE_BD_URG_FLG (0x1<<5)
+#define ETH_TX_PARSE_BD_URG_FLG_SHIFT 5
+#define ETH_TX_PARSE_BD_ECE_FLG (0x1<<6)
+#define ETH_TX_PARSE_BD_ECE_FLG_SHIFT 6
+#define ETH_TX_PARSE_BD_CWR_FLG (0x1<<7)
+#define ETH_TX_PARSE_BD_CWR_FLG_SHIFT 7
+u8 ip_hlen;
+s8 cs_offset;
+u16 total_hlen;
+#endif
+#if defined(__BIG_ENDIAN)
+u16 tcp_pseudo_csum;
+u16 lso_mss;
+#elif defined(__LITTLE_ENDIAN)
+u16 lso_mss;
+u16 tcp_pseudo_csum;
+#endif
+#if defined(__BIG_ENDIAN)
+u32 tcp_send_seq;
+u16 ip_id;
+#elif defined(__LITTLE_ENDIAN)
+u16 ip_id;
+u32 tcp_send_seq;
+#endif
+};
+
+/*
+* The last BD in the BD memory will hold a pointer to the next BD memory
+*/
+struct eth_tx_next_bd {
+u32 addr_lo;
+u32 addr_hi;
+u8 reserved[8];
+};
+
+/*
+* union for 3 Bd types
+*/
+union eth_tx_bd_types {
+struct eth_tx_bd reg_bd;
+struct eth_tx_parse_bd parse_bd;
+struct eth_tx_next_bd next_bd;
+};
+
+/*
+* The eth storm context of Xstorm
+*/
+struct xstorm_eth_st_context {
+u32 tx_bd_page_base_lo;
+u32 tx_bd_page_base_hi;
+#if defined(__BIG_ENDIAN)
+u16 tx_bd_cons;
+u8 __reserved0;
+u8 __local_tx_bd_prod;
+#elif defined(__LITTLE_ENDIAN)
+u8 __local_tx_bd_prod;
+u8 __reserved0;
+u16 tx_bd_cons;
+#endif
+u32 db_data_addr_lo;
+u32 db_data_addr_hi;
+u32 __pkt_cons;
+u32 __gso_next;
+u32 is_eth_conn_1b;
+union eth_tx_bd_types __bds[13];
+};
+
+/*
+* The eth storm context of Cstorm
+*/
+struct cstorm_eth_st_context {
+#if defined(__BIG_ENDIAN)
+u16 __reserved0;
+u8 sb_index_number;
+u8 status_block_id;
+#elif defined(__LITTLE_ENDIAN)
+u8 status_block_id;
+u8 sb_index_number;
+u16 __reserved0;
+#endif
+u32 __reserved1[3];
+};
+
+/*
+* Ethernet connection context
+*/
+struct eth_context {
+struct ustorm_eth_st_context ustorm_st_context;
+struct tstorm_eth_st_context tstorm_st_context;
+struct xstorm_eth_ag_context xstorm_ag_context;
+struct tstorm_eth_ag_context tstorm_ag_context;
+struct cstorm_eth_ag_context cstorm_ag_context;
+struct ustorm_eth_ag_context ustorm_ag_context;
+struct timers_block_context timers_context;
+struct xstorm_eth_st_context xstorm_st_context;
+struct cstorm_eth_st_context cstorm_st_context;
+};
+
+
+/*
+* ethernet doorbell
+*/
+struct eth_tx_doorbell {
+#if defined(__BIG_ENDIAN)
+u16 npackets;
+u8 params;
+#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
+#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
+#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
+#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
+#define ETH_TX_DOORBELL_SPARE (0x1<<7)
+#define ETH_TX_DOORBELL_SPARE_SHIFT 7
+struct doorbell_hdr hdr;
+#elif defined(__LITTLE_ENDIAN)
+struct doorbell_hdr hdr;
+u8 params;
+#define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
+#define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
+#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
+#define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
+#define ETH_TX_DOORBELL_SPARE (0x1<<7)
+#define ETH_TX_DOORBELL_SPARE_SHIFT 7
+u16 npackets;
+#endif
+};
+
+
+/*
+* ustorm status block
+*/
+struct ustorm_def_status_block {
+u16 index_values[HC_USTORM_DEF_SB_NUM_INDICES];
+#if defined(__BIG_ENDIAN)
+u8 status_block_id;
+u8 reserved0;
+u16 status_block_index;
+#elif defined(__LITTLE_ENDIAN)
+u16 status_block_index;
+u8 reserved0;
+u8 status_block_id;
+#endif
+u32 __flags;
+};
+
+/*
+* cstorm status block
+*/
+struct cstorm_def_status_block {
+u16 index_values[HC_CSTORM_DEF_SB_NUM_INDICES];
+#if defined(__BIG_ENDIAN)
+u8 status_block_id;
+u8 reserved0;
+u16 status_block_index;
+#elif defined(__LITTLE_ENDIAN)
+u16 status_block_index;
+u8 reserved0;
+u8 status_block_id;
+#endif
+u32 __flags;
+};
+
+/*
+* xstorm status block
+*/
+struct xstorm_def_status_block {
+u16 index_values[HC_XSTORM_DEF_SB_NUM_INDICES];
+#if defined(__BIG_ENDIAN)
+u8 status_block_id;
+u8 reserved0;
+u16 status_block_index;
+#elif defined(__LITTLE_ENDIAN)
+u16 status_block_index;
+u8 reserved0;
+u8 status_block_id;
+#endif
+u32 __flags;
+};
+
+/*
+* tstorm status block
+*/
+struct tstorm_def_status_block {
+u16 index_values[HC_TSTORM_DEF_SB_NUM_INDICES];
+#if defined(__BIG_ENDIAN)
+u8 status_block_id;
+u8 reserved0;
+u16 status_block_index;
+#elif defined(__LITTLE_ENDIAN)
+u16 status_block_index;
+u8 reserved0;
+u8 status_block_id;
+#endif
+u32 __flags;
+};
+
+/*
+* host status block
+*/
+struct host_def_status_block {
+struct atten_def_status_block atten_status_block;
+struct ustorm_def_status_block u_def_status_block;
+struct cstorm_def_status_block c_def_status_block;
+struct xstorm_def_status_block x_def_status_block;
+struct tstorm_def_status_block t_def_status_block;
+};
+
+
+/*
+* ustorm status block
+*/
+struct ustorm_status_block {
+u16 index_values[HC_USTORM_SB_NUM_INDICES];
+#if defined(__BIG_ENDIAN)
+u8 status_block_id;
+u8 reserved0;
+u16 status_block_index;
+#elif defined(__LITTLE_ENDIAN)
+u16 status_block_index;
+u8 reserved0;
+u8 status_block_id;
+#endif
+u32 __flags;
+};
+
+/*
+* cstorm status block
+*/
+struct cstorm_status_block {
+u16 index_values[HC_CSTORM_SB_NUM_INDICES];
+#if defined(__BIG_ENDIAN)
+u8 status_block_id;
+u8 reserved0;
+u16 status_block_index;
+#elif defined(__LITTLE_ENDIAN)
+u16 status_block_index;
+u8 reserved0;
+u8 status_block_id;
+#endif
+u32 __flags;
+};
+
+/*
+* host status block
+*/
+struct host_status_block {
+struct ustorm_status_block u_status_block;
+struct cstorm_status_block c_status_block;
+};
+
+
+
+
+/*
+* The data for RSS setup ramrod
+*/
+struct eth_client_setup_ramrod_data {
+u32 client_id_5b;
+#if defined(__BIG_ENDIAN)
+u16 reserved1;
+u8 reserved0;
+u8 is_rdma_1b;
+#elif defined(__LITTLE_ENDIAN)
+u8 is_rdma_1b;
+u8 reserved0;
+u16 reserved1;
+#endif
+};
+
+
+/*
+* L2 dynamic host coalescing init parameters
+*/
+struct eth_dynamic_hc_config {
+u32 threshold[3];
+u8 hc_timeout[4];
+};
+
+
+/*
+* regular eth FP CQE parameters struct
+*/
+struct eth_fast_path_rx_cqe {
+#if defined(__BIG_ENDIAN)
+u8 placement_offset;
+u8 status_flags;
+#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
+#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
+#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
+#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
+#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
+#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
+#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
+#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
+#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
+#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
+#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
+#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
+u8 error_flags;
+#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<0)
+#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 0
+#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<1)
+#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 1
+#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<2)
+#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 2
+#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x1F<<3)
+#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 3
+u8 type;
+#elif defined(__LITTLE_ENDIAN)
+u8 type;
+u8 error_flags;
+#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<0)
+#define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 0
+#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<1)
+#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 1
+#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<2)
+#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 2
+#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x1F<<3)
+#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 3
+u8 status_flags;
+#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
+#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
+#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
+#define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
+#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
+#define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
+#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
+#define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
+#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
+#define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
+#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
+#define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
+u8 placement_offset;
+#endif
+u32 rss_hash_result;
+#if defined(__BIG_ENDIAN)
+u16 pkt_len;
+u16 vlan_tag;
+#elif defined(__LITTLE_ENDIAN)
+u16 vlan_tag;
+u16 pkt_len;
+#endif
+#if defined(__BIG_ENDIAN)
+struct parsing_flags pars_flags;
+u16 l4_csum;
+#elif defined(__LITTLE_ENDIAN)
+u16 l4_csum;
+struct parsing_flags pars_flags;
+#endif
+};
+
+
+/*
+* The data for RSS setup ramrod
+*/
+struct eth_halt_ramrod_data {
+u32 client_id_5b;
+u32 reserved0;
+};
+
+
+/*
+* Place holder for ramrods protocol specific data
+*/
+struct ramrod_data {
+u32 data_lo;
+u32 data_hi;
+};
+
+/*
+* union for ramrod data for ethernet protocol (CQE) (force size of 16 bits)
+*/
+union eth_ramrod_data {
+struct ramrod_data general;
+};
+
+
+
+/*
+* Eth Rx Cqe structure- general structure for ramrods
+*/
+struct common_ramrod_eth_rx_cqe {
+#if defined(__BIG_ENDIAN)
+u16 reserved;
+u8 conn_type_3b;
+u8 type;
+#elif defined(__LITTLE_ENDIAN)
+u8 type;
+u8 conn_type_3b;
+u16 reserved;
+#endif
+u32 conn_and_cmd_data;
+#define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
+#define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
+#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
+#define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
+struct ramrod_data protocol_data;
+};
+
+/*
+* Rx Last CQE in page (in ETH)
+*/
+struct eth_rx_cqe_next_page {
+u32 addr_lo;
+u32 addr_hi;
+u32 reserved0;
+u32 reserved1;
+};
+
+/*
+* union for all eth rx cqe types (fix their sizes)
+*/
+union eth_rx_cqe {
+struct eth_fast_path_rx_cqe fast_path_cqe;
+struct common_ramrod_eth_rx_cqe ramrod_cqe;
+struct eth_rx_cqe_next_page next_page_cqe;
+};
+
+
+
+/*
+* common data for all protocols
+*/
+struct spe_hdr {
+u32 conn_and_cmd_data;
+#define SPE_HDR_CID (0xFFFFFF<<0)
+#define SPE_HDR_CID_SHIFT 0
+#define SPE_HDR_CMD_ID (0xFF<<24)
+#define SPE_HDR_CMD_ID_SHIFT 24
+#if defined(__BIG_ENDIAN)
+u16 reserved;
+u16 type;
+#define SPE_HDR_CONN_TYPE (0xFF<<0)
+#define SPE_HDR_CONN_TYPE_SHIFT 0
+#define SPE_HDR_COMMON_RAMROD (0xFF<<8)
+#define SPE_HDR_COMMON_RAMROD_SHIFT 8
+#elif defined(__LITTLE_ENDIAN)
+u16 type;
+#define SPE_HDR_CONN_TYPE (0xFF<<0)
+#define SPE_HDR_CONN_TYPE_SHIFT 0
+#define SPE_HDR_COMMON_RAMROD (0xFF<<8)
+#define SPE_HDR_COMMON_RAMROD_SHIFT 8
+u16 reserved;
+#endif
+};
+
+struct regpair {
+u32 lo;
+u32 hi;
+};
+
+/*
+* ethernet slow path element
+*/
+union eth_specific_data {
+u8 protocol_data[8];
+struct regpair mac_config_addr;
+struct eth_client_setup_ramrod_data client_setup_ramrod_data;
+struct eth_halt_ramrod_data halt_ramrod_data;
+struct regpair leading_cqe_addr;
+struct regpair update_data_addr;
+};
+
+/*
+* ethernet slow path element
+*/
+struct eth_spe {
+struct spe_hdr hdr;
+union eth_specific_data data;
+};
+
+
+
+
+
+
+/*
+* doorbell data in host memory
+*/
+struct eth_tx_db_data {
+u32 packets_prod;
+#if defined(__BIG_ENDIAN)
+u16 reserved;
+u16 bds_prod;
+#elif defined(__LITTLE_ENDIAN)
+u16 bds_prod;
+u16 reserved;
+#endif
+};
+
+
+
+
+/*
+* Common configuration parameters per port in Tstorm
+*/
+struct tstorm_eth_port_common_config {
+#if defined(__BIG_ENDIAN)
+u8 reserved;
+u8 leading_client_id;
+u8 rss_result_mask;
+u8 config_flags;
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_ENABLE (0x1<<4)
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_ENABLE_SHIFT 4
+#define TSTORM_ETH_PORT_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<5)
+#define TSTORM_ETH_PORT_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 5
+#define __TSTORM_ETH_PORT_COMMON_CONFIG_RESERVED0 (0x3<<6)
+#define __TSTORM_ETH_PORT_COMMON_CONFIG_RESERVED0_SHIFT 6
+#elif defined(__LITTLE_ENDIAN)
+u8 config_flags;
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_ENABLE (0x1<<4)
+#define TSTORM_ETH_PORT_COMMON_CONFIG_RSS_ENABLE_SHIFT 4
+#define TSTORM_ETH_PORT_COMMON_CONFIG_DEFAULT_ENABLE (0x1<<5)
+#define TSTORM_ETH_PORT_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 5
+#define __TSTORM_ETH_PORT_COMMON_CONFIG_RESERVED0 (0x3<<6)
+#define __TSTORM_ETH_PORT_COMMON_CONFIG_RESERVED0_SHIFT 6
+u8 rss_result_mask;
+u8 leading_client_id;
+u8 reserved;
+#endif
+};
+
+/*
+* parameters for eth update ramrod
+*/
+struct eth_update_ramrod_data {
+struct tstorm_eth_port_common_config port_config;
+u8 indirectionTable[128];
+u32 reserved0;
+};
+
+
+/*
+* MAC filtering configuration command header
+*/
+struct mac_configuration_hdr {
+#if defined(__BIG_ENDIAN)
+u16 reserved0;
+u8 offset;
+u8 length_6b;
+#elif defined(__LITTLE_ENDIAN)
+u8 length_6b;
+u8 offset;
+u16 reserved0;
+#endif
+u32 reserved1;
+};
+
+/*
+* MAC address in list for ramrod
+*/
+struct tstorm_cam_entry {
+#if defined(__BIG_ENDIAN)
+u16 middle_mac_addr;
+u16 lsb_mac_addr;
+#elif defined(__LITTLE_ENDIAN)
+u16 lsb_mac_addr;
+u16 middle_mac_addr;
+#endif
+#if defined(__BIG_ENDIAN)
+u16 flags;
+#define TSTORM_CAM_ENTRY_PORT_ID (0x1<<0)
+#define TSTORM_CAM_ENTRY_PORT_ID_SHIFT 0
+#define TSTORM_CAM_ENTRY_RSRVVAL0 (0x7<<1)
+#define TSTORM_CAM_ENTRY_RSRVVAL0_SHIFT 1
+#define TSTORM_CAM_ENTRY_RESERVED0 (0xFFF<<4)
+#define TSTORM_CAM_ENTRY_RESERVED0_SHIFT 4
+u16 msb_mac_addr;
+#elif defined(__LITTLE_ENDIAN)
+u16 msb_mac_addr;
+u16 flags;
+#define TSTORM_CAM_ENTRY_PORT_ID (0x1<<0)
+#define TSTORM_CAM_ENTRY_PORT_ID_SHIFT 0
+#define TSTORM_CAM_ENTRY_RSRVVAL0 (0x7<<1)
+#define TSTORM_CAM_ENTRY_RSRVVAL0_SHIFT 1
+#define TSTORM_CAM_ENTRY_RESERVED0 (0xFFF<<4)
+#define TSTORM_CAM_ENTRY_RESERVED0_SHIFT 4
+#endif
+};
+
+/*
+* MAC filtering: CAM target table entry
+*/
+struct tstorm_cam_target_table_entry {
+#if defined(__BIG_ENDIAN)
+u16 vlan_id;
+u8 client_id;
+u8 flags;
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST (0x1<<0)
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST_SHIFT 0
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<1)
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 1
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE (0x1<<2)
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE_SHIFT 2
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC (0x1<<3)
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC_SHIFT 3
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0 (0xF<<4)
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0_SHIFT 4
+#elif defined(__LITTLE_ENDIAN)
+u8 flags;
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST (0x1<<0)
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST_SHIFT 0
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<1)
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 1
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE (0x1<<2)
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE_SHIFT 2
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC (0x1<<3)
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC_SHIFT 3
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0 (0xF<<4)
+#define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0_SHIFT 4
+u8 client_id;
+u16 vlan_id;
+#endif
+};
+
+/*
+* MAC address in list for ramrod
+*/
+struct mac_configuration_entry {
+struct tstorm_cam_entry cam_entry;
+struct tstorm_cam_target_table_entry target_table_entry;
+};
+
+/*
+* MAC filtering configuration command
+*/
+struct mac_configuration_cmd {
+struct mac_configuration_hdr hdr;
+struct mac_configuration_entry config_table[64];
+};
+
+
+
+
+/*
+* Configuration parameters per client in Tstorm
+*/
+struct tstorm_eth_client_config {
+#if defined(__BIG_ENDIAN)
+u16 statistics_counter_id;
+u16 max_buffer_size;
+#elif defined(__LITTLE_ENDIAN)
+u16 max_buffer_size;
+u16 statistics_counter_id;
+#endif
+#if defined(__BIG_ENDIAN)
+u16 drop_flags;
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR (0x1<<2)
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR_SHIFT 2
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<3)
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 3
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<4)
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 4
+#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x7FF<<5)
+#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 5
+u16 config_flags;
+#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0)
+#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0
+#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1)
+#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1
+#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x3FFF<<2)
+#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 2
+#elif defined(__LITTLE_ENDIAN)
+u16 config_flags;
+#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE (0x1<<0)
+#define TSTORM_ETH_CLIENT_CONFIG_VLAN_REMOVAL_ENABLE_SHIFT 0
+#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1<<1)
+#define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 1
+#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0 (0x3FFF<<2)
+#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED0_SHIFT 2
+u16 drop_flags;
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1<<0)
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1<<1)
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR (0x1<<2)
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_MAC_ERR_SHIFT 2
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1<<3)
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 3
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1<<4)
+#define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 4
+#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x7FF<<5)
+#define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 5
+#endif
+};
+
+
+/*
+* MAC filtering configuration parameters per port in Tstorm
+*/
+struct tstorm_eth_mac_filter_config {
+u32 ucast_drop_all;
+u32 ucast_accept_all;
+u32 mcast_drop_all;
+u32 mcast_accept_all;
+u32 bcast_drop_all;
+u32 bcast_accept_all;
+u32 strict_vlan;
+};
+
+
+
+
+
+
+struct rate_shaping_per_protocol {
+#if defined(__BIG_ENDIAN)
+u16 reserved0;
+u16 protocol_rate;
+#elif defined(__LITTLE_ENDIAN)
+u16 protocol_rate;
+u16 reserved0;
+#endif
+u32 protocol_quota;
+s32 current_credit;
+u32 reserved;
+};
+
+struct rate_shaping_vars {
+struct rate_shaping_per_protocol protocol_vars[NUM_OF_PROTOCOLS];
+u32 pause_mask;
+u32 periodic_stop;
+u32 rs_periodic_timeout;
+u32 rs_threshold;
+u32 last_periodic_time;
+u32 reserved;
+};
+
+struct fairness_per_protocol {
+u32 credit_delta;
+s32 fair_credit;
+#if defined(__BIG_ENDIAN)
+u16 reserved0;
+u8 state;
+u8 weight;
+#elif defined(__LITTLE_ENDIAN)
+u8 weight;
+u8 state;
+u16 reserved0;
+#endif
+u32 reserved1;
+};
+
+struct fairness_vars {
+struct fairness_per_protocol protocol_vars[NUM_OF_PROTOCOLS];
+u32 upper_bound;
+u32 port_rate;
+u32 pause_mask;
+u32 fair_threshold;
+};
+
+struct safc_struct {
+u32 cur_pause_mask;
+u32 expire_time;
+#if defined(__BIG_ENDIAN)
+u16 reserved0;
+u8 cur_cos_types;
+u8 safc_timeout_usec;
+#elif defined(__LITTLE_ENDIAN)
+u8 safc_timeout_usec;
+u8 cur_cos_types;
+u16 reserved0;
+#endif
+u32 reserved1;
+};
+
+struct demo_struct {
+u8 con_number[NUM_OF_PROTOCOLS];
+#if defined(__BIG_ENDIAN)
+u8 reserved1;
+u8 fairness_enable;
+u8 rate_shaping_enable;
+u8 cmng_enable;
+#elif defined(__LITTLE_ENDIAN)
+u8 cmng_enable;
+u8 rate_shaping_enable;
+u8 fairness_enable;
+u8 reserved1;
+#endif
+};
+
+struct cmng_struct {
+struct rate_shaping_vars rs_vars;
+struct fairness_vars fair_vars;
+struct safc_struct safc_vars;
+struct demo_struct demo_vars;
+};
+
+
+
+struct cos_to_protocol {
+u8 mask[MAX_COS_NUMBER];
+};
+
+
+
+
+
+
+/*
+* Common statistics collected by the Xstorm (per port)
+*/
+struct xstorm_common_stats {
+struct regpair total_sent_bytes;
+u32 total_sent_pkts;
+u32 unicast_pkts_sent;
+struct regpair unicast_bytes_sent;
+struct regpair multicast_bytes_sent;
+u32 multicast_pkts_sent;
+u32 broadcast_pkts_sent;
+struct regpair broadcast_bytes_sent;
+struct regpair done;
+};
+
+/*
+* Protocol-common statistics collected by the Tstorm (per client)
+*/
+struct tstorm_per_client_stats {
+struct regpair total_rcv_bytes;
+struct regpair rcv_unicast_bytes;
+struct regpair rcv_broadcast_bytes;
+struct regpair rcv_multicast_bytes;
+struct regpair rcv_error_bytes;
+u32 total_rcv_pkts;
+u32 rcv_unicast_pkts;
+u32 rcv_broadcast_pkts;
+u32 rcv_multicast_pkts;
+u32 no_buff_discard;
+u32 errors_discard;
+u32 ttl0_discard;
+u32 reserved;
+};
+
+/*
+* Protocol-common statistics collected by the Tstorm (per port)
+*/
+struct tstorm_common_stats {
+struct tstorm_per_client_stats client_statistics[MAX_T_STAT_COUNTER_ID];
+u32 mac_filter_discard;
+u32 xxoverflow_discard;
+u32 brb_truncate_discard;
+u32 pkts_till_64B;
+u32 pkts_65_to_127B;
+u32 pkts_128_to_255B;
+u32 pkts_256_to_511B;
+u32 pkts_512_to_1023B;
+u32 pkts_1024_to_1522B;
+u32 pkts_1523_to_9022B;
+struct regpair done;
+};
+
+/*
+* Eth statistics query sturcture for the eth_stats_quesry ramrod
+*/
+struct eth_stats_query {
+struct xstorm_common_stats xstorm_common;
+struct tstorm_common_stats tstorm_common;
+};
+
+
+
+
+/*
+* FW version stored in the Xstorm RAM
+*/
+struct fw_version {
+#if defined(__BIG_ENDIAN)
+u16 patch;
+u8 primary;
+u8 client;
+#elif defined(__LITTLE_ENDIAN)
+u8 client;
+u8 primary;
+u16 patch;
+#endif
+u32 flags;
+#define FW_VERSION_OPTIMIZED (0x1<<0)
+#define FW_VERSION_OPTIMIZED_SHIFT 0
+#define __FW_VERSION_RESERVED (0x7FFFFFFF<<1)
+#define __FW_VERSION_RESERVED_SHIFT 1
+};
+
+
+/*
+* FW version stored in first line of pram
+*/
+struct pram_fw_version {
+#if defined(__BIG_ENDIAN)
+u16 patch;
+u8 primary;
+u8 client;
+#elif defined(__LITTLE_ENDIAN)
+u8 client;
+u8 primary;
+u16 patch;
+#endif
+u8 flags;
+#define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
+#define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
+#define PRAM_FW_VERSION_STORM_ID (0x3<<1)
+#define PRAM_FW_VERSION_STORM_ID_SHIFT 1
+#define __PRAM_FW_VERSION_RESERVED0 (0x1F<<3)
+#define __PRAM_FW_VERSION_RESERVED0_SHIFT 3
+};
+
+/*
+* The send queue element
+*/
+struct slow_path_element {
+struct spe_hdr hdr;
+u8 protocol_data[8];
+};
+
+/*
+* eth/toe flags that indicate if to query
+*/
+struct stats_indication_flags {
+u32 collect_eth;
+u32 collect_toe;
+};
+
+#pragma pack(pop)
+
+#endif
-- 
1.4.2



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