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Date:	Thu, 15 Nov 2007 18:17:11 -0800
From:	"Michael Chan" <mchan@...adcom.com>
To:	"Rick Jones" <rick.jones2@...com>
cc:	"David Miller" <davem@...emloft.net>, mcarlson@...adcom.com,
	"netdev" <netdev@...r.kernel.org>, andy@...yhouse.net
Subject: Re: [PATCH 10/13] tg3: Increase the PCI MRRS

On Thu, 2007-11-15 at 16:32 -0800, Rick Jones wrote:

> I'm going to get very rapidly out of my PCI depth, but on one or the 
> other (e vs X) isn't is possible from the standpoint of PCI for a device 
> to have multiple transactions outstanding at a time?

Yes, see my other response.  Multiple outstanding transactions and a
bigger maximum payload size will increase the throughput without the
need to increase the MRRS.

> 
> Does the current value of the MRRS get displayed in lspci output?  It 
> wouldn't be a slam dunk, but if someone were looking at that and saw the 
> value large they might make an educated guess.
> 

Yes:
        Capabilities: [ac] Express Endpoint IRQ 0
                Device: Supported: MaxPayload 512 bytes, PhantFunc 0, ExtTag-
                Device: Latency L0s <1us, L1 <2us
                Device: AtnBtn- AtnInd- PwrInd-
                Device: Errors: Correctable- Non-Fatal- Fatal- Unsupported-
                Device: RlxdOrd+ ExtTag- PhantFunc- AuxPwr+ NoSnoop+
                Device: MaxPayload 256 bytes, MaxReadReq 512 bytes



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