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Message-ID: <Pine.LNX.4.64.0801291421440.7503@pc-213-140-179-32.aina.net>
Date: Tue, 29 Jan 2008 14:27:26 +0200 (EET)
From: Kalle Pokki <kalle.pokki@....com>
To: netdev@...r.kernel.org, Bryan Wu <bryan.wu@...log.com>
Subject: [PATCH] bfin_mac: Fix MDIO clock frequency
The clock divisor is set to all ones at reset.
---
drivers/net/bfin_mac.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c
index eb97175..c199633 100644
--- a/drivers/net/bfin_mac.c
+++ b/drivers/net/bfin_mac.c
@@ -425,7 +425,7 @@ static int mii_probe(struct net_device *dev)
/* MDC = 2.5 MHz */
sysctl = bfin_read_EMAC_SYSCTL();
- sysctl |= SET_MDCDIV(24);
+ sysctl = (sysctl & ~MDCDIV) | SET_MDCDIV(24);
bfin_write_EMAC_SYSCTL(sysctl);
/* search for connect PHY device */
--
1.4.4.2
--
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