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Date:	Sat, 16 Feb 2008 18:55:38 -0800
From:	"Subbu Seetharaman" <subbus@...verengines.com>
To:	netdev@...r.kernel.org
Subject: [PATHCH 13/16]  ServerEngines 10Gb NIC driver

F/W header files.

------------------
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ioctl_common_bmap.h benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ioctl_common_bmap.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ioctl_common_bmap.h	1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ioctl_common_bmap.h	2008-02-14 15:23:07.833201936 +0530
@@ -0,0 +1,1398 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@...verengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __ioctl_common_bmap_h__
+#define __ioctl_common_bmap_h__
+#include "setypes.h"
+#include "ioctl_types_bmap.h"
+#include "ioctl_hdr_bmap.h"
+#include "host_struct_bmap.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_C_ASSERT
+#define SG_C_ASSERT(_name_, _condition_)
+#endif
+
+typedef struct _BE_LINK_STATUS {
+	u8 mac0_duplex;
+	u8 mac0_speed;
+	u8 mac1_duplex;
+	u8 mac1_speed;
+	u8 mgmt_mac_duplex;
+	u8 mgmt_mac_speed;
+	u8 active_port;
+	u8 rsvd0;
+	u8 mac0_fault;
+	u8 mac1_fault;
+	u16 rsvd1;
+} SG_PACK BE_LINK_STATUS, *PBE_LINK_STATUS;
+
+typedef struct _IOCTL_COMMON_ANON_170_REQUEST {
+	u32 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_170_REQUEST, *PIOCTL_COMMON_ANON_170_REQUEST;
+
+typedef union _LINK_STATUS_QUERY_PARAMS {
+	BE_LINK_STATUS response;
+	IOCTL_COMMON_ANON_170_REQUEST request;
+} SG_PACK LINK_STATUS_QUERY_PARAMS, *PLINK_STATUS_QUERY_PARAMS;
+
+/*
+ *  Queries the the link status for all ports.  The valid values below
+ *  DO NOT indicate that  a particular duplex or speed is supported by
+ *  BladeEngine. These enumerations simply  list all possible duplexes
+ *  and speeds for any port. Consult BladeEngine product  documentation
+ *  for the supported parameters.
+ */
+typedef struct _IOCTL_COMMON_NTWK_LINK_STATUS_QUERY {
+	IOCTL_HEADER header;
+	LINK_STATUS_QUERY_PARAMS params;
+} SG_PACK IOCTL_COMMON_NTWK_LINK_STATUS_QUERY,
+    *PIOCTL_COMMON_NTWK_LINK_STATUS_QUERY;
+
+typedef struct _IOCTL_COMMON_ANON_171_REQUEST {
+	u8 type;
+	u8 port;
+	u8 mac1;
+	u8 permanent;
+} SG_PACK IOCTL_COMMON_ANON_171_REQUEST, *PIOCTL_COMMON_ANON_171_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_172_RESPONSE {
+	MAC_ADDRESS_FORMAT mac;
+} SG_PACK IOCTL_COMMON_ANON_172_RESPONSE, *PIOCTL_COMMON_ANON_172_RESPONSE;
+
+typedef union _NTWK_MAC_QUERY_PARAMS {
+	IOCTL_COMMON_ANON_171_REQUEST request;
+	IOCTL_COMMON_ANON_172_RESPONSE response;
+} SG_PACK NTWK_MAC_QUERY_PARAMS, *PNTWK_MAC_QUERY_PARAMS;
+
+/* Queries one MAC address.  */
+typedef struct _IOCTL_COMMON_NTWK_MAC_QUERY {
+	IOCTL_HEADER header;
+	NTWK_MAC_QUERY_PARAMS params;
+} SG_PACK IOCTL_COMMON_NTWK_MAC_QUERY, *PIOCTL_COMMON_NTWK_MAC_QUERY;
+
+typedef struct _MAC_SET_PARAMS_IN {
+	u8 type;
+	u8 port;
+	u8 mac1;
+	u8 invalidate;
+	MAC_ADDRESS_FORMAT mac;
+} SG_PACK MAC_SET_PARAMS_IN, *PMAC_SET_PARAMS_IN;
+
+typedef struct _MAC_SET_PARAMS_OUT {
+	u32 rsvd0;
+} SG_PACK MAC_SET_PARAMS_OUT, *PMAC_SET_PARAMS_OUT;
+
+typedef union _MAC_SET_PARAMS {
+	MAC_SET_PARAMS_IN request;
+	MAC_SET_PARAMS_OUT response;
+} SG_PACK MAC_SET_PARAMS, *PMAC_SET_PARAMS;
+
+/* Sets a MAC address.  */
+typedef struct _IOCTL_COMMON_NTWK_MAC_SET {
+	IOCTL_HEADER header;
+	MAC_SET_PARAMS params;
+} SG_PACK IOCTL_COMMON_NTWK_MAC_SET, *PIOCTL_COMMON_NTWK_MAC_SET;
+
+/* MAC address list. */
+typedef struct _NTWK_MULTICAST_MAC_LIST {
+	u8 byte[6];
+} SG_PACK NTWK_MULTICAST_MAC_LIST, *PNTWK_MULTICAST_MAC_LIST;
+
+typedef struct _IOCTL_COMMON_NTWK_MULTICAST_SET_REQUEST_PAYLOAD {
+	u16 num_mac;
+	u8 promiscuous;
+	u8 rsvd0;
+	NTWK_MULTICAST_MAC_LIST mac[32];
+} SG_PACK IOCTL_COMMON_NTWK_MULTICAST_SET_REQUEST_PAYLOAD,
+    *PIOCTL_COMMON_NTWK_MULTICAST_SET_REQUEST_PAYLOAD;
+
+typedef struct _IOCTL_COMMON_ANON_174_RESPONSE {
+	u32 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_174_RESPONSE, *PIOCTL_COMMON_ANON_174_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_173_PARAMS {
+	IOCTL_COMMON_NTWK_MULTICAST_SET_REQUEST_PAYLOAD request;
+	IOCTL_COMMON_ANON_174_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_173_PARAMS, *PIOCTL_COMMON_ANON_173_PARAMS;
+
+/*
+ *  Sets multicast address hash. The MPU will merge the MAC address lists
+ *  from all clients,  including the networking and storage functions.
+ *  This ioctl may fail if the final merged  list of MAC addresses exceeds
+ *  32 entries.
+ */
+typedef struct _IOCTL_COMMON_NTWK_MULTICAST_SET {
+	IOCTL_HEADER header;
+	IOCTL_COMMON_ANON_173_PARAMS params;
+} SG_PACK IOCTL_COMMON_NTWK_MULTICAST_SET,
+    *PIOCTL_COMMON_NTWK_MULTICAST_SET;
+
+typedef struct _IOCTL_COMMON_NTWK_VLAN_CONFIG_REQUEST_PAYLOAD {
+	u16 num_vlan;
+	u8 promiscuous;
+	u8 rsvd0;
+	u16 vlan_tag[32];
+} SG_PACK IOCTL_COMMON_NTWK_VLAN_CONFIG_REQUEST_PAYLOAD,
+    *PIOCTL_COMMON_NTWK_VLAN_CONFIG_REQUEST_PAYLOAD;
+
+typedef struct _IOCTL_COMMON_ANON_176_RESPONSE {
+	u32 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_176_RESPONSE, *PIOCTL_COMMON_ANON_176_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_175_PARAMS {
+	IOCTL_COMMON_NTWK_VLAN_CONFIG_REQUEST_PAYLOAD request;
+	IOCTL_COMMON_ANON_176_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_175_PARAMS, *PIOCTL_COMMON_ANON_175_PARAMS;
+
+/*
+ *  Sets VLAN tag filter. The MPU will merge the VLAN tag list from all
+ *  clients, including  the networking and storage functions. This ioctl
+ *  may fail if the final vlan_tag array  (from all functions) is longer
+ *  than 32 entries.
+ */
+typedef struct _IOCTL_COMMON_NTWK_VLAN_CONFIG {
+	IOCTL_HEADER header;
+	IOCTL_COMMON_ANON_175_PARAMS params;
+} SG_PACK IOCTL_COMMON_NTWK_VLAN_CONFIG, *PIOCTL_COMMON_NTWK_VLAN_CONFIG;
+
+typedef struct _IOCTL_COMMON_ANON_178_REQUEST {
+	u16 num_pages;
+	u16 type;
+	PHYS_ADDR scratch_pa;
+	VIRT_ADDR sratch_va;
+	VIRT_ADDR pages_va;
+	PHYS_ADDR pages[16];
+} SG_PACK IOCTL_COMMON_ANON_178_REQUEST, *PIOCTL_COMMON_ANON_178_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_179_RESPONSE {
+	u32 num_used;
+} SG_PACK IOCTL_COMMON_ANON_179_RESPONSE, *PIOCTL_COMMON_ANON_179_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_177_PARAMS {
+	IOCTL_COMMON_ANON_178_REQUEST request;
+	IOCTL_COMMON_ANON_179_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_177_PARAMS, *PIOCTL_COMMON_ANON_177_PARAMS;
+
+/*
+ *  Posts template headers buffers. These should be posted before any
+ *  connections are  offloaded. Each buffer holds 32 template headers
+ *  at 128 bytes each.  This may be issued  multiple times to post the
+ *  template header buffers in smaller pieces. This allows the  driver
+ *  to delay allocating template header buffers until the connections
+ *  are actually  used.  Only protection domain 0 may post template header
+ *  buffers.
+ */
+typedef struct _IOCTL_COMMON_ADD_TEMPLATE_HEADER_BUFFERS {
+	IOCTL_HEADER header;
+	IOCTL_COMMON_ANON_177_PARAMS params;
+} SG_PACK IOCTL_COMMON_ADD_TEMPLATE_HEADER_BUFFERS,
+    *PIOCTL_COMMON_ADD_TEMPLATE_HEADER_BUFFERS;
+
+typedef struct _IOCTL_COMMON_ANON_181_REQUEST {
+	u16 type;
+	u16 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_181_REQUEST, *PIOCTL_COMMON_ANON_181_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_182_RESPONSE {
+	u32 num_removed;
+} SG_PACK IOCTL_COMMON_ANON_182_RESPONSE, *PIOCTL_COMMON_ANON_182_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_180_PARAMS {
+	IOCTL_COMMON_ANON_181_REQUEST request;
+	IOCTL_COMMON_ANON_182_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_180_PARAMS, *PIOCTL_COMMON_ANON_180_PARAMS;
+
+/*
+ *  Frees all template header buffers for the given type. Only protection
+ *  domain 0 may  issue this request. The IOCTL may fail if any rings
+ *  which use these template headers  are still in use.
+ */
+typedef struct _IOCTL_COMMON_REMOVE_TEMPLATE_HEADER_BUFFERS {
+	IOCTL_HEADER header;
+	IOCTL_COMMON_ANON_180_PARAMS params;
+} SG_PACK IOCTL_COMMON_REMOVE_TEMPLATE_HEADER_BUFFERS,
+    *PIOCTL_COMMON_REMOVE_TEMPLATE_HEADER_BUFFERS;
+
+typedef struct _IOCTL_COMMON_ANON_184_REQUEST {
+	u16 num;
+	u8 shared;
+	u8 rsvd0;
+	VIRT_ADDR va;
+	PHYS_ADDR page_tables[26];
+} SG_PACK IOCTL_COMMON_ANON_184_REQUEST, *PIOCTL_COMMON_ANON_184_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_185_RESPONSE {
+	u16 num_added;
+	u16 num_total;
+	u16 num_free;
+	u16 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_185_RESPONSE, *PIOCTL_COMMON_ANON_185_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_183_PARAMS {
+	IOCTL_COMMON_ANON_184_REQUEST request;
+	IOCTL_COMMON_ANON_185_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_183_PARAMS, *PIOCTL_COMMON_ANON_183_PARAMS;
+
+/*
+ *  Posts page tables for the UT. This command may be issued multiple
+ *  times to add page  tables to the chip.
+ */
+typedef struct _IOCTL_COMMON_ADD_PAGE_TABLES {
+	IOCTL_HEADER header;
+	IOCTL_COMMON_ANON_183_PARAMS params;
+} SG_PACK IOCTL_COMMON_ADD_PAGE_TABLES, *PIOCTL_COMMON_ADD_PAGE_TABLES;
+
+typedef struct _IOCTL_COMMON_ANON_187_REQUEST {
+	u16 num;
+	u16 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_187_REQUEST, *PIOCTL_COMMON_ANON_187_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_188_RESPONSE {
+	u16 actual_num;
+	u16 total_num;
+	PHYS_ADDR page_tables[27];
+} SG_PACK IOCTL_COMMON_ANON_188_RESPONSE, *PIOCTL_COMMON_ANON_188_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_186_PARAMS {
+	IOCTL_COMMON_ANON_187_REQUEST request;
+	IOCTL_COMMON_ANON_188_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_186_PARAMS, *PIOCTL_COMMON_ANON_186_PARAMS;
+
+/*
+ *  Removes free page tables from the chip. Only page tables that are
+ *  unused may be  removed. Page tables may not be removed in the same
+ *  order as they are posted. This  ioctl returns a list of physical
+ *  addresses for the page tables that were removed.
+ */
+typedef struct _IOCTL_COMMON_REMOVE_PAGE_TABLES {
+	IOCTL_HEADER header;
+	IOCTL_COMMON_ANON_186_PARAMS params;
+} SG_PACK IOCTL_COMMON_REMOVE_PAGE_TABLES,
+    *PIOCTL_COMMON_REMOVE_PAGE_TABLES;
+
+typedef struct _RING_DESTROY_REQUEST {
+	u16 ring_type;
+	u16 id;
+	u8 bypass_flush;
+	u8 rsvd0;
+	u16 rsvd1;
+} SG_PACK RING_DESTROY_REQUEST, *PRING_DESTROY_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_190_RESPONSE {
+	u32 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_190_RESPONSE, *PIOCTL_COMMON_ANON_190_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_189_PARAMS {
+	RING_DESTROY_REQUEST request;
+	IOCTL_COMMON_ANON_190_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_189_PARAMS, *PIOCTL_COMMON_ANON_189_PARAMS;
+/*
+ *  IOCTL for destroying any ring. The connection(s) using the ring should
+ *  be quiesced  before destroying the ring.
+ */
+typedef struct _IOCTL_COMMON_RING_DESTROY {
+	IOCTL_HEADER header;
+	IOCTL_COMMON_ANON_189_PARAMS params;
+} SG_PACK IOCTL_COMMON_RING_DESTROY, *PIOCTL_COMMON_RING_DESTROY;
+
+typedef struct _IOCTL_COMMON_ANON_192_REQUEST {
+	u16 num_pages;
+	u16 rsvd0;
+	CQ_CONTEXT context;
+	PHYS_ADDR pages[4];
+} SG_PACK IOCTL_COMMON_ANON_192_REQUEST, *PIOCTL_COMMON_ANON_192_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_193_RESPONSE {
+	u16 cq_id;
+} SG_PACK IOCTL_COMMON_ANON_193_RESPONSE, *PIOCTL_COMMON_ANON_193_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_191_PARAMS {
+	IOCTL_COMMON_ANON_192_REQUEST request;
+	IOCTL_COMMON_ANON_193_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_191_PARAMS, *PIOCTL_COMMON_ANON_191_PARAMS;
+
+/*
+ *  IOCTL for creating a completion queue. A Completion Queue must span
+ *  at least 1 page and  at most 4 pages. Each completion queue entry
+ *  is 16 bytes regardless of CQ entry format.  Thus the ring must be
+ *  at least 256 entries deep (corresponding to 1 page) and can be at
+ *   most 1024 entries deep (corresponding to 4 pages). The number of
+ *  pages posted must  contain the CQ ring size as encoded in the context.
+ *
+ */
+typedef struct _IOCTL_COMMON_CQ_CREATE {
+	IOCTL_HEADER header;
+	IOCTL_COMMON_ANON_191_PARAMS params;
+} SG_PACK IOCTL_COMMON_CQ_CREATE, *PIOCTL_COMMON_CQ_CREATE;
+
+typedef struct _IOCTL_COMMON_ANON_195_REQUEST {
+	u16 num_pages;
+	u16 new_cq_len;
+	u32 cq_threshold;
+	PHYS_ADDR pages[8];
+} SG_PACK IOCTL_COMMON_ANON_195_REQUEST, *PIOCTL_COMMON_ANON_195_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_196_RESPONSE {
+	u16 pidx_old;
+} SG_PACK IOCTL_COMMON_ANON_196_RESPONSE, *PIOCTL_COMMON_ANON_196_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_194_PARAMS {
+	IOCTL_COMMON_ANON_195_REQUEST request;
+	IOCTL_COMMON_ANON_196_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_194_PARAMS, *PIOCTL_COMMON_ANON_194_PARAMS;
+
+/*
+ *  IOCTL to modify select attributes of a completion queue without needing
+ *  to destroy and  create a new one.
+ */
+typedef struct _IOCTL_COMMON_CQ_MODIFY {
+	IOCTL_HEADER header;
+	IOCTL_COMMON_ANON_194_PARAMS params;
+} SG_PACK IOCTL_COMMON_CQ_MODIFY, *PIOCTL_COMMON_CQ_MODIFY;
+
+typedef struct _IOCTL_COMMON_ANON_198_REQUEST {
+	u16 num_pages;
+	u16 rsvd0;
+	EQ_CONTEXT context;
+	PHYS_ADDR pages[8];
+} SG_PACK IOCTL_COMMON_ANON_198_REQUEST, *PIOCTL_COMMON_ANON_198_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_199_RESPONSE {
+	u16 eq_id;
+} SG_PACK IOCTL_COMMON_ANON_199_RESPONSE, *PIOCTL_COMMON_ANON_199_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_197_PARAMS {
+	IOCTL_COMMON_ANON_198_REQUEST request;
+	IOCTL_COMMON_ANON_199_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_197_PARAMS, *PIOCTL_COMMON_ANON_197_PARAMS;
+
+/*
+ *  IOCTL for creating a event queue. An Event Queue must span at least
+ *  1 page and at most  8 pages. The number of pages posted must contain
+ *  the EQ ring. The ring is defined by  the size of the EQ entries (encoded
+ *  in the context) and the number of EQ entries (also  encoded in the
+ *  context).
+ */
+typedef struct _IOCTL_COMMON_EQ_CREATE {
+	IOCTL_HEADER header;
+	IOCTL_COMMON_ANON_197_PARAMS params;
+} SG_PACK IOCTL_COMMON_EQ_CREATE, *PIOCTL_COMMON_EQ_CREATE;
+
+typedef struct _IOCTL_COMMON_ANON_201_REQUEST {
+	u16 cq_id;
+	u16 bcmc_cq_id;
+	u16 num_pages;
+	u16 rsvd0;
+	PHYS_ADDR pages[2];
+} SG_PACK IOCTL_COMMON_ANON_201_REQUEST, *PIOCTL_COMMON_ANON_201_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_202_RESPONSE {
+	u16 id;
+} SG_PACK IOCTL_COMMON_ANON_202_RESPONSE, *PIOCTL_COMMON_ANON_202_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_200_PARAMS {
+	IOCTL_COMMON_ANON_201_REQUEST request;
+	IOCTL_COMMON_ANON_202_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_200_PARAMS, *PIOCTL_COMMON_ANON_200_PARAMS;
+
+/*
+ *  IOCTL for creating Ethernet receive ring.  An ERX ring contains ETH_RX_D
+ *  entries (8  bytes each). An ERX ring must be 1024 entries deep
+ *  (corresponding to 2 pages).
+ */
+typedef struct _IOCTL_COMMON_ETH_RX_CREATE {
+	IOCTL_HEADER header;
+	IOCTL_COMMON_ANON_200_PARAMS params;
+} SG_PACK IOCTL_COMMON_ETH_RX_CREATE, *PIOCTL_COMMON_ETH_RX_CREATE;
+
+typedef struct _IOCTL_COMMON_ANON_204_REQUEST {
+	u16 num_pages;
+	u8 ulp_num;
+	u8 type;
+	ETX_CONTEXT context;
+	PHYS_ADDR pages[8];
+} SG_PACK IOCTL_COMMON_ANON_204_REQUEST, *PIOCTL_COMMON_ANON_204_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_205_RESPONSE {
+	u16 cid;
+	u8 ulp_num;
+	u8 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_205_RESPONSE, *PIOCTL_COMMON_ANON_205_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_203_PARAMS {
+	IOCTL_COMMON_ANON_204_REQUEST request;
+	IOCTL_COMMON_ANON_205_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_203_PARAMS, *PIOCTL_COMMON_ANON_203_PARAMS;
+
+/*
+ *  IOCTL for creating an Ethernet transmit ring.  An ETX ring contains
+ *  ETH_WRB entries (16  bytes each). An ETX ring must be at least 256
+ *  entries deep (corresponding to 1 page)  and at most 2k entries deep
+ *  (corresponding to 8 pages).
+ */
+typedef struct _IOCTL_COMMON_ETH_TX_CREATE {
+	IOCTL_HEADER header;
+	IOCTL_COMMON_ANON_203_PARAMS params;
+} SG_PACK IOCTL_COMMON_ETH_TX_CREATE, *PIOCTL_COMMON_ETH_TX_CREATE;
+
+typedef struct _IOCTL_COMMON_ANON_207_REQUEST {
+	u16 num_pages;
+	u16 rsvd0;
+	ISCSI_DEFAULT_PDU_CONTEXT context;
+	PHYS_ADDR pages[8];
+} SG_PACK IOCTL_COMMON_ANON_207_REQUEST, *PIOCTL_COMMON_ANON_207_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_208_RESPONSE {
+	u16 id;
+} SG_PACK IOCTL_COMMON_ANON_208_RESPONSE, *PIOCTL_COMMON_ANON_208_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_206_PARAMS {
+	IOCTL_COMMON_ANON_207_REQUEST request;
+	IOCTL_COMMON_ANON_208_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_206_PARAMS, *PIOCTL_COMMON_ANON_206_PARAMS;
+
+/*
+ *  IOCTL for creating iSCSI default PDU ring. Use opcode
+ *  OPCODE_COMMON_ISCSI_DEFQ_CREATE.
+ *    An iSCSI default PDU ring must be at least 512 entries deep (corresponding
+ *  to 1 page)  and at most 4k entries deep (corresponding to 8 pages).
+ *
+ */
+typedef struct _IOCTL_COMMON_ISCSI_DEFQ_CREATE {
+	IOCTL_HEADER header;
+	IOCTL_COMMON_ANON_206_PARAMS params;
+} SG_PACK IOCTL_COMMON_ISCSI_DEFQ_CREATE, *PIOCTL_COMMON_ISCSI_DEFQ_CREATE;
+
+typedef struct _IOCTL_COMMON_ANON_210_REQUEST {
+	u16 num_pages;
+	u16 rsvd0;
+	PHYS_ADDR pages[8];
+} SG_PACK IOCTL_COMMON_ANON_210_REQUEST, *PIOCTL_COMMON_ANON_210_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_211_RESPONSE {
+	u16 cid;
+} SG_PACK IOCTL_COMMON_ANON_211_RESPONSE, *PIOCTL_COMMON_ANON_211_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_209_PARAMS {
+	IOCTL_COMMON_ANON_210_REQUEST request;
+	IOCTL_COMMON_ANON_211_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_209_PARAMS, *PIOCTL_COMMON_ANON_209_PARAMS;
+
+/*
+ *  IOCTL for creating iSCSI WRB ring. An iSCSI WRB (transmit) ring must
+ *  be at least 128  entries deep (corresponding to 1 page) and at most
+ *  2k entries deep (corresponding to 4  pages). When the connection
+ *  is offloaded, the encoded ring size in the context must  result in
+ *  a ring fitting within the number of pages posted with this IOCTL.
+ *
+ */
+typedef struct _IOCTL_COMMON_ISCSI_WRBQ_CREATE {
+	IOCTL_HEADER header;
+	IOCTL_COMMON_ANON_209_PARAMS params;
+} SG_PACK IOCTL_COMMON_ISCSI_WRBQ_CREATE, *PIOCTL_COMMON_ISCSI_WRBQ_CREATE;
+
+typedef struct _IOCTL_COMMON_ANON_213_REQUEST {
+	u16 num_pages;
+	u16 rsvd0;
+	u32 rsvd1[16];		/* DWORDS 1 to 16 */
+	PHYS_ADDR pages[8];
+} SG_PACK IOCTL_COMMON_ANON_213_REQUEST, *PIOCTL_COMMON_ANON_213_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_214_RESPONSE {
+	u16 id;
+} SG_PACK IOCTL_COMMON_ANON_214_RESPONSE, *PIOCTL_COMMON_ANON_214_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_212_PARAMS {
+	IOCTL_COMMON_ANON_213_REQUEST request;
+	IOCTL_COMMON_ANON_214_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_212_PARAMS, *PIOCTL_COMMON_ANON_212_PARAMS;
+
+typedef struct _IOCTL_COMMON_ANON_216_REQUEST {
+	u16 num_pages;
+	u16 rsvd0;
+	PHYS_ADDR pages[8];
+} SG_PACK IOCTL_COMMON_ANON_216_REQUEST, *PIOCTL_COMMON_ANON_216_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_217_RESPONSE {
+	u16 cid;
+} SG_PACK IOCTL_COMMON_ANON_217_RESPONSE, *PIOCTL_COMMON_ANON_217_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_215_PARAMS {
+	IOCTL_COMMON_ANON_216_REQUEST request;
+	IOCTL_COMMON_ANON_217_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_215_PARAMS, *PIOCTL_COMMON_ANON_215_PARAMS;
+
+typedef struct _IOCTL_COMMON_ANON_222_REQUEST {
+	u16 num_pages;
+	u16 rsvd0;
+	MCC_RING_CONTEXT context;
+	PHYS_ADDR pages[8];
+} SG_PACK IOCTL_COMMON_ANON_222_REQUEST, *PIOCTL_COMMON_ANON_222_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_223_RESPONSE {
+	u16 id;
+} SG_PACK IOCTL_COMMON_ANON_223_RESPONSE, *PIOCTL_COMMON_ANON_223_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_221_PARAMS {
+	IOCTL_COMMON_ANON_222_REQUEST request;
+	IOCTL_COMMON_ANON_223_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_221_PARAMS, *PIOCTL_COMMON_ANON_221_PARAMS;
+
+/*
+ *  IOCTL for creating the MCC ring. An MCC ring must be at least 16
+ *  entries deep  (corresponding to 1 page) and at most 128 entries deep
+ *  (corresponding to 8 pages).
+ */
+typedef struct _IOCTL_COMMON_MCC_CREATE {
+	IOCTL_HEADER header;
+	IOCTL_COMMON_ANON_221_PARAMS params;
+} SG_PACK IOCTL_COMMON_MCC_CREATE, *PIOCTL_COMMON_MCC_CREATE;
+
+typedef struct _IOCTL_COMMON_ANON_225_REQUEST {
+	PHYS_ADDR page;
+} SG_PACK IOCTL_COMMON_ANON_225_REQUEST, *PIOCTL_COMMON_ANON_225_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_226_RESPONSE {
+	u32 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_226_RESPONSE, *PIOCTL_COMMON_ANON_226_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_224_PARAMS {
+	IOCTL_COMMON_ANON_225_REQUEST request;
+	IOCTL_COMMON_ANON_226_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_224_PARAMS, *PIOCTL_COMMON_ANON_224_PARAMS;
+
+/*
+ *  Posts a physical address pointing to a single byte of zero data that
+ *  may be DMA'd.
+ */
+typedef struct _IOCTL_COMMON_POST_ZERO_BUFFER {
+	IOCTL_HEADER header;
+	IOCTL_COMMON_ANON_224_PARAMS params;
+} SG_PACK IOCTL_COMMON_POST_ZERO_BUFFER, *PIOCTL_COMMON_POST_ZERO_BUFFER;
+
+typedef struct _IOCTL_COMMON_ANON_228_REQUEST {
+	u8 free_jell;
+	u8 ddr;
+	u8 done;
+	u8 rsvd0;
+	u16 page_offset;
+	u16 num_pages;
+	PHYS_ADDR pages[26];
+} SG_PACK IOCTL_COMMON_ANON_228_REQUEST, *PIOCTL_COMMON_ANON_228_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_229_RESPONSE {
+	u32 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_229_RESPONSE, *PIOCTL_COMMON_ANON_229_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_227_PARAMS {
+	IOCTL_COMMON_ANON_228_REQUEST request;
+	IOCTL_COMMON_ANON_229_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_227_PARAMS, *PIOCTL_COMMON_ANON_227_PARAMS;
+
+/*
+ *  Configures the JELL -- the journal entry linked list required for
+ *  any TCP offload. This  may also free a previously configured JELL.
+ *
+ */
+typedef struct _IOCTL_COMMON_JELL_CONFIG {
+	IOCTL_HEADER header;
+	IOCTL_COMMON_ANON_227_PARAMS params;
+} SG_PACK IOCTL_COMMON_JELL_CONFIG, *PIOCTL_COMMON_JELL_CONFIG;
+
+typedef struct _GET_QOS_IN {
+	u32 qos_params_rsvd;
+} SG_PACK GET_QOS_IN, *PGET_QOS_IN;
+
+typedef struct _GET_QOS_OUT {
+	u32 max_bits_per_second_NIC;
+	u32 max_packets_per_second_NIC;
+	u32 max_ios_per_second_iSCSI;
+	u32 max_bytes_per_second_iSCSI;
+	u16 domain_VLAN_tag;
+	u16 fabric_domain_ID;
+	u32 qos_params_oem[4];
+} SG_PACK GET_QOS_OUT, *PGET_QOS_OUT;
+
+typedef union _GET_QOS_PARAMS {
+	GET_QOS_IN request;
+	GET_QOS_OUT response;
+} SG_PACK GET_QOS_PARAMS, *PGET_QOS_PARAMS;
+
+/* QOS/Bandwidth settings per domain. Applicable only in VMs.  */
+typedef struct _IOCTL_COMMON_GET_QOS {
+	IOCTL_HEADER header;
+	GET_QOS_PARAMS params;
+} SG_PACK IOCTL_COMMON_GET_QOS, *PIOCTL_COMMON_GET_QOS;
+
+typedef struct _SET_QOS_IN {
+	u32 valid_flags;
+	u32 max_bits_per_second_NIC;
+	u32 max_packets_per_second_NIC;
+	u32 max_ios_per_second_iSCSI;
+	u32 max_bytes_per_second_iSCSI;
+	u16 domain_VLAN_tag;
+	u16 fabric_domain_ID;
+	u32 qos_params_oem[4];
+} SG_PACK SET_QOS_IN, *PSET_QOS_IN;
+
+typedef struct _SET_QOS_OUT {
+	u32 qos_params_rsvd;
+} SG_PACK SET_QOS_OUT, *PSET_QOS_OUT;
+
+typedef union _SET_QOS_PARAMS {
+	SET_QOS_IN request;
+	SET_QOS_OUT response;
+} SG_PACK SET_QOS_PARAMS, *PSET_QOS_PARAMS;
+
+/* QOS/Bandwidth settings per domain. Applicable only in VMs.  */
+typedef struct _IOCTL_COMMON_SET_QOS {
+	IOCTL_HEADER header;
+	SET_QOS_PARAMS params;
+} SG_PACK IOCTL_COMMON_SET_QOS, *PIOCTL_COMMON_SET_QOS;
+
+typedef struct _SET_FRAME_SIZE_IN {
+	u32 max_tx_frame_size;
+	u32 max_rx_frame_size;
+} SG_PACK SET_FRAME_SIZE_IN, *PSET_FRAME_SIZE_IN;
+
+typedef struct _SET_FRAME_SIZE_OUT {
+	u32 chip_max_tx_frame_size;
+	u32 chip_max_rx_frame_size;
+} SG_PACK SET_FRAME_SIZE_OUT, *PSET_FRAME_SIZE_OUT;
+
+typedef union _SET_FRAME_SIZE_PARAMS {
+	SET_FRAME_SIZE_IN request;
+	SET_FRAME_SIZE_OUT response;
+} SG_PACK SET_FRAME_SIZE_PARAMS, *PSET_FRAME_SIZE_PARAMS;
+
+/* Set frame size IOCTL. Only host domain may issue this IOCTL.  */
+typedef struct _IOCTL_COMMON_SET_FRAME_SIZE {
+	IOCTL_HEADER header;
+	SET_FRAME_SIZE_PARAMS params;
+} SG_PACK IOCTL_COMMON_SET_FRAME_SIZE, *PIOCTL_COMMON_SET_FRAME_SIZE;
+
+typedef struct _FORCE_FAILOVER_IN {
+	u32 move_to_port;
+	u32 failover_config;
+} SG_PACK FORCE_FAILOVER_IN, *PFORCE_FAILOVER_IN;
+
+typedef struct _IOCTL_COMMON_ANON_231_RESPONSE {
+	u32 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_231_RESPONSE, *PIOCTL_COMMON_ANON_231_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_230_PARAMS {
+	FORCE_FAILOVER_IN request;
+	IOCTL_COMMON_ANON_231_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_230_PARAMS, *PIOCTL_COMMON_ANON_230_PARAMS;
+
+/*
+ *  Use this IOCTL to control failover in BladeEngine. It may be used
+ *  to failback to a  restored port or to forcibly move traffic from
+ *  one port to another. It may also be used  to enable or disable the
+ *  automatic failover feature. This IOCTL can only be issued by  domain
+ *  0.
+ */
+typedef struct _IOCTL_COMMON_FORCE_FAILOVER {
+	IOCTL_HEADER header;
+	IOCTL_COMMON_ANON_230_PARAMS params;
+} SG_PACK IOCTL_COMMON_FORCE_FAILOVER, *PIOCTL_COMMON_FORCE_FAILOVER;
+
+typedef struct _QUERY_MAX_IOCTL_BUFFER_SIZE_PARAMS_OUT {
+	u32 max_ioctl_buffer_size;
+} SG_PACK QUERY_MAX_IOCTL_BUFFER_SIZE_PARAMS_OUT,
+    *PQUERY_MAX_IOCTL_BUFFER_SIZE_PARAMS_OUT;
+
+/*
+ *  IOCTL_QUERY_MAX_IOCTL_BUFFER_SIZE MILI uses this IOCTL to find out
+ *  the maximum buffer  size that can be accepted by the host OS or the
+ *  OSM. During MILI initialization, MILI  should send this IOCTL to
+ *  find out the maximum IOCTL buffer size allowed. For all the  IOCTLs
+ *  in the future, MILI should not allocate a buffer larger than this
+ *  value. In  Windows, the OS doesn't deliver the IOCTL request when
+ *  the buffer size allocated by  MILI is larger than the maximum I/O
+ *  size allowed by OSM.
+ */
+typedef struct _IOCTL_COMMON_QUERY_MAX_IOCTL_BUFFER_SIZE {
+	IOCTL_HEADER header;
+	QUERY_MAX_IOCTL_BUFFER_SIZE_PARAMS_OUT response;
+} SG_PACK IOCTL_COMMON_QUERY_MAX_IOCTL_BUFFER_SIZE,
+    *PIOCTL_COMMON_QUERY_MAX_IOCTL_BUFFER_SIZE;
+
+typedef struct _FLASHROM_PARAMS {
+	u32 op_code;
+	u32 op_type;
+	u32 data_buffer_size;
+	u32 offset;
+	u8 data_buffer[4];
+} SG_PACK FLASHROM_PARAMS, *PFLASHROM_PARAMS;
+
+typedef struct _IOCTL_COMMON_FLASHROM {
+	IOCTL_HEADER header;
+	FLASHROM_PARAMS params;
+} SG_PACK IOCTL_COMMON_FLASHROM, *PIOCTL_COMMON_FLASHROM;
+
+typedef IOCTL_COMMON_FLASHROM IOCTL_COMMON_READ_FLASHROM;
+
+typedef IOCTL_COMMON_FLASHROM *PIOCTL_COMMON_READ_FLASHROM;
+
+typedef IOCTL_COMMON_FLASHROM IOCTL_COMMON_WRITE_FLASHROM;
+
+typedef IOCTL_COMMON_FLASHROM *PIOCTL_COMMON_WRITE_FLASHROM;
+
+typedef struct _FLASH_ROM_INFO {
+	u8 manuf_code;
+	u8 device_code;
+	u8 id[3];
+	u8 device_size;
+	u8 device_interface[2];
+	u8 buffer_size[2];
+	u8 is_block_oriented;
+	u8 num_regions[2];
+	u8 region_size[2];
+} SG_PACK FLASH_ROM_INFO, *PFLASH_ROM_INFO;
+
+typedef struct _SEEPROM_DATA {
+	u32 jmp_addr_for_ISM;
+	u8 seeprom_version[2];
+	u8 supported_modes;
+	u8 max_domains_supported;
+	u8 storage_MAC0_port0[6];
+	u8 storage_MAC1_port0[6];
+	u8 storage_MAC0_port1[6];
+	u8 storage_MAC1_port1[6];
+	u8 ntwk_MAC0_port0[6];
+	u8 ntwk_MAC1_port0[6];
+	u8 ntwk_MAC0_port1[6];
+	u8 ntwk_MAC1_port1[6];
+	u8 ntwk_MAC_VMs[186];
+	u8 mgmt_MAC[6];
+	u8 flash_ROM_type;
+	u8 flash_ROM_size;
+	FLASH_ROM_INFO flash_cfi_data;
+	u8 DDR_type;
+	u8 DDR_size;
+	u8 DDR_mode;
+	u8 xml_config;
+	u8 interface_10Gb_type;
+	u16 max_iscsi_sessions;
+	u8 rsvd0[44];
+	u8 rsvd1[4];
+	u32 emph_lev_sel_port0;
+	u32 emph_lev_sel_port1;
+	u8 xaui_vo_sel;
+	u8 xaui_state;
+	u16 rsvd2;
+	u32 xaui_eq_vector;
+	u32 hba_mtu;
+	u8 vld_mode;
+	u8 pad[171];
+	u8 ism_code[508];
+	u32 digest;
+} SG_PACK SEEPROM_DATA, *PSEEPROM_DATA;
+
+typedef struct _SEEPROM_READ_PARAMS_OUT {
+	SEEPROM_DATA seeprom_data;
+} SG_PACK SEEPROM_READ_PARAMS_OUT, *PSEEPROM_READ_PARAMS_OUT;
+
+typedef union _SEEPROM_READ_PARAMS {
+	SEEPROM_READ_PARAMS_OUT response;
+} SG_PACK SEEPROM_READ_PARAMS, *PSEEPROM_READ_PARAMS;
+
+/*
+ *  Use this IOCTL to retrieve BE HBA/instance specific information
+ *  - Functionality (or  combinations of functions) supported (NIC/iSCSI/VM/RDMA
+ *  etc.)  - Manufacturer  assigned MAC addresses for the various functions
+ *   - Flash ROM type and size
+ */
+typedef struct _IOCTL_COMMON_SEEPROM_READ {
+	IOCTL_HEADER header;
+	SEEPROM_READ_PARAMS params;
+} SG_PACK IOCTL_COMMON_SEEPROM_READ, *PIOCTL_COMMON_SEEPROM_READ;
+
+typedef struct _BE_TCP_STATS {
+	u32 rsvd0[256];		/* DWORDS 0 to 255 */
+	u32 rsvd1[256];		/* DWORDS 256 to 511 */
+} SG_PACK BE_TCP_STATS, *PBE_TCP_STATS;
+
+typedef struct _IOCTL_COMMON_ANON_232_REQUEST {
+	u32 rsvd0[1];		/* DWORDS 0 to 0 */
+} SG_PACK IOCTL_COMMON_ANON_232_REQUEST, *PIOCTL_COMMON_ANON_232_REQUEST;
+
+typedef union _TCP_GET_STATISTICS_PARAMS {
+	BE_TCP_STATS response;
+	IOCTL_COMMON_ANON_232_REQUEST request;
+} SG_PACK TCP_GET_STATISTICS_PARAMS, *PTCP_GET_STATISTICS_PARAMS;
+
+typedef struct _IOCTL_COMMON_TCP_GET_STATISTICS {
+	IOCTL_HEADER header;
+	TCP_GET_STATISTICS_PARAMS params;
+} SG_PACK IOCTL_COMMON_TCP_GET_STATISTICS,
+    *PIOCTL_COMMON_TCP_GET_STATISTICS;
+
+typedef struct _IOCTL_COMMON_ANON_234_RESPONSE {
+	u32 rsvd0[32];		/* DWORDS 0 to 31 */
+} SG_PACK IOCTL_COMMON_ANON_234_RESPONSE, *PIOCTL_COMMON_ANON_234_RESPONSE;
+
+typedef struct _IOCTL_COMMON_ANON_235_REQUEST {
+	u32 cid;
+} SG_PACK IOCTL_COMMON_ANON_235_REQUEST, *PIOCTL_COMMON_ANON_235_REQUEST;
+
+typedef union _IOCTL_COMMON_ANON_233_PARAMS {
+	IOCTL_COMMON_ANON_234_RESPONSE response;
+	IOCTL_COMMON_ANON_235_REQUEST request;
+} SG_PACK IOCTL_COMMON_ANON_233_PARAMS, *PIOCTL_COMMON_ANON_233_PARAMS;
+
+/* Queries the TCP state of a given connection.  */
+typedef struct _IOCTL_COMMON_TCP_STATE_QUERY {
+	IOCTL_HEADER header;
+	IOCTL_COMMON_ANON_233_PARAMS params;
+} SG_PACK IOCTL_COMMON_TCP_STATE_QUERY, *PIOCTL_COMMON_TCP_STATE_QUERY;
+
+typedef struct _IOCTL_COMMON_ANON_237_REQUEST {
+	u32 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_237_REQUEST, *PIOCTL_COMMON_ANON_237_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_238_RESPONSE {
+	MGMT_CONTROLLER_ATTRIBUTES cntl_attributes_info;
+} SG_PACK IOCTL_COMMON_ANON_238_RESPONSE, *PIOCTL_COMMON_ANON_238_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_236_PARAMS {
+	IOCTL_COMMON_ANON_237_REQUEST request;
+	IOCTL_COMMON_ANON_238_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_236_PARAMS, *PIOCTL_COMMON_ANON_236_PARAMS;
+
+/*
+ *  This ioctl queries the controller information from the Flash ROM.
+ *  This is required for  management applications and BIOS to display
+ *  this information to the users.
+ */
+typedef struct _IOCTL_COMMON_GET_CNTL_ATTRIBUTES {
+	IOCTL_HEADER header;
+	IOCTL_COMMON_ANON_236_PARAMS params;
+} SG_PACK IOCTL_COMMON_GET_CNTL_ATTRIBUTES,
+    *PIOCTL_COMMON_GET_CNTL_ATTRIBUTES;
+
+typedef struct _IOCTL_COMMON_ANON_240_REQUEST {
+	u64 context;
+} SG_PACK IOCTL_COMMON_ANON_240_REQUEST, *PIOCTL_COMMON_ANON_240_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_241_RESPONSE {
+	u64 context;
+} SG_PACK IOCTL_COMMON_ANON_241_RESPONSE, *PIOCTL_COMMON_ANON_241_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_239_PARAMS {
+	IOCTL_COMMON_ANON_240_REQUEST request;
+	IOCTL_COMMON_ANON_241_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_239_PARAMS, *PIOCTL_COMMON_ANON_239_PARAMS;
+
+/*
+ *  This ioctl can be used by clients as a no-operation request. Typical
+ *  uses for drivers  are as a heartbeat mechanism, or deferred processing
+ *  catalyst. The ARM will always  complete this IOCTL with a good completion.
+ *  The 64-bit parameter is not touched by the  ARM processor.
+ */
+typedef struct _IOCTL_COMMON_NOP {
+	IOCTL_HEADER header;
+	IOCTL_COMMON_ANON_239_PARAMS params;
+} SG_PACK IOCTL_COMMON_NOP, *PIOCTL_COMMON_NOP;
+
+typedef struct _NTWK_RX_FILTER_SETTINGS {
+	u8 promiscuous;
+	u8 ip_cksum;
+	u8 tcp_cksum;
+	u8 udp_cksum;
+	u8 pass_err;
+	u8 pass_ckerr;
+	u8 strip_crc;
+	u8 mcast_en;
+	u8 bcast_en;
+	u8 mcast_promiscuous_en;
+	u8 unicast_en;
+	u8 vlan_promiscuous;
+} SG_PACK NTWK_RX_FILTER_SETTINGS, *PNTWK_RX_FILTER_SETTINGS;
+
+typedef union _IOCTL_COMMON_ANON_242_PARAMS {
+	NTWK_RX_FILTER_SETTINGS request;
+	NTWK_RX_FILTER_SETTINGS response;
+} SG_PACK IOCTL_COMMON_ANON_242_PARAMS, *PIOCTL_COMMON_ANON_242_PARAMS;
+
+/*
+ *  This IOCTL is used to modify the ethernet receive filter configuration.
+ *  Only domain 0  network function drivers may issue this IOCTL. The
+ *  applied configuration is returned in  the response payload. Note:
+ *  Some receive packet filter settings are global on  BladeEngine and
+ *  can affect both the storage and network function clients that the
+ *   BladeEngine hardware and firmware serve. Additionaly, depending
+ *  on the revision of  BladeEngine, some ethernet receive filter settings
+ *  are dependent on others. If a  dependency exists between settings
+ *  for the BladeEngine revision, and the IOCTL request  settings do
+ *  not meet the dependency requirement, the invalid settings will not
+ *  be  applied despite the IOCTL succeeding. For example: a driver may
+ *  request to enable  broadcast packets, but not enable multicast packets.
+ *  On early revisions of BladeEngine,  there may be no distinction between
+ *  broadcast and multicast filters, so broadcast could  not be enabled
+ *  without enabling multicast. In this scenario, the IOCTL would still
+ *   succeed, but the response payload would indicate the previously
+ *  configured broadcast  and multicast setting.
+ */
+typedef struct _IOCTL_COMMON_NTWK_RX_FILTER {
+	IOCTL_HEADER header;
+	IOCTL_COMMON_ANON_242_PARAMS params;
+} SG_PACK IOCTL_COMMON_NTWK_RX_FILTER, *PIOCTL_COMMON_NTWK_RX_FILTER;
+
+typedef struct _IOCTL_COMMON_ANON_244_REQUEST {
+	u32 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_244_REQUEST, *PIOCTL_COMMON_ANON_244_REQUEST;
+
+typedef struct _IOCTL_COMMON_GET_FW_VERSION_RESPONSE_PAYLOAD {
+	u8 firmware_version_string[32];
+	u8 fw_on_flash_version_string[32];
+} SG_PACK IOCTL_COMMON_GET_FW_VERSION_RESPONSE_PAYLOAD,
+    *PIOCTL_COMMON_GET_FW_VERSION_RESPONSE_PAYLOAD;
+
+typedef union _IOCTL_COMMON_ANON_243_PARAMS {
+	IOCTL_COMMON_ANON_244_REQUEST request;
+	IOCTL_COMMON_GET_FW_VERSION_RESPONSE_PAYLOAD response;
+} SG_PACK IOCTL_COMMON_ANON_243_PARAMS, *PIOCTL_COMMON_ANON_243_PARAMS;
+
+/* This IOCTL retrieves the firmware version.  */
+typedef struct _IOCTL_COMMON_GET_FW_VERSION {
+	IOCTL_HEADER header;
+	IOCTL_COMMON_ANON_243_PARAMS params;
+} SG_PACK IOCTL_COMMON_GET_FW_VERSION, *PIOCTL_COMMON_GET_FW_VERSION;
+
+typedef struct _IOCTL_COMMON_ANON_246_REQUEST {
+	u16 tx_flow_control;
+	u16 rx_flow_control;
+} SG_PACK IOCTL_COMMON_ANON_246_REQUEST, *PIOCTL_COMMON_ANON_246_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_247_RESPONSE {
+	u32 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_247_RESPONSE, *PIOCTL_COMMON_ANON_247_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_245_PARAMS {
+	IOCTL_COMMON_ANON_246_REQUEST request;
+	IOCTL_COMMON_ANON_247_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_245_PARAMS, *PIOCTL_COMMON_ANON_245_PARAMS;
+
+/*
+ *  This IOCTL is used to program BladeEngine flow control behavior.
+ *  Only the host  networking driver is allowed to use this IOCTL.
+ */
+typedef struct _IOCTL_COMMON_SET_FLOW_CONTROL {
+	IOCTL_HEADER header;
+	IOCTL_COMMON_ANON_245_PARAMS params;
+} SG_PACK IOCTL_COMMON_SET_FLOW_CONTROL, *PIOCTL_COMMON_SET_FLOW_CONTROL;
+
+typedef struct _IOCTL_COMMON_ANON_249_REQUEST {
+	u32 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_249_REQUEST, *PIOCTL_COMMON_ANON_249_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_250_RESPONSE {
+	u16 tx_flow_control;
+	u16 rx_flow_control;
+} SG_PACK IOCTL_COMMON_ANON_250_RESPONSE, *PIOCTL_COMMON_ANON_250_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_248_PARAMS {
+	IOCTL_COMMON_ANON_249_REQUEST request;
+	IOCTL_COMMON_ANON_250_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_248_PARAMS, *PIOCTL_COMMON_ANON_248_PARAMS;
+
+/* This IOCTL is used to read BladeEngine flow control settings.  */
+typedef struct _IOCTL_COMMON_GET_FLOW_CONTROL {
+	IOCTL_HEADER header;
+	IOCTL_COMMON_ANON_248_PARAMS params;
+} SG_PACK IOCTL_COMMON_GET_FLOW_CONTROL, *PIOCTL_COMMON_GET_FLOW_CONTROL;
+
+typedef struct _BE_DRIVER_TCP_PARAMETERS {
+	u32 fin_wait2_ms;
+	u32 push_timer_ms;
+	u32 delayed_ack_ms;
+	u32 idle_ms;
+	u32 sws_prevention_ms;
+	u32 dup_ack_threshold;
+	u32 max_warning_count;
+	u32 max_rxmt_count;
+	u32 ack_frequency;
+	u32 rsvd0[2];
+} SG_PACK BE_DRIVER_TCP_PARAMETERS, *PBE_DRIVER_TCP_PARAMETERS;
+
+typedef struct _IOCTL_COMMON_ANON_252_REQUEST {
+	u32 ulp_mask;
+	BE_DRIVER_TCP_PARAMETERS tcp_params;
+} SG_PACK IOCTL_COMMON_ANON_252_REQUEST, *PIOCTL_COMMON_ANON_252_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_253_RESPONSE {
+	u32 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_253_RESPONSE, *PIOCTL_COMMON_ANON_253_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_251_PARAMS {
+	IOCTL_COMMON_ANON_252_REQUEST request;
+	IOCTL_COMMON_ANON_253_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_251_PARAMS, *PIOCTL_COMMON_ANON_251_PARAMS;
+
+/*
+ *  This IOCTL sets the global TCP parameters for offloaded connections.
+ *  Only host device  drivers are allowed to set these.
+ */
+typedef struct _IOCTL_COMMON_SET_TCP_PARAMETERS {
+	IOCTL_HEADER header;
+	IOCTL_COMMON_ANON_251_PARAMS params;
+} SG_PACK IOCTL_COMMON_SET_TCP_PARAMETERS,
+    *PIOCTL_COMMON_SET_TCP_PARAMETERS;
+
+typedef struct _IOCTL_COMMON_ANON_255_REQUEST {
+	u8 clear_log;
+	u8 num_pages;
+	u16 page_offset;
+	PHYS_ADDR buffer_addr[27];
+} SG_PACK IOCTL_COMMON_ANON_255_REQUEST, *PIOCTL_COMMON_ANON_255_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_256_RESPONSE {
+	u32 log_size;
+	u32 bytes_transferred;
+} SG_PACK IOCTL_COMMON_ANON_256_RESPONSE, *PIOCTL_COMMON_ANON_256_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_254_PARAMS {
+	IOCTL_COMMON_ANON_255_REQUEST request;
+	IOCTL_COMMON_ANON_256_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_254_PARAMS, *PIOCTL_COMMON_ANON_254_PARAMS;
+
+/*
+ *  This IOCTL retrieves a Fault Analaysis Tool (FAT) log. The log data
+ *  can be anaylzed by  BladeEngine support tools to diagnose faults.
+ *  Only host domains may issue this IOCTL.
+ */
+typedef struct _IOCTL_COMMON_GET_FAT {
+	IOCTL_HEADER header;
+	IOCTL_COMMON_ANON_254_PARAMS params;
+} SG_PACK IOCTL_COMMON_GET_FAT, *PIOCTL_COMMON_GET_FAT;
+
+typedef struct _ENABLE_DISABLE_DOMAINS_PARAMS_IN {
+	u8 domain_function;
+	u8 enable_disable;
+	u16 rsvd0;
+} SG_PACK ENABLE_DISABLE_DOMAINS_PARAMS_IN,
+    *PENABLE_DISABLE_DOMAINS_PARAMS_IN;
+
+typedef struct _ENABLE_DISABLE_DOMAINS_PARAMS_OUT {
+	u32 rsvd0;
+} SG_PACK ENABLE_DISABLE_DOMAINS_PARAMS_OUT,
+    *PENABLE_DISABLE_DOMAINS_PARAMS_OUT;
+
+typedef union _ENABLE_DISABLE_DOMAINS_PARAMS {
+	ENABLE_DISABLE_DOMAINS_PARAMS_IN request;
+	ENABLE_DISABLE_DOMAINS_PARAMS_OUT response;
+} SG_PACK ENABLE_DISABLE_DOMAINS_PARAMS, *PENABLE_DISABLE_DOMAINS_PARAMS;
+
+/*
+ *  This IOCTL enables or disables a domain for NIC or iSCSI functionality.
+ *  If a  particular domain is enabled, management utilities like SMCLP
+ *  expose a logicalHBA to  the user allowing the QoS, iSCSI (iqn) name
+ *  etc to be set for that domain. The domain  number is specified in
+ *  the IOCTL_HEADER. This IOCTL can only originate from domain 0.  <break>
+ *  This IOCTL may return one of the following status values in the response
+ *   -  MGMT_STATUS_SUCCESS  - MGMT_STATUS_FAILED with additional status
+ *  set to  MGMT_ADDI_STATUS_INVALID_DOMAIN
+ */
+typedef struct _IOCTL_COMMON_ENABLE_DISABLE_DOMAINS {
+	IOCTL_HEADER header;
+	ENABLE_DISABLE_DOMAINS_PARAMS params;
+} SG_PACK IOCTL_COMMON_ENABLE_DISABLE_DOMAINS,
+    *PIOCTL_COMMON_ENABLE_DISABLE_DOMAINS;
+
+typedef struct _GET_DOMAIN_CONFIG_PARAMS_IN {
+	u8 domain_function;
+	u8 enable_disable;
+	u16 rsvd0;
+} SG_PACK GET_DOMAIN_CONFIG_PARAMS_IN, *PGET_DOMAIN_CONFIG_PARAMS_IN;
+
+typedef struct _GET_DOMAIN_CONFIG_PARAMS_OUT {
+	u32 domain_bitmap;
+} SG_PACK GET_DOMAIN_CONFIG_PARAMS_OUT, *PGET_DOMAIN_CONFIG_PARAMS_OUT;
+
+typedef union _GET_DOMAIN_CONFIG_PARAMS {
+	GET_DOMAIN_CONFIG_PARAMS_IN request;
+	GET_DOMAIN_CONFIG_PARAMS_OUT response;
+} SG_PACK GET_DOMAIN_CONFIG_PARAMS, *PGET_DOMAIN_CONFIG_PARAMS;
+
+/*
+ *  This IOCTL returns a bitmap indicating the current status of the
+ *  NIC or iSCSI  functionality for all the domains supported on a given
+ *  BladeEngine. The domain number  in the IOCTL header is ignored. This
+ *  IOCTL can only originate from domain 0. This IOCTL  will always return
+ *  MGMT_STATUS_SUCCESS
+ */
+typedef struct _IOCTL_COMMON_GET_DOMAIN_CONFIG {
+	IOCTL_HEADER header;
+	GET_DOMAIN_CONFIG_PARAMS params;
+} SG_PACK IOCTL_COMMON_GET_DOMAIN_CONFIG, *PIOCTL_COMMON_GET_DOMAIN_CONFIG;
+
+typedef struct _SET_VLD_CONFIG_PARAMS_IN {
+	u8 enable_disable;
+	u8 rsvd0;
+	u16 rsvd1;
+} SG_PACK SET_VLD_CONFIG_PARAMS_IN, *PSET_VLD_CONFIG_PARAMS_IN;
+
+typedef struct _SET_VLD_CONFIG_PARAMS_OUT {
+	u32 rsvd0;
+} SG_PACK SET_VLD_CONFIG_PARAMS_OUT, *PSET_VLD_CONFIG_PARAMS_OUT;
+
+typedef union _SET_VLD_CONFIG_PARAMS {
+	SET_VLD_CONFIG_PARAMS_IN request;
+	SET_VLD_CONFIG_PARAMS_OUT response;
+} SG_PACK SET_VLD_CONFIG_PARAMS, *PSET_VLD_CONFIG_PARAMS;
+
+/*
+ *  Enable/Disable Virtual Link Down (VLD) if this feature is enabled
+ *  on your BladeEngine.  Use IOCTL_COMMON_GET_CNTL_ATTRIBUTES to determine
+ *  whether VLD can be enabled. This  IOCTL can only originate from domain
+ *  0. The VLD setting applies to the entire  BladeEngine and affects
+ *  all NIC/iSCSI drivers.
+ */
+typedef struct _IOCTL_COMMON_SET_VLD_CONFIG {
+	IOCTL_HEADER header;
+	SET_VLD_CONFIG_PARAMS params;
+} SG_PACK IOCTL_COMMON_SET_VLD_CONFIG, *PIOCTL_COMMON_SET_VLD_CONFIG;
+
+typedef struct _GET_VLD_CONFIG_PARAMS_IN {
+	u32 rsvd0;
+} SG_PACK GET_VLD_CONFIG_PARAMS_IN, *PGET_VLD_CONFIG_PARAMS_IN;
+
+typedef struct _GET_VLD_CONFIG_PARAMS_OUT {
+	u8 enable_disable;
+	u8 rsvd0;
+	u16 rsvd1;
+} SG_PACK GET_VLD_CONFIG_PARAMS_OUT, *PGET_VLD_CONFIG_PARAMS_OUT;
+
+typedef union _GET_VLD_CONFIG_PARAMS {
+	GET_VLD_CONFIG_PARAMS_IN request;
+	GET_VLD_CONFIG_PARAMS_OUT response;
+} SG_PACK GET_VLD_CONFIG_PARAMS, *PGET_VLD_CONFIG_PARAMS;
+
+/*
+ *  Use this IOCTL to determine whether Virtual Link Down (VLD) is currently
+ *  enabled or  disabled. Use IOCTL_COMMON_GET_CNTL_ATTRIBUTES to determine
+ *  whether VLD can be  enabled/disabled. This IOCTL can only originate
+ *  from domain 0. The VLD setting applies  to the entire BladeEngine
+ *  and affects all NIC/iSCSI drivers.
+ */
+typedef struct _IOCTL_COMMON_GET_VLD_CONFIG {
+	IOCTL_HEADER header;
+	GET_VLD_CONFIG_PARAMS params;
+} SG_PACK IOCTL_COMMON_GET_VLD_CONFIG, *PIOCTL_COMMON_GET_VLD_CONFIG;
+
+typedef struct _EQ_DELAY_PARAMS {
+	u32 eq_id;
+	u32 delay_in_microseconds;
+} SG_PACK EQ_DELAY_PARAMS, *PEQ_DELAY_PARAMS;
+
+typedef struct _IOCTL_COMMON_ANON_257_REQUEST {
+	u32 num_eq;
+	u32 rsvd0;
+	EQ_DELAY_PARAMS delay[16];
+} SG_PACK IOCTL_COMMON_ANON_257_REQUEST, *PIOCTL_COMMON_ANON_257_REQUEST;
+
+typedef struct _IOCTL_COMMON_ANON_258_RESPONSE {
+	u32 delay_resolution_in_microseconds;
+	u32 delay_max_in_microseconds;
+} SG_PACK IOCTL_COMMON_ANON_258_RESPONSE, *PIOCTL_COMMON_ANON_258_RESPONSE;
+
+typedef union _MODIFY_EQ_DELAY_PARAMS {
+	IOCTL_COMMON_ANON_257_REQUEST request;
+	IOCTL_COMMON_ANON_258_RESPONSE response;
+} SG_PACK MODIFY_EQ_DELAY_PARAMS, *PMODIFY_EQ_DELAY_PARAMS;
+
+/* This IOCTL changes the EQ delay for a given set of EQs.  */
+typedef struct _IOCTL_COMMON_MODIFY_EQ_DELAY {
+	IOCTL_HEADER header;
+	MODIFY_EQ_DELAY_PARAMS params;
+} SG_PACK IOCTL_COMMON_MODIFY_EQ_DELAY, *PIOCTL_COMMON_MODIFY_EQ_DELAY;
+
+typedef struct _IOCTL_COMMON_ANON_260_REQUEST {
+	u32 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_260_REQUEST, *PIOCTL_COMMON_ANON_260_REQUEST;
+
+typedef struct _BE_FIRMWARE_CONFIG {
+	u16 be_config_number;
+	u16 asic_revision;
+	u32 nic_ulp_mask;
+	u32 tulp_mask;
+	u32 iscsi_ulp_mask;
+	u32 rdma_ulp_mask;
+	u32 rsvd0[4];
+	u32 eth_tx_id_start;
+	u32 eth_tx_id_count;
+	u32 eth_rx_id_start;
+	u32 eth_rx_id_count;
+	u32 tpm_wrbq_id_start;
+	u32 tpm_wrbq_id_count;
+	u32 tpm_defq_id_start;
+	u32 tpm_defq_id_count;
+	u32 iscsi_wrbq_id_start;
+	u32 iscsi_wrbq_id_count;
+	u32 iscsi_defq_id_start;
+	u32 iscsi_defq_id_count;
+	u32 rdma_qp_id_start;
+	u32 rdma_qp_id_count;
+	u32 rsvd1[8];
+} SG_PACK BE_FIRMWARE_CONFIG, *PBE_FIRMWARE_CONFIG;
+
+typedef union _IOCTL_COMMON_ANON_259_PARAMS {
+	IOCTL_COMMON_ANON_260_REQUEST request;
+	BE_FIRMWARE_CONFIG response;
+} SG_PACK IOCTL_COMMON_ANON_259_PARAMS, *PIOCTL_COMMON_ANON_259_PARAMS;
+
+/*
+ *  This IOCTL queries the current firmware configuration parameters.
+ *   The static  configuration type is defined by be_config_number. This
+ *  differentiates different  BladeEngine builds, such as iSCSI Initiator
+ *  versus iSCSI Target.  For a given static  configuration, the Upper
+ *  Layer Protocol (ULP) processors may be reconfigured to support  different
+ *  protocols. Each ULP processor supports one or more protocols. The
+ *  masks  indicate which processors are configured for each protocol.
+ *   For a given static  configuration, the number of TCP connections
+ *  supported for each protocol may vary. The  *_id_start and *_id_count
+ *  variables define a linear range of IDs that are available for  each
+ *  supported protocol. The *_id_count may be used by the driver to allocate
+ *  the  appropriate number of connection resources. The *_id_start may
+ *  be used to map the  arbitrary range of IDs to a zero-based range
+ *  of indices.
+ */
+typedef struct _IOCTL_COMMON_FIRMWARE_CONFIG {
+	IOCTL_HEADER header;
+	IOCTL_COMMON_ANON_259_PARAMS params;
+} SG_PACK IOCTL_COMMON_FIRMWARE_CONFIG, *PIOCTL_COMMON_FIRMWARE_CONFIG;
+
+typedef struct _IOCTL_COMMON_PORT_EQUALIZATION_PARAMS {
+	u32 emph_lev_sel_port0;
+	u32 emph_lev_sel_port1;
+	u8 xaui_vo_sel;
+	u8 xaui_state;
+	u16 rsvd0;
+	u32 xaui_eq_vector;
+} SG_PACK IOCTL_COMMON_PORT_EQUALIZATION_PARAMS,
+    *PIOCTL_COMMON_PORT_EQUALIZATION_PARAMS;
+
+typedef struct _IOCTL_COMMON_ANON_262_REQUEST {
+	u32 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_262_REQUEST, *PIOCTL_COMMON_ANON_262_REQUEST;
+
+typedef union _IOCTL_COMMON_ANON_261_PARAMS {
+	IOCTL_COMMON_ANON_262_REQUEST request;
+	IOCTL_COMMON_PORT_EQUALIZATION_PARAMS response;
+} SG_PACK IOCTL_COMMON_ANON_261_PARAMS, *PIOCTL_COMMON_ANON_261_PARAMS;
+
+/*
+ *  This IOCTL can be used to read XAUI equalization parameters. The
+ *  ARM firmware applies  default equalization parameters during initialization.
+ *  These parameters may be  customer-specific when derived from the
+ *  SEEPROM. See SEEPROM_DATA for equalization  specific fields.
+ */
+typedef struct _IOCTL_COMMON_GET_PORT_EQUALIZATION {
+	IOCTL_HEADER header;
+	IOCTL_COMMON_ANON_261_PARAMS params;
+} SG_PACK IOCTL_COMMON_GET_PORT_EQUALIZATION,
+    *PIOCTL_COMMON_GET_PORT_EQUALIZATION;
+
+typedef struct _IOCTL_COMMON_ANON_264_RESPONSE {
+	u32 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_264_RESPONSE, *PIOCTL_COMMON_ANON_264_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_263_PARAMS {
+	IOCTL_COMMON_PORT_EQUALIZATION_PARAMS request;
+	IOCTL_COMMON_ANON_264_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_263_PARAMS, *PIOCTL_COMMON_ANON_263_PARAMS;
+
+/*
+ *  This IOCTL can be used to set XAUI equalization parameters. The ARM
+ *  firmware applies  default equalization parameters during initialization.
+ *  These parameters may be  customer-specific when derived from the
+ *  SEEPROM. See SEEPROM_DATA for equalization  specific fields.
+ */
+typedef struct _IOCTL_COMMON_SET_PORT_EQUALIZATION {
+	IOCTL_HEADER header;
+	IOCTL_COMMON_ANON_263_PARAMS params;
+} SG_PACK IOCTL_COMMON_SET_PORT_EQUALIZATION,
+    *PIOCTL_COMMON_SET_PORT_EQUALIZATION;
+
+typedef struct _BE_RED_CHUTE_PARAMETERS {
+	u8 enable;
+	u8 w1;
+	u8 w2;
+	u8 slope;
+	u8 mtu_integer;
+	u8 mtu_exponent;
+	u16 rsvd0;
+	u16 min_pbuf;
+	u16 max_pbuf;
+} SG_PACK BE_RED_CHUTE_PARAMETERS, *PBE_RED_CHUTE_PARAMETERS;
+
+typedef struct _BE_RED_PARAMETERS {
+	BE_RED_CHUTE_PARAMETERS chute[3];
+} SG_PACK BE_RED_PARAMETERS, *PBE_RED_PARAMETERS;
+
+typedef struct _IOCTL_COMMON_ANON_266_RESPONSE {
+	u32 rsvd0;
+} SG_PACK IOCTL_COMMON_ANON_266_RESPONSE, *PIOCTL_COMMON_ANON_266_RESPONSE;
+
+typedef union _IOCTL_COMMON_ANON_265_PARAMS {
+	BE_RED_PARAMETERS request;
+	IOCTL_COMMON_ANON_266_RESPONSE response;
+} SG_PACK IOCTL_COMMON_ANON_265_PARAMS, *PIOCTL_COMMON_ANON_265_PARAMS;
+
+/*
+ *  This IOCTL configures the Random Early Discard (RED) functionality
+ *  for the PCI  function. Only the chutes owned by the given PCI function
+ *  are configured. The other  chutes are ignored.
+ */
+typedef struct _IOCTL_COMMON_RED_CONFIG {
+	IOCTL_HEADER header;
+	IOCTL_COMMON_ANON_265_PARAMS params;
+} SG_PACK IOCTL_COMMON_RED_CONFIG, *PIOCTL_COMMON_RED_CONFIG;
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __ioctl_common_bmap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ep_bmap.h benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ep_bmap.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ep_bmap.h	1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/ep_bmap.h	2008-02-14 15:23:07.834201784 +0530
@@ -0,0 +1,175 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@...verengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __ep_bmap_h__
+#define __ep_bmap_h__
+#include "setypes.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_C_ASSERT
+#define SG_C_ASSERT(_name_, _condition_)
+#endif
+
+#if defined(__BIG_ENDIAN)
+   /* General Control and Status Register. */
+typedef struct _EP_CONTROL_CSR {
+	union {
+		struct {
+			u32 CPU_reset:1;	/* DWORD 0 */
+			u32 rsvd0:27;	/* DWORD 0 */
+			u32 ff_en:1;	/* DWORD 0 */
+			u32 m2_RxPbuf:1;	/* DWORD 0 */
+			u32 m1_RxPbuf:1;	/* DWORD 0 */
+			u32 m0_RxPbuf:1;	/* DWORD 0 */
+		} SG_PACK;	/* unnamed struct */
+		u32 dw;		/* dword union */
+	};			/* unnamed union */
+} SG_PACK EP_CONTROL_CSR, *PEP_CONTROL_CSR;
+
+SG_C_ASSERT(__sizeof__EP_CONTROL_CSR, sizeof(EP_CONTROL_CSR) == 4);
+
+#else
+   /* General Control and Status Register. */
+typedef struct _EP_CONTROL_CSR {
+	union {
+		struct {
+			u32 m0_RxPbuf:1;	/* DWORD 0 */
+			u32 m1_RxPbuf:1;	/* DWORD 0 */
+			u32 m2_RxPbuf:1;	/* DWORD 0 */
+			u32 ff_en:1;	/* DWORD 0 */
+			u32 rsvd0:27;	/* DWORD 0 */
+			u32 CPU_reset:1;	/* DWORD 0 */
+		} SG_PACK;	/* unnamed struct */
+		u32 dw;		/* dword union */
+	};			/* unnamed union */
+} SG_PACK EP_CONTROL_CSR, *PEP_CONTROL_CSR;
+
+SG_C_ASSERT(__sizeof__EP_CONTROL_CSR, sizeof(EP_CONTROL_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+   /* Semaphore Register. */
+typedef struct _EP_SEMAPHORE_CSR {
+	union {
+		struct {
+			u32 value;	/* DWORD 0 */
+		} SG_PACK;	/* unnamed struct */
+		u32 dw;		/* dword union */
+	};			/* unnamed union */
+} SG_PACK EP_SEMAPHORE_CSR, *PEP_SEMAPHORE_CSR;
+
+SG_C_ASSERT(__sizeof__EP_SEMAPHORE_CSR, sizeof(EP_SEMAPHORE_CSR) == 4);
+
+#else
+   /* Semaphore Register. */
+typedef struct _EP_SEMAPHORE_CSR {
+	union {
+		struct {
+			u32 value;	/* DWORD 0 */
+		} SG_PACK;	/* unnamed struct */
+		u32 dw;		/* dword union */
+	};			/* unnamed union */
+} SG_PACK EP_SEMAPHORE_CSR, *PEP_SEMAPHORE_CSR;
+
+SG_C_ASSERT(__sizeof__EP_SEMAPHORE_CSR, sizeof(EP_SEMAPHORE_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+   /* Embedded Processor Specific Registers. */
+typedef struct _EP_CSRMAP {
+	union {
+		struct {
+			EP_CONTROL_CSR ep_control;
+			u32 rsvd0[1];	/* DWORDS 1 to 1 */
+			u32 rsvd1[1];	/* DWORDS 2 to 2 */
+			u32 rsvd2[1];	/* DWORDS 3 to 3 */
+			u32 rsvd3[1];	/* DWORDS 4 to 4 */
+			u32 rsvd4[1];	/* DWORDS 5 to 5 */
+			u32 rsvd5[32];	/* DWORDS 6 to 37 */
+			u32 rsvd6[1];	/* DWORDS 38 to 38 */
+			u32 rsvd7[1];	/* DWORDS 39 to 39 */
+			u32 rsvd8[1];	/* DWORDS 40 to 40 */
+			u32 rsvd9[1];	/* DWORDS 41 to 41 */
+			u32 rsvd10[1];	/* DWORDS 42 to 42 */
+			EP_SEMAPHORE_CSR ep_semaphore;
+			u32 rsvd11[1];	/* DWORDS 44 to 44 */
+			u32 rsvd12[19];	/* DWORDS 45 to 63 */
+		} SG_PACK;	/* unnamed struct */
+		u32 dw[64];	/* dword union */
+	};			/* unnamed union */
+} SG_PACK EP_CSRMAP, *PEP_CSRMAP;
+
+SG_C_ASSERT(__sizeof__EP_CSRMAP, sizeof(EP_CSRMAP) == 256);
+
+#else
+   /* Embedded Processor Specific Registers. */
+typedef struct _EP_CSRMAP {
+	union {
+		struct {
+			EP_CONTROL_CSR ep_control;
+			u32 rsvd0[1];	/* DWORDS 1 to 1 */
+			u32 rsvd1[1];	/* DWORDS 2 to 2 */
+			u32 rsvd2[1];	/* DWORDS 3 to 3 */
+			u32 rsvd3[1];	/* DWORDS 4 to 4 */
+			u32 rsvd4[1];	/* DWORDS 5 to 5 */
+			u32 rsvd5[32];	/* DWORDS 6 to 37 */
+			u32 rsvd6[1];	/* DWORDS 38 to 38 */
+			u32 rsvd7[1];	/* DWORDS 39 to 39 */
+			u32 rsvd8[1];	/* DWORDS 40 to 40 */
+			u32 rsvd9[1];	/* DWORDS 41 to 41 */
+			u32 rsvd10[1];	/* DWORDS 42 to 42 */
+			EP_SEMAPHORE_CSR ep_semaphore;
+			u32 rsvd11[1];	/* DWORDS 44 to 44 */
+			u32 rsvd12[19];	/* DWORDS 45 to 63 */
+		} SG_PACK;	/* unnamed struct */
+		u32 dw[64];	/* dword union */
+	};			/* unnamed union */
+} SG_PACK EP_CSRMAP, *PEP_CSRMAP;
+
+SG_C_ASSERT(__sizeof__EP_CSRMAP, sizeof(EP_CSRMAP) == 256);
+#endif
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __ep_bmap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/cev_bmap.h benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/cev_bmap.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/cev_bmap.h	1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/cev_bmap.h	2008-02-14 15:23:07.834201784 +0530
@@ -0,0 +1,552 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@...verengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __cev_bmap_h__
+#define __cev_bmap_h__
+#include "setypes.h"
+#include "ep_bmap.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_C_ASSERT
+#define SG_C_ASSERT(_name_, _condition_)
+#endif
+
+#if defined(__BIG_ENDIAN)
+   /*
+    *  Host Interrupt Status Register 0. The first of four application interrupt
+    *  status registers. This register contains the interrupts for Event
+    *  Queues EQ0 through EQ31.
+    */
+typedef struct _CEV_ISR0_CSR {
+	union {
+		struct {
+			u32 interrupt31:1;	/* DWORD 0 */
+			u32 interrupt30:1;	/* DWORD 0 */
+			u32 interrupt29:1;	/* DWORD 0 */
+			u32 interrupt28:1;	/* DWORD 0 */
+			u32 interrupt27:1;	/* DWORD 0 */
+			u32 interrupt26:1;	/* DWORD 0 */
+			u32 interrupt25:1;	/* DWORD 0 */
+			u32 interrupt24:1;	/* DWORD 0 */
+			u32 interrupt23:1;	/* DWORD 0 */
+			u32 interrupt22:1;	/* DWORD 0 */
+			u32 interrupt21:1;	/* DWORD 0 */
+			u32 interrupt20:1;	/* DWORD 0 */
+			u32 interrupt19:1;	/* DWORD 0 */
+			u32 interrupt18:1;	/* DWORD 0 */
+			u32 interrupt17:1;	/* DWORD 0 */
+			u32 interrupt16:1;	/* DWORD 0 */
+			u32 interrupt15:1;	/* DWORD 0 */
+			u32 interrupt14:1;	/* DWORD 0 */
+			u32 interrupt13:1;	/* DWORD 0 */
+			u32 interrupt12:1;	/* DWORD 0 */
+			u32 interrupt11:1;	/* DWORD 0 */
+			u32 interrupt10:1;	/* DWORD 0 */
+			u32 interrupt9:1;	/* DWORD 0 */
+			u32 interrupt8:1;	/* DWORD 0 */
+			u32 interrupt7:1;	/* DWORD 0 */
+			u32 interrupt6:1;	/* DWORD 0 */
+			u32 interrupt5:1;	/* DWORD 0 */
+			u32 interrupt4:1;	/* DWORD 0 */
+			u32 interrupt3:1;	/* DWORD 0 */
+			u32 interrupt2:1;	/* DWORD 0 */
+			u32 interrupt1:1;	/* DWORD 0 */
+			u32 interrupt0:1;	/* DWORD 0 */
+		} SG_PACK;	/* unnamed struct */
+		u32 dw;		/* dword union */
+	};			/* unnamed union */
+} SG_PACK CEV_ISR0_CSR, *PCEV_ISR0_CSR;
+
+SG_C_ASSERT(__sizeof__CEV_ISR0_CSR, sizeof(CEV_ISR0_CSR) == 4);
+
+#else
+   /*
+    *  Host Interrupt Status Register 0. The first of four application interrupt
+    *  status registers. This register contains the interrupts for Event
+    *  Queues EQ0 through EQ31.
+    */
+typedef struct _CEV_ISR0_CSR {
+	union {
+		struct {
+			u32 interrupt0:1;	/* DWORD 0 */
+			u32 interrupt1:1;	/* DWORD 0 */
+			u32 interrupt2:1;	/* DWORD 0 */
+			u32 interrupt3:1;	/* DWORD 0 */
+			u32 interrupt4:1;	/* DWORD 0 */
+			u32 interrupt5:1;	/* DWORD 0 */
+			u32 interrupt6:1;	/* DWORD 0 */
+			u32 interrupt7:1;	/* DWORD 0 */
+			u32 interrupt8:1;	/* DWORD 0 */
+			u32 interrupt9:1;	/* DWORD 0 */
+			u32 interrupt10:1;	/* DWORD 0 */
+			u32 interrupt11:1;	/* DWORD 0 */
+			u32 interrupt12:1;	/* DWORD 0 */
+			u32 interrupt13:1;	/* DWORD 0 */
+			u32 interrupt14:1;	/* DWORD 0 */
+			u32 interrupt15:1;	/* DWORD 0 */
+			u32 interrupt16:1;	/* DWORD 0 */
+			u32 interrupt17:1;	/* DWORD 0 */
+			u32 interrupt18:1;	/* DWORD 0 */
+			u32 interrupt19:1;	/* DWORD 0 */
+			u32 interrupt20:1;	/* DWORD 0 */
+			u32 interrupt21:1;	/* DWORD 0 */
+			u32 interrupt22:1;	/* DWORD 0 */
+			u32 interrupt23:1;	/* DWORD 0 */
+			u32 interrupt24:1;	/* DWORD 0 */
+			u32 interrupt25:1;	/* DWORD 0 */
+			u32 interrupt26:1;	/* DWORD 0 */
+			u32 interrupt27:1;	/* DWORD 0 */
+			u32 interrupt28:1;	/* DWORD 0 */
+			u32 interrupt29:1;	/* DWORD 0 */
+			u32 interrupt30:1;	/* DWORD 0 */
+			u32 interrupt31:1;	/* DWORD 0 */
+		} SG_PACK;	/* unnamed struct */
+		u32 dw;		/* dword union */
+	};			/* unnamed union */
+} SG_PACK CEV_ISR0_CSR, *PCEV_ISR0_CSR;
+
+SG_C_ASSERT(__sizeof__CEV_ISR0_CSR, sizeof(CEV_ISR0_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+   /*
+    *  Host Interrupt Status Register 1. The second of four application
+    *  interrupt status registers. This register contains the interrupts
+    *  for Event Queues EQ32 through EQ63.
+    */
+typedef struct _CEV_ISR1_CSR {
+	union {
+		struct {
+			u32 interrupt63:1;	/* DWORD 0 */
+			u32 interrupt62:1;	/* DWORD 0 */
+			u32 interrupt61:1;	/* DWORD 0 */
+			u32 interrupt60:1;	/* DWORD 0 */
+			u32 interrupt59:1;	/* DWORD 0 */
+			u32 interrupt58:1;	/* DWORD 0 */
+			u32 interrupt57:1;	/* DWORD 0 */
+			u32 interrupt56:1;	/* DWORD 0 */
+			u32 interrupt55:1;	/* DWORD 0 */
+			u32 interrupt54:1;	/* DWORD 0 */
+			u32 interrupt53:1;	/* DWORD 0 */
+			u32 interrupt52:1;	/* DWORD 0 */
+			u32 interrupt51:1;	/* DWORD 0 */
+			u32 interrupt50:1;	/* DWORD 0 */
+			u32 interrupt49:1;	/* DWORD 0 */
+			u32 interrupt48:1;	/* DWORD 0 */
+			u32 interrupt47:1;	/* DWORD 0 */
+			u32 interrupt46:1;	/* DWORD 0 */
+			u32 interrupt45:1;	/* DWORD 0 */
+			u32 interrupt44:1;	/* DWORD 0 */
+			u32 interrupt43:1;	/* DWORD 0 */
+			u32 interrupt42:1;	/* DWORD 0 */
+			u32 interrupt41:1;	/* DWORD 0 */
+			u32 interrupt40:1;	/* DWORD 0 */
+			u32 interrupt39:1;	/* DWORD 0 */
+			u32 interrupt38:1;	/* DWORD 0 */
+			u32 interrupt37:1;	/* DWORD 0 */
+			u32 interrupt36:1;	/* DWORD 0 */
+			u32 interrupt35:1;	/* DWORD 0 */
+			u32 interrupt34:1;	/* DWORD 0 */
+			u32 interrupt33:1;	/* DWORD 0 */
+			u32 interrupt32:1;	/* DWORD 0 */
+		} SG_PACK;	/* unnamed struct */
+		u32 dw;		/* dword union */
+	};			/* unnamed union */
+} SG_PACK CEV_ISR1_CSR, *PCEV_ISR1_CSR;
+
+SG_C_ASSERT(__sizeof__CEV_ISR1_CSR, sizeof(CEV_ISR1_CSR) == 4);
+
+#else
+   /*
+    *  Host Interrupt Status Register 1. The second of four application
+    *  interrupt status registers. This register contains the interrupts
+    *  for Event Queues EQ32 through EQ63.
+    */
+typedef struct _CEV_ISR1_CSR {
+	union {
+		struct {
+			u32 interrupt32:1;	/* DWORD 0 */
+			u32 interrupt33:1;	/* DWORD 0 */
+			u32 interrupt34:1;	/* DWORD 0 */
+			u32 interrupt35:1;	/* DWORD 0 */
+			u32 interrupt36:1;	/* DWORD 0 */
+			u32 interrupt37:1;	/* DWORD 0 */
+			u32 interrupt38:1;	/* DWORD 0 */
+			u32 interrupt39:1;	/* DWORD 0 */
+			u32 interrupt40:1;	/* DWORD 0 */
+			u32 interrupt41:1;	/* DWORD 0 */
+			u32 interrupt42:1;	/* DWORD 0 */
+			u32 interrupt43:1;	/* DWORD 0 */
+			u32 interrupt44:1;	/* DWORD 0 */
+			u32 interrupt45:1;	/* DWORD 0 */
+			u32 interrupt46:1;	/* DWORD 0 */
+			u32 interrupt47:1;	/* DWORD 0 */
+			u32 interrupt48:1;	/* DWORD 0 */
+			u32 interrupt49:1;	/* DWORD 0 */
+			u32 interrupt50:1;	/* DWORD 0 */
+			u32 interrupt51:1;	/* DWORD 0 */
+			u32 interrupt52:1;	/* DWORD 0 */
+			u32 interrupt53:1;	/* DWORD 0 */
+			u32 interrupt54:1;	/* DWORD 0 */
+			u32 interrupt55:1;	/* DWORD 0 */
+			u32 interrupt56:1;	/* DWORD 0 */
+			u32 interrupt57:1;	/* DWORD 0 */
+			u32 interrupt58:1;	/* DWORD 0 */
+			u32 interrupt59:1;	/* DWORD 0 */
+			u32 interrupt60:1;	/* DWORD 0 */
+			u32 interrupt61:1;	/* DWORD 0 */
+			u32 interrupt62:1;	/* DWORD 0 */
+			u32 interrupt63:1;	/* DWORD 0 */
+		} SG_PACK;	/* unnamed struct */
+		u32 dw;		/* dword union */
+	};			/* unnamed union */
+} SG_PACK CEV_ISR1_CSR, *PCEV_ISR1_CSR;
+
+SG_C_ASSERT(__sizeof__CEV_ISR1_CSR, sizeof(CEV_ISR1_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+   /*
+    *  Host Interrupt Status Register 2. The third of four application interrupt
+    *  status registers. This register contains the interrupts for Event
+    *  Queues EQ64 through EQ95.
+    */
+typedef struct _CEV_ISR2_CSR {
+	union {
+		struct {
+			u32 interrupt95:1;	/* DWORD 0 */
+			u32 interrupt94:1;	/* DWORD 0 */
+			u32 interrupt93:1;	/* DWORD 0 */
+			u32 interrupt92:1;	/* DWORD 0 */
+			u32 interrupt91:1;	/* DWORD 0 */
+			u32 interrupt90:1;	/* DWORD 0 */
+			u32 interrupt89:1;	/* DWORD 0 */
+			u32 interrupt88:1;	/* DWORD 0 */
+			u32 interrupt87:1;	/* DWORD 0 */
+			u32 interrupt86:1;	/* DWORD 0 */
+			u32 interrupt85:1;	/* DWORD 0 */
+			u32 interrupt84:1;	/* DWORD 0 */
+			u32 interrupt83:1;	/* DWORD 0 */
+			u32 interrupt82:1;	/* DWORD 0 */
+			u32 interrupt81:1;	/* DWORD 0 */
+			u32 interrupt80:1;	/* DWORD 0 */
+			u32 interrupt79:1;	/* DWORD 0 */
+			u32 interrupt78:1;	/* DWORD 0 */
+			u32 interrupt77:1;	/* DWORD 0 */
+			u32 interrupt76:1;	/* DWORD 0 */
+			u32 interrupt75:1;	/* DWORD 0 */
+			u32 interrupt74:1;	/* DWORD 0 */
+			u32 interrupt73:1;	/* DWORD 0 */
+			u32 interrupt72:1;	/* DWORD 0 */
+			u32 interrupt71:1;	/* DWORD 0 */
+			u32 interrupt70:1;	/* DWORD 0 */
+			u32 interrupt69:1;	/* DWORD 0 */
+			u32 interrupt68:1;	/* DWORD 0 */
+			u32 interrupt67:1;	/* DWORD 0 */
+			u32 interrupt66:1;	/* DWORD 0 */
+			u32 interrupt65:1;	/* DWORD 0 */
+			u32 interrupt64:1;	/* DWORD 0 */
+		} SG_PACK;	/* unnamed struct */
+		u32 dw;		/* dword union */
+	};			/* unnamed union */
+} SG_PACK CEV_ISR2_CSR, *PCEV_ISR2_CSR;
+
+SG_C_ASSERT(__sizeof__CEV_ISR2_CSR, sizeof(CEV_ISR2_CSR) == 4);
+
+#else
+   /*
+    *  Host Interrupt Status Register 2. The third of four application interrupt
+    *  status registers. This register contains the interrupts for Event
+    *  Queues EQ64 through EQ95.
+    */
+typedef struct _CEV_ISR2_CSR {
+	union {
+		struct {
+			u32 interrupt64:1;	/* DWORD 0 */
+			u32 interrupt65:1;	/* DWORD 0 */
+			u32 interrupt66:1;	/* DWORD 0 */
+			u32 interrupt67:1;	/* DWORD 0 */
+			u32 interrupt68:1;	/* DWORD 0 */
+			u32 interrupt69:1;	/* DWORD 0 */
+			u32 interrupt70:1;	/* DWORD 0 */
+			u32 interrupt71:1;	/* DWORD 0 */
+			u32 interrupt72:1;	/* DWORD 0 */
+			u32 interrupt73:1;	/* DWORD 0 */
+			u32 interrupt74:1;	/* DWORD 0 */
+			u32 interrupt75:1;	/* DWORD 0 */
+			u32 interrupt76:1;	/* DWORD 0 */
+			u32 interrupt77:1;	/* DWORD 0 */
+			u32 interrupt78:1;	/* DWORD 0 */
+			u32 interrupt79:1;	/* DWORD 0 */
+			u32 interrupt80:1;	/* DWORD 0 */
+			u32 interrupt81:1;	/* DWORD 0 */
+			u32 interrupt82:1;	/* DWORD 0 */
+			u32 interrupt83:1;	/* DWORD 0 */
+			u32 interrupt84:1;	/* DWORD 0 */
+			u32 interrupt85:1;	/* DWORD 0 */
+			u32 interrupt86:1;	/* DWORD 0 */
+			u32 interrupt87:1;	/* DWORD 0 */
+			u32 interrupt88:1;	/* DWORD 0 */
+			u32 interrupt89:1;	/* DWORD 0 */
+			u32 interrupt90:1;	/* DWORD 0 */
+			u32 interrupt91:1;	/* DWORD 0 */
+			u32 interrupt92:1;	/* DWORD 0 */
+			u32 interrupt93:1;	/* DWORD 0 */
+			u32 interrupt94:1;	/* DWORD 0 */
+			u32 interrupt95:1;	/* DWORD 0 */
+		} SG_PACK;	/* unnamed struct */
+		u32 dw;		/* dword union */
+	};			/* unnamed union */
+} SG_PACK CEV_ISR2_CSR, *PCEV_ISR2_CSR;
+
+SG_C_ASSERT(__sizeof__CEV_ISR2_CSR, sizeof(CEV_ISR2_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+   /*
+    *  Host Interrupt Status Register 3. The fourth of four application
+    *  interrupt status registers. This register contains the interrupts
+    *  for Event Queues EQ96 through EQ127.
+    */
+typedef struct _CEV_ISR3_CSR {
+	union {
+		struct {
+			u32 interrupt127:1;	/* DWORD 0 */
+			u32 interrupt126:1;	/* DWORD 0 */
+			u32 interrupt125:1;	/* DWORD 0 */
+			u32 interrupt124:1;	/* DWORD 0 */
+			u32 interrupt123:1;	/* DWORD 0 */
+			u32 interrupt122:1;	/* DWORD 0 */
+			u32 interrupt121:1;	/* DWORD 0 */
+			u32 interrupt120:1;	/* DWORD 0 */
+			u32 interrupt119:1;	/* DWORD 0 */
+			u32 interrupt118:1;	/* DWORD 0 */
+			u32 interrupt117:1;	/* DWORD 0 */
+			u32 interrupt116:1;	/* DWORD 0 */
+			u32 interrupt115:1;	/* DWORD 0 */
+			u32 interrupt114:1;	/* DWORD 0 */
+			u32 interrupt113:1;	/* DWORD 0 */
+			u32 interrupt112:1;	/* DWORD 0 */
+			u32 interrupt111:1;	/* DWORD 0 */
+			u32 interrupt110:1;	/* DWORD 0 */
+			u32 interrupt109:1;	/* DWORD 0 */
+			u32 interrupt108:1;	/* DWORD 0 */
+			u32 interrupt107:1;	/* DWORD 0 */
+			u32 interrupt106:1;	/* DWORD 0 */
+			u32 interrupt105:1;	/* DWORD 0 */
+			u32 interrupt104:1;	/* DWORD 0 */
+			u32 interrupt103:1;	/* DWORD 0 */
+			u32 interrupt102:1;	/* DWORD 0 */
+			u32 interrupt101:1;	/* DWORD 0 */
+			u32 interrupt100:1;	/* DWORD 0 */
+			u32 interrupt99:1;	/* DWORD 0 */
+			u32 interrupt98:1;	/* DWORD 0 */
+			u32 interrupt97:1;	/* DWORD 0 */
+			u32 interrupt96:1;	/* DWORD 0 */
+		} SG_PACK;	/* unnamed struct */
+		u32 dw;		/* dword union */
+	};			/* unnamed union */
+} SG_PACK CEV_ISR3_CSR, *PCEV_ISR3_CSR;
+
+SG_C_ASSERT(__sizeof__CEV_ISR3_CSR, sizeof(CEV_ISR3_CSR) == 4);
+
+#else
+   /*
+    *  Host Interrupt Status Register 3. The fourth of four application
+    *  interrupt status registers. This register contains the interrupts
+    *  for Event Queues EQ96 through EQ127.
+    */
+typedef struct _CEV_ISR3_CSR {
+	union {
+		struct {
+			u32 interrupt96:1;	/* DWORD 0 */
+			u32 interrupt97:1;	/* DWORD 0 */
+			u32 interrupt98:1;	/* DWORD 0 */
+			u32 interrupt99:1;	/* DWORD 0 */
+			u32 interrupt100:1;	/* DWORD 0 */
+			u32 interrupt101:1;	/* DWORD 0 */
+			u32 interrupt102:1;	/* DWORD 0 */
+			u32 interrupt103:1;	/* DWORD 0 */
+			u32 interrupt104:1;	/* DWORD 0 */
+			u32 interrupt105:1;	/* DWORD 0 */
+			u32 interrupt106:1;	/* DWORD 0 */
+			u32 interrupt107:1;	/* DWORD 0 */
+			u32 interrupt108:1;	/* DWORD 0 */
+			u32 interrupt109:1;	/* DWORD 0 */
+			u32 interrupt110:1;	/* DWORD 0 */
+			u32 interrupt111:1;	/* DWORD 0 */
+			u32 interrupt112:1;	/* DWORD 0 */
+			u32 interrupt113:1;	/* DWORD 0 */
+			u32 interrupt114:1;	/* DWORD 0 */
+			u32 interrupt115:1;	/* DWORD 0 */
+			u32 interrupt116:1;	/* DWORD 0 */
+			u32 interrupt117:1;	/* DWORD 0 */
+			u32 interrupt118:1;	/* DWORD 0 */
+			u32 interrupt119:1;	/* DWORD 0 */
+			u32 interrupt120:1;	/* DWORD 0 */
+			u32 interrupt121:1;	/* DWORD 0 */
+			u32 interrupt122:1;	/* DWORD 0 */
+			u32 interrupt123:1;	/* DWORD 0 */
+			u32 interrupt124:1;	/* DWORD 0 */
+			u32 interrupt125:1;	/* DWORD 0 */
+			u32 interrupt126:1;	/* DWORD 0 */
+			u32 interrupt127:1;	/* DWORD 0 */
+		} SG_PACK;	/* unnamed struct */
+		u32 dw;		/* dword union */
+	};			/* unnamed union */
+} SG_PACK CEV_ISR3_CSR, *PCEV_ISR3_CSR;
+
+SG_C_ASSERT(__sizeof__CEV_ISR3_CSR, sizeof(CEV_ISR3_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+   /* Completions and Events block Registers.  */
+typedef struct _CEV_CSRMAP {
+	union {
+		struct {
+			u32 rsvd0[1];	/* DWORDS 0 to 0 */
+			u32 rsvd1[1];	/* DWORDS 1 to 1 */
+			u32 rsvd2[1];	/* DWORDS 2 to 2 */
+			u32 rsvd3[1];	/* DWORDS 3 to 3 */
+			CEV_ISR0_CSR isr0;
+			CEV_ISR1_CSR isr1;
+			CEV_ISR2_CSR isr2;
+			CEV_ISR3_CSR isr3;
+			u32 rsvd4[1];	/* DWORDS 8 to 8 */
+			u32 rsvd5[1];	/* DWORDS 9 to 9 */
+			u32 rsvd6[1];	/* DWORDS 10 to 10 */
+			u32 rsvd7[1];	/* DWORDS 11 to 11 */
+			u32 rsvd8[1];	/* DWORDS 12 to 12 */
+			u32 rsvd9[1];	/* DWORDS 13 to 13 */
+			u32 rsvd10[1];	/* DWORDS 14 to 14 */
+			u32 rsvd11[1];	/* DWORDS 15 to 15 */
+			u32 rsvd12[1];	/* DWORDS 16 to 16 */
+			u32 rsvd13[1];	/* DWORDS 17 to 17 */
+			u32 rsvd14[1];	/* DWORDS 18 to 18 */
+			u32 rsvd15[1];	/* DWORDS 19 to 19 */
+			u32 rsvd16[1];	/* DWORDS 20 to 20 */
+			u32 rsvd17[1];	/* DWORDS 21 to 21 */
+			u32 rsvd18[1];	/* DWORDS 22 to 22 */
+			u32 rsvd19[1];	/* DWORDS 23 to 23 */
+			u32 rsvd20[1];	/* DWORDS 24 to 24 */
+			u32 rsvd21[1];	/* DWORDS 25 to 25 */
+			u32 rsvd22[1];	/* DWORDS 26 to 26 */
+			u32 rsvd23[1];	/* DWORDS 27 to 27 */
+			u32 rsvd24[1];	/* DWORDS 28 to 28 */
+			u32 rsvd25[1];	/* DWORDS 29 to 29 */
+			u32 rsvd26[1];	/* DWORDS 30 to 30 */
+			u32 rsvd27[1];	/* DWORDS 31 to 31 */
+			u32 rsvd28[1];	/* DWORDS 32 to 32 */
+			u32 rsvd29[1];	/* DWORDS 33 to 33 */
+			u32 rsvd30[6];	/* DWORDS 34 to 39 */
+			u32 rsvd31[6];	/* DWORDS 40 to 45 */
+			u32 rsvd32[5];	/* DWORDS 46 to 50 */
+			u32 rsvd33[5];	/* DWORDS 51 to 55 */
+			u32 rsvd34[5];	/* DWORDS 56 to 60 */
+			u32 rsvd35[3];	/* DWORDS 61 to 63 */
+			u32 rsvd36[192];	/* DWORDS 64 to 255 */
+		} SG_PACK;	/* unnamed struct */
+		u32 dw[256];	/* dword union */
+	};			/* unnamed union */
+} SG_PACK CEV_CSRMAP, *PCEV_CSRMAP;
+
+SG_C_ASSERT(__sizeof__CEV_CSRMAP, sizeof(CEV_CSRMAP) == 1024);
+
+#else
+   /* Completions and Events block Registers.  */
+typedef struct _CEV_CSRMAP {
+	union {
+		struct {
+			u32 rsvd0[1];	/* DWORDS 0 to 0 */
+			u32 rsvd1[1];	/* DWORDS 1 to 1 */
+			u32 rsvd2[1];	/* DWORDS 2 to 2 */
+			u32 rsvd3[1];	/* DWORDS 3 to 3 */
+			CEV_ISR0_CSR isr0;
+			CEV_ISR1_CSR isr1;
+			CEV_ISR2_CSR isr2;
+			CEV_ISR3_CSR isr3;
+			u32 rsvd4[1];	/* DWORDS 8 to 8 */
+			u32 rsvd5[1];	/* DWORDS 9 to 9 */
+			u32 rsvd6[1];	/* DWORDS 10 to 10 */
+			u32 rsvd7[1];	/* DWORDS 11 to 11 */
+			u32 rsvd8[1];	/* DWORDS 12 to 12 */
+			u32 rsvd9[1];	/* DWORDS 13 to 13 */
+			u32 rsvd10[1];	/* DWORDS 14 to 14 */
+			u32 rsvd11[1];	/* DWORDS 15 to 15 */
+			u32 rsvd12[1];	/* DWORDS 16 to 16 */
+			u32 rsvd13[1];	/* DWORDS 17 to 17 */
+			u32 rsvd14[1];	/* DWORDS 18 to 18 */
+			u32 rsvd15[1];	/* DWORDS 19 to 19 */
+			u32 rsvd16[1];	/* DWORDS 20 to 20 */
+			u32 rsvd17[1];	/* DWORDS 21 to 21 */
+			u32 rsvd18[1];	/* DWORDS 22 to 22 */
+			u32 rsvd19[1];	/* DWORDS 23 to 23 */
+			u32 rsvd20[1];	/* DWORDS 24 to 24 */
+			u32 rsvd21[1];	/* DWORDS 25 to 25 */
+			u32 rsvd22[1];	/* DWORDS 26 to 26 */
+			u32 rsvd23[1];	/* DWORDS 27 to 27 */
+			u32 rsvd24[1];	/* DWORDS 28 to 28 */
+			u32 rsvd25[1];	/* DWORDS 29 to 29 */
+			u32 rsvd26[1];	/* DWORDS 30 to 30 */
+			u32 rsvd27[1];	/* DWORDS 31 to 31 */
+			u32 rsvd28[1];	/* DWORDS 32 to 32 */
+			u32 rsvd29[1];	/* DWORDS 33 to 33 */
+			u32 rsvd30[6];	/* DWORDS 34 to 39 */
+			u32 rsvd31[6];	/* DWORDS 40 to 45 */
+			u32 rsvd32[5];	/* DWORDS 46 to 50 */
+			u32 rsvd33[5];	/* DWORDS 51 to 55 */
+			u32 rsvd34[5];	/* DWORDS 56 to 60 */
+			u32 rsvd35[3];	/* DWORDS 61 to 63 */
+			u32 rsvd36[192];	/* DWORDS 64 to 255 */
+		} SG_PACK;	/* unnamed struct */
+		u32 dw[256];	/* dword union */
+	};			/* unnamed union */
+} SG_PACK CEV_CSRMAP, *PCEV_CSRMAP;
+
+SG_C_ASSERT(__sizeof__CEV_CSRMAP, sizeof(CEV_CSRMAP) == 1024);
+#endif
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __cev_bmap_h__ */
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/be_cm_bmap.h benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/be_cm_bmap.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/be_cm_bmap.h	1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/be_cm_bmap.h	2008-02-14 15:23:07.835201632 +0530
@@ -0,0 +1,174 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@...verengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __be_cm_bmap_h__
+#define __be_cm_bmap_h__
+#include "setypes.h"
+#include "be_common_bmap.h"
+#include "iscsi_common_host_struct_bmap.h"
+#include "etx_context_bmap.h"
+#include "mpu_context_bmap.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_C_ASSERT
+#define SG_C_ASSERT(_name_, _condition_)
+#endif
+
+#if defined(__BIG_ENDIAN)
+   /*
+    *  Completion Queue Context Table Entry. Contains the state of a CQ.
+    *  Located in RAM within the CEV block.
+    */
+typedef struct _CQ_CONTEXT {
+	u32 Eventable:1;	/* DWORD 0 */
+	u32 SolEvent:1;		/* DWORD 0 */
+	u32 valid:1;		/* DWORD 0 */
+	u32 Count:2;		/* DWORD 0 */
+	u32 EPIdx:11;		/* DWORD 0 */
+	u32 NoDelay:1;		/* DWORD 0 */
+	u32 Watermark:4;	/* DWORD 0 */
+	u32 Cidx:11;		/* DWORD 0 */
+	u32 Armed:1;		/* DWORD 1 */
+	u32 Stalled:1;		/* DWORD 1 */
+	u32 WME:1;		/* DWORD 1 */
+	u32 Func:1;		/* DWORD 1 */
+	u32 EQID:7;		/* DWORD 1 */
+	u32 PD:10;		/* DWORD 1 */
+	u32 Pidx:11;		/* DWORD 1 */
+} SG_PACK CQ_CONTEXT, *PCQ_CONTEXT;
+
+#else
+   /*
+    *  Completion Queue Context Table Entry. Contains the state of a CQ.
+    *  Located in RAM within the CEV block.
+    */
+typedef struct _CQ_CONTEXT {
+	u32 Cidx:11;		/* DWORD 0 */
+	u32 Watermark:4;	/* DWORD 0 */
+	u32 NoDelay:1;		/* DWORD 0 */
+	u32 EPIdx:11;		/* DWORD 0 */
+	u32 Count:2;		/* DWORD 0 */
+	u32 valid:1;		/* DWORD 0 */
+	u32 SolEvent:1;		/* DWORD 0 */
+	u32 Eventable:1;	/* DWORD 0 */
+	u32 Pidx:11;		/* DWORD 1 */
+	u32 PD:10;		/* DWORD 1 */
+	u32 EQID:7;		/* DWORD 1 */
+	u32 Func:1;		/* DWORD 1 */
+	u32 WME:1;		/* DWORD 1 */
+	u32 Stalled:1;		/* DWORD 1 */
+	u32 Armed:1;		/* DWORD 1 */
+} SG_PACK CQ_CONTEXT, *PCQ_CONTEXT;
+
+#endif
+
+#if defined(__BIG_ENDIAN)
+   /*
+    *  Event Queue Context Table Entry. Contains the state of an EQ. Located
+    *  in RAM in the CEV block.
+    */
+typedef struct _EQ_CONTEXT {
+	u32 Size:1;		/* DWORD 0 */
+	u32 rsvd1:1;		/* DWORD 0 */
+	u32 valid:1;		/* DWORD 0 */
+	u32 EPIdx:13;		/* DWORD 0 */
+	u32 Func:1;		/* DWORD 0 */
+	u32 rsvd0:2;		/* DWORD 0 */
+	u32 Cidx:13;		/* DWORD 0 */
+	u32 Armed:1;		/* DWORD 1 */
+	u32 Stalled:1;		/* DWORD 1 */
+	u32 SolEvent:1;		/* DWORD 1 */
+	u32 Count:3;		/* DWORD 1 */
+	u32 PD:10;		/* DWORD 1 */
+	u32 rsvd2:3;		/* DWORD 1 */
+	u32 Pidx:13;		/* DWORD 1 */
+	u32 rsvd6:1;		/* DWORD 2 */
+	u32 TMR:1;		/* DWORD 2 */
+	u32 rsvd5:6;		/* DWORD 2 */
+	u32 Delay:8;		/* DWORD 2 */
+	u32 rsvd4:2;		/* DWORD 2 */
+	u32 EventVect:6;	/* DWORD 2 */
+	u32 rsvd3:3;		/* DWORD 2 */
+	u32 WME:1;		/* DWORD 2 */
+	u32 Watermark:4;	/* DWORD 2 */
+	u32 rsvd7[1];		/* DWORDS 3 to 3 */
+} SG_PACK EQ_CONTEXT, *PEQ_CONTEXT;
+
+#else
+   /*
+    *  Event Queue Context Table Entry. Contains the state of an EQ. Located
+    *  in RAM in the CEV block.
+    */
+typedef struct _EQ_CONTEXT {
+	u32 Cidx:13;		/* DWORD 0 */
+	u32 rsvd0:2;		/* DWORD 0 */
+	u32 Func:1;		/* DWORD 0 */
+	u32 EPIdx:13;		/* DWORD 0 */
+	u32 valid:1;		/* DWORD 0 */
+	u32 rsvd1:1;		/* DWORD 0 */
+	u32 Size:1;		/* DWORD 0 */
+	u32 Pidx:13;		/* DWORD 1 */
+	u32 rsvd2:3;		/* DWORD 1 */
+	u32 PD:10;		/* DWORD 1 */
+	u32 Count:3;		/* DWORD 1 */
+	u32 SolEvent:1;		/* DWORD 1 */
+	u32 Stalled:1;		/* DWORD 1 */
+	u32 Armed:1;		/* DWORD 1 */
+	u32 Watermark:4;	/* DWORD 2 */
+	u32 WME:1;		/* DWORD 2 */
+	u32 rsvd3:3;		/* DWORD 2 */
+	u32 EventVect:6;	/* DWORD 2 */
+	u32 rsvd4:2;		/* DWORD 2 */
+	u32 Delay:8;		/* DWORD 2 */
+	u32 rsvd5:6;		/* DWORD 2 */
+	u32 TMR:1;		/* DWORD 2 */
+	u32 rsvd6:1;		/* DWORD 2 */
+	u32 rsvd7[1];		/* DWORDS 3 to 3 */
+} SG_PACK EQ_CONTEXT, *PEQ_CONTEXT;
+
+#endif
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __be_cm_bmap_h__ */

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