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Message-ID: <20080217031317.46122fa5@mailhost.serverengines.com>
Date: Sat, 16 Feb 2008 19:13:17 -0800
From: "Subbu Seetharaman" <subbus@...verengines.com>
To: netdev@...r.kernel.org
Subject: [PATHCH 15/16] ServerEngines 10Gb NIC driver
F/W header files.
-------------------
diff -uprN orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/pcicfg_bmap.h benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/pcicfg_bmap.h
--- orig/linux-2.6.24.2/drivers/message/beclib/fw/bmap/pcicfg_bmap.h 1970-01-01 05:30:00.000000000 +0530
+++ benet/linux-2.6.24.2/drivers/message/beclib/fw/bmap/pcicfg_bmap.h 2008-02-14 15:23:07.839201024 +0530
@@ -0,0 +1,2333 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@...verengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __pcicfg_bmap_h__
+#define __pcicfg_bmap_h__
+#include "setypes.h"
+
+#undef SG_PACK
+#if defined(SG_PRAGMA_PACK)
+#pragma pack(push, 1)
+#define SG_PACK
+#elif defined(SG_ATTRIBUTE_PACK)
+#define SG_PACK __attribute__ ((packed))
+#else
+#define SG_PACK
+#endif
+
+#ifndef SG_C_ASSERT
+#define SG_C_ASSERT(_name_, _condition_)
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Vendor and Device ID Register. */
+typedef struct _PCICFG_ID_CSR {
+ union {
+ struct {
+ u32 deviceid:16; /* DWORD 0 */
+ u32 vendorid:16; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ID_CSR, *PPCICFG_ID_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_ID_CSR, sizeof(PCICFG_ID_CSR) == 4);
+
+#else
+ /* Vendor and Device ID Register. */
+typedef struct _PCICFG_ID_CSR {
+ union {
+ struct {
+ u32 vendorid:16; /* DWORD 0 */
+ u32 deviceid:16; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ID_CSR, *PPCICFG_ID_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_ID_CSR, sizeof(PCICFG_ID_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* IO Bar Register. */
+typedef struct _PCICFG_IOBAR_CSR {
+ union {
+ struct {
+ u32 iobar:24; /* DWORD 0 */
+ u32 rsvd0:7; /* DWORD 0 */
+ u32 iospace:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_IOBAR_CSR, *PPCICFG_IOBAR_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_IOBAR_CSR, sizeof(PCICFG_IOBAR_CSR) == 4);
+
+#else
+ /* IO Bar Register. */
+typedef struct _PCICFG_IOBAR_CSR {
+ union {
+ struct {
+ u32 iospace:1; /* DWORD 0 */
+ u32 rsvd0:7; /* DWORD 0 */
+ u32 iobar:24; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_IOBAR_CSR, *PPCICFG_IOBAR_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_IOBAR_CSR, sizeof(PCICFG_IOBAR_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Memory BAR 0 Register. */
+typedef struct _PCICFG_MEMBAR0_CSR {
+ union {
+ struct {
+ u32 membar0:18; /* DWORD 0 */
+ u32 rsvd0:10; /* DWORD 0 */
+ u32 pf:1; /* DWORD 0 */
+ u32 type:2; /* DWORD 0 */
+ u32 memspace:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MEMBAR0_CSR, *PPCICFG_MEMBAR0_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MEMBAR0_CSR, sizeof(PCICFG_MEMBAR0_CSR) == 4);
+
+#else
+ /* Memory BAR 0 Register. */
+typedef struct _PCICFG_MEMBAR0_CSR {
+ union {
+ struct {
+ u32 memspace:1; /* DWORD 0 */
+ u32 type:2; /* DWORD 0 */
+ u32 pf:1; /* DWORD 0 */
+ u32 rsvd0:10; /* DWORD 0 */
+ u32 membar0:18; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MEMBAR0_CSR, *PPCICFG_MEMBAR0_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MEMBAR0_CSR, sizeof(PCICFG_MEMBAR0_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Memory BAR 1 - Low Address Register. */
+typedef struct _PCICFG_MEMBAR1_LO_CSR {
+ union {
+ struct {
+ u32 membar1lo:15; /* DWORD 0 */
+ u32 rsvd0:13; /* DWORD 0 */
+ u32 pf:1; /* DWORD 0 */
+ u32 type:2; /* DWORD 0 */
+ u32 memspace:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MEMBAR1_LO_CSR, *PPCICFG_MEMBAR1_LO_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MEMBAR1_LO_CSR,
+ sizeof(PCICFG_MEMBAR1_LO_CSR) == 4);
+
+#else
+ /* Memory BAR 1 - Low Address Register. */
+typedef struct _PCICFG_MEMBAR1_LO_CSR {
+ union {
+ struct {
+ u32 memspace:1; /* DWORD 0 */
+ u32 type:2; /* DWORD 0 */
+ u32 pf:1; /* DWORD 0 */
+ u32 rsvd0:13; /* DWORD 0 */
+ u32 membar1lo:15; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MEMBAR1_LO_CSR, *PPCICFG_MEMBAR1_LO_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MEMBAR1_LO_CSR,
+ sizeof(PCICFG_MEMBAR1_LO_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Memory BAR 1 - High Address Register. */
+typedef struct _PCICFG_MEMBAR1_HI_CSR {
+ union {
+ struct {
+ u32 membar1hi; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MEMBAR1_HI_CSR, *PPCICFG_MEMBAR1_HI_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MEMBAR1_HI_CSR,
+ sizeof(PCICFG_MEMBAR1_HI_CSR) == 4);
+
+#else
+ /* Memory BAR 1 - High Address Register. */
+typedef struct _PCICFG_MEMBAR1_HI_CSR {
+ union {
+ struct {
+ u32 membar1hi; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MEMBAR1_HI_CSR, *PPCICFG_MEMBAR1_HI_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MEMBAR1_HI_CSR,
+ sizeof(PCICFG_MEMBAR1_HI_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Memory BAR 2 - Low Address Register. */
+typedef struct _PCICFG_MEMBAR2_LO_CSR {
+ union {
+ struct {
+ u32 membar2lo:11; /* DWORD 0 */
+ u32 rsvd0:17; /* DWORD 0 */
+ u32 pf:1; /* DWORD 0 */
+ u32 type:2; /* DWORD 0 */
+ u32 memspace:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MEMBAR2_LO_CSR, *PPCICFG_MEMBAR2_LO_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MEMBAR2_LO_CSR,
+ sizeof(PCICFG_MEMBAR2_LO_CSR) == 4);
+
+#else
+ /* Memory BAR 2 - Low Address Register. */
+typedef struct _PCICFG_MEMBAR2_LO_CSR {
+ union {
+ struct {
+ u32 memspace:1; /* DWORD 0 */
+ u32 type:2; /* DWORD 0 */
+ u32 pf:1; /* DWORD 0 */
+ u32 rsvd0:17; /* DWORD 0 */
+ u32 membar2lo:11; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MEMBAR2_LO_CSR, *PPCICFG_MEMBAR2_LO_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MEMBAR2_LO_CSR,
+ sizeof(PCICFG_MEMBAR2_LO_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Memory BAR 2 - High Address Register. */
+typedef struct _PCICFG_MEMBAR2_HI_CSR {
+ union {
+ struct {
+ u32 membar2hi; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MEMBAR2_HI_CSR, *PPCICFG_MEMBAR2_HI_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MEMBAR2_HI_CSR,
+ sizeof(PCICFG_MEMBAR2_HI_CSR) == 4);
+
+#else
+ /* Memory BAR 2 - High Address Register. */
+typedef struct _PCICFG_MEMBAR2_HI_CSR {
+ union {
+ struct {
+ u32 membar2hi; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MEMBAR2_HI_CSR, *PPCICFG_MEMBAR2_HI_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MEMBAR2_HI_CSR,
+ sizeof(PCICFG_MEMBAR2_HI_CSR) == 4);
+
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Subsystem Vendor and ID (Function 0) Register. */
+typedef struct _PCICFG_SUBSYSTEM_ID_F0_CSR {
+ union {
+ struct {
+ u32 subsys_id:16; /* DWORD 0 */
+ u32 subsys_vendor_id:16; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_SUBSYSTEM_ID_F0_CSR, *PPCICFG_SUBSYSTEM_ID_F0_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_SUBSYSTEM_ID_F0_CSR,
+ sizeof(PCICFG_SUBSYSTEM_ID_F0_CSR) == 4);
+
+#else
+ /* Subsystem Vendor and ID (Function 0) Register. */
+typedef struct _PCICFG_SUBSYSTEM_ID_F0_CSR {
+ union {
+ struct {
+ u32 subsys_vendor_id:16; /* DWORD 0 */
+ u32 subsys_id:16; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_SUBSYSTEM_ID_F0_CSR, *PPCICFG_SUBSYSTEM_ID_F0_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_SUBSYSTEM_ID_F0_CSR,
+ sizeof(PCICFG_SUBSYSTEM_ID_F0_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Subsystem Vendor and ID (Function 1) Register. */
+typedef struct _PCICFG_SUBSYSTEM_ID_F1_CSR {
+ union {
+ struct {
+ u32 subsys_id:16; /* DWORD 0 */
+ u32 subsys_vendor_id:16; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_SUBSYSTEM_ID_F1_CSR, *PPCICFG_SUBSYSTEM_ID_F1_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_SUBSYSTEM_ID_F1_CSR,
+ sizeof(PCICFG_SUBSYSTEM_ID_F1_CSR) == 4);
+
+#else
+ /* Subsystem Vendor and ID (Function 1) Register. */
+typedef struct _PCICFG_SUBSYSTEM_ID_F1_CSR {
+ union {
+ struct {
+ u32 subsys_vendor_id:16; /* DWORD 0 */
+ u32 subsys_id:16; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_SUBSYSTEM_ID_F1_CSR, *PPCICFG_SUBSYSTEM_ID_F1_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_SUBSYSTEM_ID_F1_CSR,
+ sizeof(PCICFG_SUBSYSTEM_ID_F1_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Semaphore Register. */
+typedef struct _PCICFG_SEMAPHORE_CSR {
+ union {
+ struct {
+ u32 rsvd0:31; /* DWORD 0 */
+ u32 locked:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_SEMAPHORE_CSR, *PPCICFG_SEMAPHORE_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_SEMAPHORE_CSR,
+ sizeof(PCICFG_SEMAPHORE_CSR) == 4);
+
+#else
+ /* Semaphore Register. */
+typedef struct _PCICFG_SEMAPHORE_CSR {
+ union {
+ struct {
+ u32 locked:1; /* DWORD 0 */
+ u32 rsvd0:31; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_SEMAPHORE_CSR, *PPCICFG_SEMAPHORE_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_SEMAPHORE_CSR,
+ sizeof(PCICFG_SEMAPHORE_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Soft Reset Register. */
+typedef struct _PCICFG_SOFT_RESET_CSR {
+ union {
+ struct {
+ u32 nec_ll_rcvdetect_i:8; /* DWORD 0 */
+ u32 rsvd1:16; /* DWORD 0 */
+ u32 softreset:1; /* DWORD 0 */
+ u32 rsvd0:7; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_SOFT_RESET_CSR, *PPCICFG_SOFT_RESET_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_SOFT_RESET_CSR,
+ sizeof(PCICFG_SOFT_RESET_CSR) == 4);
+
+#else
+ /* Soft Reset Register. */
+typedef struct _PCICFG_SOFT_RESET_CSR {
+ union {
+ struct {
+ u32 rsvd0:7; /* DWORD 0 */
+ u32 softreset:1; /* DWORD 0 */
+ u32 rsvd1:16; /* DWORD 0 */
+ u32 nec_ll_rcvdetect_i:8; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_SOFT_RESET_CSR, *PPCICFG_SOFT_RESET_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_SOFT_RESET_CSR,
+ sizeof(PCICFG_SOFT_RESET_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * Unrecoverable Error Status (Low) Register.<BR> Each bit corresponds
+ * to an internal Unrecoverable Error. These are set by hardware
+ * and may be cleared by writing a one to the respective bit(s)
+ * to be cleared. Any bit being set that is also unmasked will result
+ * in Unrecoverable Error interrupt notification to the host CPU
+ * and/or Server Management chip; and the transitioning of BladeEngine
+ * to an Offline state.
+ */
+typedef struct _PCICFG_UE_STATUS_LOW_CSR {
+ union {
+ struct {
+ u32 mpu_intpend_ue_status:1; /* DWORD 0 */
+ u32 axgmac1_ue_status:1; /* DWORD 0 */
+ u32 axgmac0_ue_status:1; /* DWORD 0 */
+ u32 mbox_stor_ue_status:1; /* DWORD 0 */
+ u32 mbox_netw_ue_status:1; /* DWORD 0 */
+ u32 host_gpio_ue_status:1; /* DWORD 0 */
+ u32 p1_ob_link_ue_status:1; /* DWORD 0 */
+ u32 p0_ob_link_ue_status:1; /* DWORD 0 */
+ u32 host1_ue_status:1; /* DWORD 0 */
+ u32 txulp2_ue_status:1; /* DWORD 0 */
+ u32 wdma_ue_status:1; /* DWORD 0 */
+ u32 uc_ue_status:1; /* DWORD 0 */
+ u32 txulp1_ue_status:1; /* DWORD 0 */
+ u32 txulp0_ue_status:1; /* DWORD 0 */
+ u32 txips_ue_status:1; /* DWORD 0 */
+ u32 tpre_ue_status:1; /* DWORD 0 */
+ u32 tpost_ue_status:1; /* DWORD 0 */
+ u32 tim_ue_status:1; /* DWORD 0 */
+ u32 rxulp2_ue_status:1; /* DWORD 0 */
+ u32 rxulp1_ue_status:1; /* DWORD 0 */
+ u32 rxulp0_ue_status:1; /* DWORD 0 */
+ u32 rxips_ue_status:1; /* DWORD 0 */
+ u32 rxf_ue_status:1; /* DWORD 0 */
+ u32 rdma_ue_status:1; /* DWORD 0 */
+ u32 ptc_ue_status:1; /* DWORD 0 */
+ u32 ndma_ue_status:1; /* DWORD 0 */
+ u32 mpu_ue_status:1; /* DWORD 0 */
+ u32 host_ue_status:1; /* DWORD 0 */
+ u32 erx_ue_status:1; /* DWORD 0 */
+ u32 dbuf_ue_status:1; /* DWORD 0 */
+ u32 ctx_ue_status:1; /* DWORD 0 */
+ u32 cev_ue_status:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_UE_STATUS_LOW_CSR, *PPCICFG_UE_STATUS_LOW_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_UE_STATUS_LOW_CSR,
+ sizeof(PCICFG_UE_STATUS_LOW_CSR) == 4);
+
+#else
+ /*
+ * Unrecoverable Error Status (Low) Register.<BR> Each bit corresponds
+ * to an internal Unrecoverable Error. These are set by hardware
+ * and may be cleared by writing a one to the respective bit(s)
+ * to be cleared. Any bit being set that is also unmasked will result
+ * in Unrecoverable Error interrupt notification to the host CPU
+ * and/or Server Management chip; and the transitioning of BladeEngine
+ * to an Offline state.
+ */
+typedef struct _PCICFG_UE_STATUS_LOW_CSR {
+ union {
+ struct {
+ u32 cev_ue_status:1; /* DWORD 0 */
+ u32 ctx_ue_status:1; /* DWORD 0 */
+ u32 dbuf_ue_status:1; /* DWORD 0 */
+ u32 erx_ue_status:1; /* DWORD 0 */
+ u32 host_ue_status:1; /* DWORD 0 */
+ u32 mpu_ue_status:1; /* DWORD 0 */
+ u32 ndma_ue_status:1; /* DWORD 0 */
+ u32 ptc_ue_status:1; /* DWORD 0 */
+ u32 rdma_ue_status:1; /* DWORD 0 */
+ u32 rxf_ue_status:1; /* DWORD 0 */
+ u32 rxips_ue_status:1; /* DWORD 0 */
+ u32 rxulp0_ue_status:1; /* DWORD 0 */
+ u32 rxulp1_ue_status:1; /* DWORD 0 */
+ u32 rxulp2_ue_status:1; /* DWORD 0 */
+ u32 tim_ue_status:1; /* DWORD 0 */
+ u32 tpost_ue_status:1; /* DWORD 0 */
+ u32 tpre_ue_status:1; /* DWORD 0 */
+ u32 txips_ue_status:1; /* DWORD 0 */
+ u32 txulp0_ue_status:1; /* DWORD 0 */
+ u32 txulp1_ue_status:1; /* DWORD 0 */
+ u32 uc_ue_status:1; /* DWORD 0 */
+ u32 wdma_ue_status:1; /* DWORD 0 */
+ u32 txulp2_ue_status:1; /* DWORD 0 */
+ u32 host1_ue_status:1; /* DWORD 0 */
+ u32 p0_ob_link_ue_status:1; /* DWORD 0 */
+ u32 p1_ob_link_ue_status:1; /* DWORD 0 */
+ u32 host_gpio_ue_status:1; /* DWORD 0 */
+ u32 mbox_netw_ue_status:1; /* DWORD 0 */
+ u32 mbox_stor_ue_status:1; /* DWORD 0 */
+ u32 axgmac0_ue_status:1; /* DWORD 0 */
+ u32 axgmac1_ue_status:1; /* DWORD 0 */
+ u32 mpu_intpend_ue_status:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_UE_STATUS_LOW_CSR, *PPCICFG_UE_STATUS_LOW_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_UE_STATUS_LOW_CSR,
+ sizeof(PCICFG_UE_STATUS_LOW_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * Unrecoverable Error Status (High) Register.<BR> Each bit corresponds
+ * to an internal Unrecoverable Error. These are set by hardware
+ * and may be cleared by writing a one to the respective bit(s)
+ * to be cleared. Any bit being set that is also unmasked will result
+ * in Unrecoverable Error interrupt notification to the host CPU
+ * and/or Server Management chip; and the transitioning of BladeEngine
+ * to an Offline state.
+ */
+typedef struct _PCICFG_UE_STATUS_HI_CSR {
+ union {
+ struct {
+ u32 rsvd0:16; /* DWORD 0 */
+ u32 ipc_ue_status:1; /* DWORD 0 */
+ u32 arm_ue_status:1; /* DWORD 0 */
+ u32 xaui_ue_status:1; /* DWORD 0 */
+ u32 txp_ue_status:1; /* DWORD 0 */
+ u32 txpb_ue_status:1; /* DWORD 0 */
+ u32 rxpp_ue_status:1; /* DWORD 0 */
+ u32 rr_ue_status:1; /* DWORD 0 */
+ u32 pmem_ue_status:1; /* DWORD 0 */
+ u32 pctl1_ue_status:1; /* DWORD 0 */
+ u32 pctl0_ue_status:1; /* DWORD 0 */
+ u32 pcs1online_ue_status:1; /* DWORD 0 */
+ u32 pcs0online_ue_status:1; /* DWORD 0 */
+ u32 mpu_iram_ue_status:1; /* DWORD 0 */
+ u32 mgmt_mac_ue_status:1; /* DWORD 0 */
+ u32 lpcmemhost_ue_status:1; /* DWORD 0 */
+ u32 jtag_ue_status:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_UE_STATUS_HI_CSR, *PPCICFG_UE_STATUS_HI_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_UE_STATUS_HI_CSR,
+ sizeof(PCICFG_UE_STATUS_HI_CSR) == 4);
+
+#else
+ /*
+ * Unrecoverable Error Status (High) Register.<BR> Each bit corresponds
+ * to an internal Unrecoverable Error. These are set by hardware
+ * and may be cleared by writing a one to the respective bit(s)
+ * to be cleared. Any bit being set that is also unmasked will result
+ * in Unrecoverable Error interrupt notification to the host CPU
+ * and/or Server Management chip; and the transitioning of BladeEngine
+ * to an Offline state.
+ */
+typedef struct _PCICFG_UE_STATUS_HI_CSR {
+ union {
+ struct {
+ u32 jtag_ue_status:1; /* DWORD 0 */
+ u32 lpcmemhost_ue_status:1; /* DWORD 0 */
+ u32 mgmt_mac_ue_status:1; /* DWORD 0 */
+ u32 mpu_iram_ue_status:1; /* DWORD 0 */
+ u32 pcs0online_ue_status:1; /* DWORD 0 */
+ u32 pcs1online_ue_status:1; /* DWORD 0 */
+ u32 pctl0_ue_status:1; /* DWORD 0 */
+ u32 pctl1_ue_status:1; /* DWORD 0 */
+ u32 pmem_ue_status:1; /* DWORD 0 */
+ u32 rr_ue_status:1; /* DWORD 0 */
+ u32 rxpp_ue_status:1; /* DWORD 0 */
+ u32 txpb_ue_status:1; /* DWORD 0 */
+ u32 txp_ue_status:1; /* DWORD 0 */
+ u32 xaui_ue_status:1; /* DWORD 0 */
+ u32 arm_ue_status:1; /* DWORD 0 */
+ u32 ipc_ue_status:1; /* DWORD 0 */
+ u32 rsvd0:16; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_UE_STATUS_HI_CSR, *PPCICFG_UE_STATUS_HI_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_UE_STATUS_HI_CSR,
+ sizeof(PCICFG_UE_STATUS_HI_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * Unrecoverable Error Mask (Low) Register.<BR> Each bit, when set to
+ * one, will mask the associated Unrecoverable Error status bit
+ * from notification of Unrecoverable Error to the host CPU and/or
+ * Server Managment chip and the transitioning of all BladeEngine
+ * units to an Offline state.
+ */
+typedef struct _PCICFG_UE_STATUS_LOW_MASK_CSR {
+ union {
+ struct {
+ u32 mpu_intpend_ue_mask:1; /* DWORD 0 */
+ u32 axgmac1_ue_mask:1; /* DWORD 0 */
+ u32 axgmac0_ue_mask:1; /* DWORD 0 */
+ u32 mbox_stor_ue_mask:1; /* DWORD 0 */
+ u32 mbox_netw_ue_mask:1; /* DWORD 0 */
+ u32 host_gpio_ue_mask:1; /* DWORD 0 */
+ u32 p1_ob_link_ue_mask:1; /* DWORD 0 */
+ u32 p0_ob_link_ue_mask:1; /* DWORD 0 */
+ u32 host1_ue_mask:1; /* DWORD 0 */
+ u32 txulp2_ue_mask:1; /* DWORD 0 */
+ u32 wdma_ue_mask:1; /* DWORD 0 */
+ u32 uc_ue_mask:1; /* DWORD 0 */
+ u32 txulp1_ue_mask:1; /* DWORD 0 */
+ u32 txulp0_ue_mask:1; /* DWORD 0 */
+ u32 txips_ue_mask:1; /* DWORD 0 */
+ u32 tpre_ue_mask:1; /* DWORD 0 */
+ u32 tpost_ue_mask:1; /* DWORD 0 */
+ u32 tim_ue_mask:1; /* DWORD 0 */
+ u32 rxulp2_ue_mask:1; /* DWORD 0 */
+ u32 rxulp1_ue_mask:1; /* DWORD 0 */
+ u32 rxulp0_ue_mask:1; /* DWORD 0 */
+ u32 rxips_ue_mask:1; /* DWORD 0 */
+ u32 rxf_ue_mask:1; /* DWORD 0 */
+ u32 rdma_ue_mask:1; /* DWORD 0 */
+ u32 ptc_ue_mask:1; /* DWORD 0 */
+ u32 ndma_ue_mask:1; /* DWORD 0 */
+ u32 mpu_ue_mask:1; /* DWORD 0 */
+ u32 host_ue_mask:1; /* DWORD 0 */
+ u32 erx_ue_mask:1; /* DWORD 0 */
+ u32 dbuf_ue_mask:1; /* DWORD 0 */
+ u32 ctx_ue_mask:1; /* DWORD 0 */
+ u32 cev_ue_mask:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_UE_STATUS_LOW_MASK_CSR, *PPCICFG_UE_STATUS_LOW_MASK_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_UE_STATUS_LOW_MASK_CSR,
+ sizeof(PCICFG_UE_STATUS_LOW_MASK_CSR) == 4);
+
+#else
+ /*
+ * Unrecoverable Error Mask (Low) Register.<BR> Each bit, when set to
+ * one, will mask the associated Unrecoverable Error status bit
+ * from notification of Unrecoverable Error to the host CPU and/or
+ * Server Managment chip and the transitioning of all BladeEngine
+ * units to an Offline state.
+ */
+typedef struct _PCICFG_UE_STATUS_LOW_MASK_CSR {
+ union {
+ struct {
+ u32 cev_ue_mask:1; /* DWORD 0 */
+ u32 ctx_ue_mask:1; /* DWORD 0 */
+ u32 dbuf_ue_mask:1; /* DWORD 0 */
+ u32 erx_ue_mask:1; /* DWORD 0 */
+ u32 host_ue_mask:1; /* DWORD 0 */
+ u32 mpu_ue_mask:1; /* DWORD 0 */
+ u32 ndma_ue_mask:1; /* DWORD 0 */
+ u32 ptc_ue_mask:1; /* DWORD 0 */
+ u32 rdma_ue_mask:1; /* DWORD 0 */
+ u32 rxf_ue_mask:1; /* DWORD 0 */
+ u32 rxips_ue_mask:1; /* DWORD 0 */
+ u32 rxulp0_ue_mask:1; /* DWORD 0 */
+ u32 rxulp1_ue_mask:1; /* DWORD 0 */
+ u32 rxulp2_ue_mask:1; /* DWORD 0 */
+ u32 tim_ue_mask:1; /* DWORD 0 */
+ u32 tpost_ue_mask:1; /* DWORD 0 */
+ u32 tpre_ue_mask:1; /* DWORD 0 */
+ u32 txips_ue_mask:1; /* DWORD 0 */
+ u32 txulp0_ue_mask:1; /* DWORD 0 */
+ u32 txulp1_ue_mask:1; /* DWORD 0 */
+ u32 uc_ue_mask:1; /* DWORD 0 */
+ u32 wdma_ue_mask:1; /* DWORD 0 */
+ u32 txulp2_ue_mask:1; /* DWORD 0 */
+ u32 host1_ue_mask:1; /* DWORD 0 */
+ u32 p0_ob_link_ue_mask:1; /* DWORD 0 */
+ u32 p1_ob_link_ue_mask:1; /* DWORD 0 */
+ u32 host_gpio_ue_mask:1; /* DWORD 0 */
+ u32 mbox_netw_ue_mask:1; /* DWORD 0 */
+ u32 mbox_stor_ue_mask:1; /* DWORD 0 */
+ u32 axgmac0_ue_mask:1; /* DWORD 0 */
+ u32 axgmac1_ue_mask:1; /* DWORD 0 */
+ u32 mpu_intpend_ue_mask:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_UE_STATUS_LOW_MASK_CSR, *PPCICFG_UE_STATUS_LOW_MASK_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_UE_STATUS_LOW_MASK_CSR,
+ sizeof(PCICFG_UE_STATUS_LOW_MASK_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * Unrecoverable Error Mask (High) Register.<BR> Each bit, when set
+ * to one, will mask the associated Unrecoverable Error status bit
+ * from notification of Unrecoverable Error to the host CPU and/or
+ * Server Managment chip and the transitioning of all BladeEngine
+ * units to an Offline state.
+ */
+typedef struct _PCICFG_UE_STATUS_HI_MASK_CSR {
+ union {
+ struct {
+ u32 rsvd0:16; /* DWORD 0 */
+ u32 ipc_ue_mask:1; /* DWORD 0 */
+ u32 arm_ue_mask:1; /* DWORD 0 */
+ u32 xaui_ue_mask:1; /* DWORD 0 */
+ u32 txp_ue_mask:1; /* DWORD 0 */
+ u32 txpb_ue_mask:1; /* DWORD 0 */
+ u32 rxpp_ue_mask:1; /* DWORD 0 */
+ u32 rr_ue_mask:1; /* DWORD 0 */
+ u32 pmem_ue_mask:1; /* DWORD 0 */
+ u32 pctl1_ue_mask:1; /* DWORD 0 */
+ u32 pctl0_ue_mask:1; /* DWORD 0 */
+ u32 pcs1online_ue_mask:1; /* DWORD 0 */
+ u32 pcs0online_ue_mask:1; /* DWORD 0 */
+ u32 mpu_iram_ue_mask:1; /* DWORD 0 */
+ u32 mgmt_mac_ue_mask:1; /* DWORD 0 */
+ u32 lpcmemhost_ue_mask:1; /* DWORD 0 */
+ u32 jtag_ue_mask:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_UE_STATUS_HI_MASK_CSR, *PPCICFG_UE_STATUS_HI_MASK_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_UE_STATUS_HI_MASK_CSR,
+ sizeof(PCICFG_UE_STATUS_HI_MASK_CSR) == 4);
+
+#else
+ /*
+ * Unrecoverable Error Mask (High) Register.<BR> Each bit, when set
+ * to one, will mask the associated Unrecoverable Error status bit
+ * from notification of Unrecoverable Error to the host CPU and/or
+ * Server Managment chip and the transitioning of all BladeEngine
+ * units to an Offline state.
+ */
+typedef struct _PCICFG_UE_STATUS_HI_MASK_CSR {
+ union {
+ struct {
+ u32 jtag_ue_mask:1; /* DWORD 0 */
+ u32 lpcmemhost_ue_mask:1; /* DWORD 0 */
+ u32 mgmt_mac_ue_mask:1; /* DWORD 0 */
+ u32 mpu_iram_ue_mask:1; /* DWORD 0 */
+ u32 pcs0online_ue_mask:1; /* DWORD 0 */
+ u32 pcs1online_ue_mask:1; /* DWORD 0 */
+ u32 pctl0_ue_mask:1; /* DWORD 0 */
+ u32 pctl1_ue_mask:1; /* DWORD 0 */
+ u32 pmem_ue_mask:1; /* DWORD 0 */
+ u32 rr_ue_mask:1; /* DWORD 0 */
+ u32 rxpp_ue_mask:1; /* DWORD 0 */
+ u32 txpb_ue_mask:1; /* DWORD 0 */
+ u32 txp_ue_mask:1; /* DWORD 0 */
+ u32 xaui_ue_mask:1; /* DWORD 0 */
+ u32 arm_ue_mask:1; /* DWORD 0 */
+ u32 ipc_ue_mask:1; /* DWORD 0 */
+ u32 rsvd0:16; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_UE_STATUS_HI_MASK_CSR, *PPCICFG_UE_STATUS_HI_MASK_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_UE_STATUS_HI_MASK_CSR,
+ sizeof(PCICFG_UE_STATUS_HI_MASK_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * Online Control Register 0. This register controls various units within
+ * BladeEngine being in an Online or Offline state.
+ */
+typedef struct _PCICFG_ONLINE0_CSR {
+ union {
+ struct {
+ u32 mpu_intpend_online:1; /* DWORD 0 */
+ u32 axgmac1_online:1; /* DWORD 0 */
+ u32 axgmac0_online:1; /* DWORD 0 */
+ u32 mbox_stor_online:1; /* DWORD 0 */
+ u32 mbox_netw_online:1; /* DWORD 0 */
+ u32 host_gpio_online:1; /* DWORD 0 */
+ u32 p1_ob_link_online:1; /* DWORD 0 */
+ u32 p0_ob_link_online:1; /* DWORD 0 */
+ u32 host1_online:1; /* DWORD 0 */
+ u32 txulp2_online:1; /* DWORD 0 */
+ u32 wdma_online:1; /* DWORD 0 */
+ u32 uc_online:1; /* DWORD 0 */
+ u32 txulp1_online:1; /* DWORD 0 */
+ u32 txulp0_online:1; /* DWORD 0 */
+ u32 txips_online:1; /* DWORD 0 */
+ u32 tpre_online:1; /* DWORD 0 */
+ u32 tpost_online:1; /* DWORD 0 */
+ u32 tim_online:1; /* DWORD 0 */
+ u32 rxulp2_online:1; /* DWORD 0 */
+ u32 rxulp1_online:1; /* DWORD 0 */
+ u32 rxulp0_online:1; /* DWORD 0 */
+ u32 rxips_online:1; /* DWORD 0 */
+ u32 rxf_online:1; /* DWORD 0 */
+ u32 rdma_online:1; /* DWORD 0 */
+ u32 ptc_online:1; /* DWORD 0 */
+ u32 ndma_online:1; /* DWORD 0 */
+ u32 mpu_online:1; /* DWORD 0 */
+ u32 host_online:1; /* DWORD 0 */
+ u32 erx_online:1; /* DWORD 0 */
+ u32 dbuf_online:1; /* DWORD 0 */
+ u32 ctx_online:1; /* DWORD 0 */
+ u32 cev_online:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ONLINE0_CSR, *PPCICFG_ONLINE0_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_ONLINE0_CSR, sizeof(PCICFG_ONLINE0_CSR) == 4);
+
+#else
+ /*
+ * Online Control Register 0. This register controls various units within
+ * BladeEngine being in an Online or Offline state.
+ */
+typedef struct _PCICFG_ONLINE0_CSR {
+ union {
+ struct {
+ u32 cev_online:1; /* DWORD 0 */
+ u32 ctx_online:1; /* DWORD 0 */
+ u32 dbuf_online:1; /* DWORD 0 */
+ u32 erx_online:1; /* DWORD 0 */
+ u32 host_online:1; /* DWORD 0 */
+ u32 mpu_online:1; /* DWORD 0 */
+ u32 ndma_online:1; /* DWORD 0 */
+ u32 ptc_online:1; /* DWORD 0 */
+ u32 rdma_online:1; /* DWORD 0 */
+ u32 rxf_online:1; /* DWORD 0 */
+ u32 rxips_online:1; /* DWORD 0 */
+ u32 rxulp0_online:1; /* DWORD 0 */
+ u32 rxulp1_online:1; /* DWORD 0 */
+ u32 rxulp2_online:1; /* DWORD 0 */
+ u32 tim_online:1; /* DWORD 0 */
+ u32 tpost_online:1; /* DWORD 0 */
+ u32 tpre_online:1; /* DWORD 0 */
+ u32 txips_online:1; /* DWORD 0 */
+ u32 txulp0_online:1; /* DWORD 0 */
+ u32 txulp1_online:1; /* DWORD 0 */
+ u32 uc_online:1; /* DWORD 0 */
+ u32 wdma_online:1; /* DWORD 0 */
+ u32 txulp2_online:1; /* DWORD 0 */
+ u32 host1_online:1; /* DWORD 0 */
+ u32 p0_ob_link_online:1; /* DWORD 0 */
+ u32 p1_ob_link_online:1; /* DWORD 0 */
+ u32 host_gpio_online:1; /* DWORD 0 */
+ u32 mbox_netw_online:1; /* DWORD 0 */
+ u32 mbox_stor_online:1; /* DWORD 0 */
+ u32 axgmac0_online:1; /* DWORD 0 */
+ u32 axgmac1_online:1; /* DWORD 0 */
+ u32 mpu_intpend_online:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ONLINE0_CSR, *PPCICFG_ONLINE0_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_ONLINE0_CSR, sizeof(PCICFG_ONLINE0_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * Online Control Register 1. This register controls various units within
+ * BladeEngine being in an Online or Offline state.
+ */
+typedef struct _PCICFG_ONLINE1_CSR {
+ union {
+ struct {
+ u32 rsvd0:16; /* DWORD 0 */
+ u32 ipc_online:1; /* DWORD 0 */
+ u32 arm_online:1; /* DWORD 0 */
+ u32 xaui_online:1; /* DWORD 0 */
+ u32 txp_online:1; /* DWORD 0 */
+ u32 txpb_online:1; /* DWORD 0 */
+ u32 rxpp_online:1; /* DWORD 0 */
+ u32 rr_online:1; /* DWORD 0 */
+ u32 pmem_online:1; /* DWORD 0 */
+ u32 pctl1_online:1; /* DWORD 0 */
+ u32 pctl0_online:1; /* DWORD 0 */
+ u32 pcs1online_online:1; /* DWORD 0 */
+ u32 pcs0online_online:1; /* DWORD 0 */
+ u32 mpu_iram_online:1; /* DWORD 0 */
+ u32 mgmt_mac_online:1; /* DWORD 0 */
+ u32 lpcmemhost_online:1; /* DWORD 0 */
+ u32 jtag_online:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ONLINE1_CSR, *PPCICFG_ONLINE1_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_ONLINE1_CSR, sizeof(PCICFG_ONLINE1_CSR) == 4);
+
+#else
+ /*
+ * Online Control Register 1. This register controls various units within
+ * BladeEngine being in an Online or Offline state.
+ */
+typedef struct _PCICFG_ONLINE1_CSR {
+ union {
+ struct {
+ u32 jtag_online:1; /* DWORD 0 */
+ u32 lpcmemhost_online:1; /* DWORD 0 */
+ u32 mgmt_mac_online:1; /* DWORD 0 */
+ u32 mpu_iram_online:1; /* DWORD 0 */
+ u32 pcs0online_online:1; /* DWORD 0 */
+ u32 pcs1online_online:1; /* DWORD 0 */
+ u32 pctl0_online:1; /* DWORD 0 */
+ u32 pctl1_online:1; /* DWORD 0 */
+ u32 pmem_online:1; /* DWORD 0 */
+ u32 rr_online:1; /* DWORD 0 */
+ u32 rxpp_online:1; /* DWORD 0 */
+ u32 txpb_online:1; /* DWORD 0 */
+ u32 txp_online:1; /* DWORD 0 */
+ u32 xaui_online:1; /* DWORD 0 */
+ u32 arm_online:1; /* DWORD 0 */
+ u32 ipc_online:1; /* DWORD 0 */
+ u32 rsvd0:16; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ONLINE1_CSR, *PPCICFG_ONLINE1_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_ONLINE1_CSR, sizeof(PCICFG_ONLINE1_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Host Timer Register. */
+typedef struct _PCICFG_HOST_TIMER_INT_CTRL_CSR {
+ union {
+ struct {
+ u32 rsvd0:7; /* DWORD 0 */
+ u32 hostintr:1; /* DWORD 0 */
+ u32 hosttimer:24; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_HOST_TIMER_INT_CTRL_CSR, *PPCICFG_HOST_TIMER_INT_CTRL_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_HOST_TIMER_INT_CTRL_CSR,
+ sizeof(PCICFG_HOST_TIMER_INT_CTRL_CSR) == 4);
+
+#else
+ /* Host Timer Register. */
+typedef struct _PCICFG_HOST_TIMER_INT_CTRL_CSR {
+ union {
+ struct {
+ u32 hosttimer:24; /* DWORD 0 */
+ u32 hostintr:1; /* DWORD 0 */
+ u32 rsvd0:7; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_HOST_TIMER_INT_CTRL_CSR, *PPCICFG_HOST_TIMER_INT_CTRL_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_HOST_TIMER_INT_CTRL_CSR,
+ sizeof(PCICFG_HOST_TIMER_INT_CTRL_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* Scratchpad Register (for software use). */
+typedef struct _PCICFG_SCRATCHPAD_CSR {
+ union {
+ struct {
+ u32 scratchpad; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_SCRATCHPAD_CSR, *PPCICFG_SCRATCHPAD_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_SCRATCHPAD_CSR,
+ sizeof(PCICFG_SCRATCHPAD_CSR) == 4);
+
+#else
+ /* Scratchpad Register (for software use). */
+typedef struct _PCICFG_SCRATCHPAD_CSR {
+ union {
+ struct {
+ u32 scratchpad; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_SCRATCHPAD_CSR, *PPCICFG_SCRATCHPAD_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_SCRATCHPAD_CSR,
+ sizeof(PCICFG_SCRATCHPAD_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* PCI Express Capabilities Register. */
+typedef struct _PCICFG_PCIE_CAP_CSR {
+ union {
+ struct {
+ u32 rsvd1:2; /* DWORD 0 */
+ u32 rsvd0:6; /* DWORD 0 */
+ u32 devport:4; /* DWORD 0 */
+ u32 capver:4; /* DWORD 0 */
+ u32 nextcap:8; /* DWORD 0 */
+ u32 capid:8; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_PCIE_CAP_CSR, *PPCICFG_PCIE_CAP_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_PCIE_CAP_CSR,
+ sizeof(PCICFG_PCIE_CAP_CSR) == 4);
+
+#else
+ /* PCI Express Capabilities Register. */
+typedef struct _PCICFG_PCIE_CAP_CSR {
+ union {
+ struct {
+ u32 capid:8; /* DWORD 0 */
+ u32 nextcap:8; /* DWORD 0 */
+ u32 capver:4; /* DWORD 0 */
+ u32 devport:4; /* DWORD 0 */
+ u32 rsvd0:6; /* DWORD 0 */
+ u32 rsvd1:2; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_PCIE_CAP_CSR, *PPCICFG_PCIE_CAP_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_PCIE_CAP_CSR,
+ sizeof(PCICFG_PCIE_CAP_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* PCI Express Device Capabilities Register. */
+typedef struct _PCICFG_PCIE_DEVCAP_CSR {
+ union {
+ struct {
+ u32 rsvd3:4; /* DWORD 0 */
+ u32 pwr_scale:2; /* DWORD 0 */
+ u32 pwr_value:8; /* DWORD 0 */
+ u32 rsvd2:3; /* DWORD 0 */
+ u32 rsvd1:3; /* DWORD 0 */
+ u32 l1_lat:3; /* DWORD 0 */
+ u32 lo_lat:3; /* DWORD 0 */
+ u32 rsvd0:3; /* DWORD 0 */
+ u32 payload:3; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_PCIE_DEVCAP_CSR, *PPCICFG_PCIE_DEVCAP_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_PCIE_DEVCAP_CSR,
+ sizeof(PCICFG_PCIE_DEVCAP_CSR) == 4);
+
+#else
+ /* PCI Express Device Capabilities Register. */
+typedef struct _PCICFG_PCIE_DEVCAP_CSR {
+ union {
+ struct {
+ u32 payload:3; /* DWORD 0 */
+ u32 rsvd0:3; /* DWORD 0 */
+ u32 lo_lat:3; /* DWORD 0 */
+ u32 l1_lat:3; /* DWORD 0 */
+ u32 rsvd1:3; /* DWORD 0 */
+ u32 rsvd2:3; /* DWORD 0 */
+ u32 pwr_value:8; /* DWORD 0 */
+ u32 pwr_scale:2; /* DWORD 0 */
+ u32 rsvd3:4; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_PCIE_DEVCAP_CSR, *PPCICFG_PCIE_DEVCAP_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_PCIE_DEVCAP_CSR,
+ sizeof(PCICFG_PCIE_DEVCAP_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* PCI Express Device Control/Status Registers. */
+typedef struct _PCICFG_PCIE_CONTROL_STATUS_CSR {
+ union {
+ struct {
+ u32 rsvd1:10; /* DWORD 0 */
+ u32 TransPending:1; /* DWORD 0 */
+ u32 AuxPwrDetect:1; /* DWORD 0 */
+ u32 UnsuppReqDetect:1; /* DWORD 0 */
+ u32 FatalErrDetect:1; /* DWORD 0 */
+ u32 NonFatalErrDetect:1; /* DWORD 0 */
+ u32 CorrErrDetect:1; /* DWORD 0 */
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 Max_Read_Req_Size:3; /* DWORD 0 */
+ u32 EnableNoSnoop:1; /* DWORD 0 */
+ u32 AuxPwrPMEnable:1; /* DWORD 0 */
+ u32 PhantomFnEnable:1; /* DWORD 0 */
+ u32 ExtendTagFieldEnable:1; /* DWORD 0 */
+ u32 Max_Payload_Size:3; /* DWORD 0 */
+ u32 EnableRelaxOrder:1; /* DWORD 0 */
+ u32 UnsuppReqReportEn:1; /* DWORD 0 */
+ u32 FatalErrReportEn:1; /* DWORD 0 */
+ u32 NonFatalErrReportEn:1; /* DWORD 0 */
+ u32 CorrErrReportEn:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_PCIE_CONTROL_STATUS_CSR, *PPCICFG_PCIE_CONTROL_STATUS_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_PCIE_CONTROL_STATUS_CSR,
+ sizeof(PCICFG_PCIE_CONTROL_STATUS_CSR) == 4);
+
+#else
+ /* PCI Express Device Control/Status Registers. */
+typedef struct _PCICFG_PCIE_CONTROL_STATUS_CSR {
+ union {
+ struct {
+ u32 CorrErrReportEn:1; /* DWORD 0 */
+ u32 NonFatalErrReportEn:1; /* DWORD 0 */
+ u32 FatalErrReportEn:1; /* DWORD 0 */
+ u32 UnsuppReqReportEn:1; /* DWORD 0 */
+ u32 EnableRelaxOrder:1; /* DWORD 0 */
+ u32 Max_Payload_Size:3; /* DWORD 0 */
+ u32 ExtendTagFieldEnable:1; /* DWORD 0 */
+ u32 PhantomFnEnable:1; /* DWORD 0 */
+ u32 AuxPwrPMEnable:1; /* DWORD 0 */
+ u32 EnableNoSnoop:1; /* DWORD 0 */
+ u32 Max_Read_Req_Size:3; /* DWORD 0 */
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 CorrErrDetect:1; /* DWORD 0 */
+ u32 NonFatalErrDetect:1; /* DWORD 0 */
+ u32 FatalErrDetect:1; /* DWORD 0 */
+ u32 UnsuppReqDetect:1; /* DWORD 0 */
+ u32 AuxPwrDetect:1; /* DWORD 0 */
+ u32 TransPending:1; /* DWORD 0 */
+ u32 rsvd1:10; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_PCIE_CONTROL_STATUS_CSR, *PPCICFG_PCIE_CONTROL_STATUS_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_PCIE_CONTROL_STATUS_CSR,
+ sizeof(PCICFG_PCIE_CONTROL_STATUS_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* PCI Express Link Capabilities Register. */
+typedef struct _PCICFG_PCIE_LINK_CAP_CSR {
+ union {
+ struct {
+ u32 PortNum:8; /* DWORD 0 */
+ u32 rsvd0:6; /* DWORD 0 */
+ u32 L1ExitLat:3; /* DWORD 0 */
+ u32 L0sExitLat:3; /* DWORD 0 */
+ u32 ASPMSupport:2; /* DWORD 0 */
+ u32 MaxLinkWidth:6; /* DWORD 0 */
+ u32 MaxLinkSpeed:4; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_PCIE_LINK_CAP_CSR, *PPCICFG_PCIE_LINK_CAP_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_PCIE_LINK_CAP_CSR,
+ sizeof(PCICFG_PCIE_LINK_CAP_CSR) == 4);
+
+#else
+ /* PCI Express Link Capabilities Register. */
+typedef struct _PCICFG_PCIE_LINK_CAP_CSR {
+ union {
+ struct {
+ u32 MaxLinkSpeed:4; /* DWORD 0 */
+ u32 MaxLinkWidth:6; /* DWORD 0 */
+ u32 ASPMSupport:2; /* DWORD 0 */
+ u32 L0sExitLat:3; /* DWORD 0 */
+ u32 L1ExitLat:3; /* DWORD 0 */
+ u32 rsvd0:6; /* DWORD 0 */
+ u32 PortNum:8; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_PCIE_LINK_CAP_CSR, *PPCICFG_PCIE_LINK_CAP_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_PCIE_LINK_CAP_CSR,
+ sizeof(PCICFG_PCIE_LINK_CAP_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* PCI Express Link Status Register. */
+typedef struct _PCICFG_PCIE_LINK_STATUS_CSR {
+ union {
+ struct {
+ u32 rsvd2:3; /* DWORD 0 */
+ u32 SlotClkConfig:1; /* DWORD 0 */
+ u32 LinkTrain:1; /* DWORD 0 */
+ u32 LinkTrainErr:1; /* DWORD 0 */
+ u32 NegLinkWidth:6; /* DWORD 0 */
+ u32 LinkSpeed:4; /* DWORD 0 */
+ u32 rsvd1:8; /* DWORD 0 */
+ u32 ExtendSync:1; /* DWORD 0 */
+ u32 CommonClkConfig:1; /* DWORD 0 */
+ u32 RetrainLink:1; /* DWORD 0 */
+ u32 LinkDisable:1; /* DWORD 0 */
+ u32 ReadCmplBndry:1; /* DWORD 0 */
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 ASPMCtl:2; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_PCIE_LINK_STATUS_CSR, *PPCICFG_PCIE_LINK_STATUS_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_PCIE_LINK_STATUS_CSR,
+ sizeof(PCICFG_PCIE_LINK_STATUS_CSR) == 4);
+
+#else
+ /* PCI Express Link Status Register. */
+typedef struct _PCICFG_PCIE_LINK_STATUS_CSR {
+ union {
+ struct {
+ u32 ASPMCtl:2; /* DWORD 0 */
+ u32 rsvd0:1; /* DWORD 0 */
+ u32 ReadCmplBndry:1; /* DWORD 0 */
+ u32 LinkDisable:1; /* DWORD 0 */
+ u32 RetrainLink:1; /* DWORD 0 */
+ u32 CommonClkConfig:1; /* DWORD 0 */
+ u32 ExtendSync:1; /* DWORD 0 */
+ u32 rsvd1:8; /* DWORD 0 */
+ u32 LinkSpeed:4; /* DWORD 0 */
+ u32 NegLinkWidth:6; /* DWORD 0 */
+ u32 LinkTrainErr:1; /* DWORD 0 */
+ u32 LinkTrain:1; /* DWORD 0 */
+ u32 SlotClkConfig:1; /* DWORD 0 */
+ u32 rsvd2:3; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_PCIE_LINK_STATUS_CSR, *PPCICFG_PCIE_LINK_STATUS_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_PCIE_LINK_STATUS_CSR,
+ sizeof(PCICFG_PCIE_LINK_STATUS_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* PCI Express MSI Configuration Register. */
+typedef struct _PCICFG_MSI_CSR {
+ union {
+ struct {
+ u32 en:1; /* DWORD 0 */
+ u32 funcmask:1; /* DWORD 0 */
+ u32 rsvd0:3; /* DWORD 0 */
+ u32 tablesize:11; /* DWORD 0 */
+ u32 nextptr:8; /* DWORD 0 */
+ u32 capid:8; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MSI_CSR, *PPCICFG_MSI_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MSI_CSR, sizeof(PCICFG_MSI_CSR) == 4);
+
+#else
+ /* PCI Express MSI Configuration Register. */
+typedef struct _PCICFG_MSI_CSR {
+ union {
+ struct {
+ u32 capid:8; /* DWORD 0 */
+ u32 nextptr:8; /* DWORD 0 */
+ u32 tablesize:11; /* DWORD 0 */
+ u32 rsvd0:3; /* DWORD 0 */
+ u32 funcmask:1; /* DWORD 0 */
+ u32 en:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MSI_CSR, *PPCICFG_MSI_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MSI_CSR, sizeof(PCICFG_MSI_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* MSI-X Table Offset Register. */
+typedef struct _PCICFG_MSIX_TABLE_CSR {
+ union {
+ struct {
+ u32 offset:29; /* DWORD 0 */
+ u32 tablebir:3; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MSIX_TABLE_CSR, *PPCICFG_MSIX_TABLE_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MSIX_TABLE_CSR,
+ sizeof(PCICFG_MSIX_TABLE_CSR) == 4);
+
+#else
+ /* MSI-X Table Offset Register. */
+typedef struct _PCICFG_MSIX_TABLE_CSR {
+ union {
+ struct {
+ u32 tablebir:3; /* DWORD 0 */
+ u32 offset:29; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MSIX_TABLE_CSR, *PPCICFG_MSIX_TABLE_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MSIX_TABLE_CSR,
+ sizeof(PCICFG_MSIX_TABLE_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* MSI-X PBA Offset Register. */
+typedef struct _PCICFG_MSIX_PBA_CSR {
+ union {
+ struct {
+ u32 offset:29; /* DWORD 0 */
+ u32 pbabir:3; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MSIX_PBA_CSR, *PPCICFG_MSIX_PBA_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MSIX_PBA_CSR,
+ sizeof(PCICFG_MSIX_PBA_CSR) == 4);
+
+#else
+ /* MSI-X PBA Offset Register. */
+typedef struct _PCICFG_MSIX_PBA_CSR {
+ union {
+ struct {
+ u32 pbabir:3; /* DWORD 0 */
+ u32 offset:29; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MSIX_PBA_CSR, *PPCICFG_MSIX_PBA_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MSIX_PBA_CSR,
+ sizeof(PCICFG_MSIX_PBA_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* PCI Express MSI-X Message Vector Control Register. */
+typedef struct _PCICFG_MSIX_VECTOR_CONTROL_CSR {
+ union {
+ struct {
+ u32 rsvd0:31; /* DWORD 0 */
+ u32 vector_control:1; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MSIX_VECTOR_CONTROL_CSR, *PPCICFG_MSIX_VECTOR_CONTROL_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MSIX_VECTOR_CONTROL_CSR,
+ sizeof(PCICFG_MSIX_VECTOR_CONTROL_CSR) == 4);
+
+#else
+ /* PCI Express MSI-X Message Vector Control Register. */
+typedef struct _PCICFG_MSIX_VECTOR_CONTROL_CSR {
+ union {
+ struct {
+ u32 vector_control:1; /* DWORD 0 */
+ u32 rsvd0:31; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MSIX_VECTOR_CONTROL_CSR, *PPCICFG_MSIX_VECTOR_CONTROL_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MSIX_VECTOR_CONTROL_CSR,
+ sizeof(PCICFG_MSIX_VECTOR_CONTROL_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* PCI Express MSI-X Message Data Register. */
+typedef struct _PCICFG_MSIX_MSG_DATA_CSR {
+ union {
+ struct {
+ u32 rsvd0:16; /* DWORD 0 */
+ u32 data:16; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MSIX_MSG_DATA_CSR, *PPCICFG_MSIX_MSG_DATA_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MSIX_MSG_DATA_CSR,
+ sizeof(PCICFG_MSIX_MSG_DATA_CSR) == 4);
+
+#else
+ /* PCI Express MSI-X Message Data Register. */
+typedef struct _PCICFG_MSIX_MSG_DATA_CSR {
+ union {
+ struct {
+ u32 data:16; /* DWORD 0 */
+ u32 rsvd0:16; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MSIX_MSG_DATA_CSR, *PPCICFG_MSIX_MSG_DATA_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MSIX_MSG_DATA_CSR,
+ sizeof(PCICFG_MSIX_MSG_DATA_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* PCI Express MSI-X Message Address Register - High Part. */
+typedef struct _PCICFG_MSIX_MSG_ADDR_HI_CSR {
+ union {
+ struct {
+ u32 addr; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MSIX_MSG_ADDR_HI_CSR, *PPCICFG_MSIX_MSG_ADDR_HI_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MSIX_MSG_ADDR_HI_CSR,
+ sizeof(PCICFG_MSIX_MSG_ADDR_HI_CSR) == 4);
+
+#else
+ /* PCI Express MSI-X Message Address Register - High Part. */
+typedef struct _PCICFG_MSIX_MSG_ADDR_HI_CSR {
+ union {
+ struct {
+ u32 addr; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MSIX_MSG_ADDR_HI_CSR, *PPCICFG_MSIX_MSG_ADDR_HI_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MSIX_MSG_ADDR_HI_CSR,
+ sizeof(PCICFG_MSIX_MSG_ADDR_HI_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /* PCI Express MSI-X Message Address Register - Low Part. */
+typedef struct _PCICFG_MSIX_MSG_ADDR_LO_CSR {
+ union {
+ struct {
+ u32 addr:30; /* DWORD 0 */
+ u32 rsvd0:2; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MSIX_MSG_ADDR_LO_CSR, *PPCICFG_MSIX_MSG_ADDR_LO_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MSIX_MSG_ADDR_LO_CSR,
+ sizeof(PCICFG_MSIX_MSG_ADDR_LO_CSR) == 4);
+
+#else
+ /* PCI Express MSI-X Message Address Register - Low Part. */
+typedef struct _PCICFG_MSIX_MSG_ADDR_LO_CSR {
+ union {
+ struct {
+ u32 rsvd0:2; /* DWORD 0 */
+ u32 addr:30; /* DWORD 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_MSIX_MSG_ADDR_LO_CSR, *PPCICFG_MSIX_MSG_ADDR_LO_CSR;
+
+SG_C_ASSERT(__sizeof__PCICFG_MSIX_MSG_ADDR_LO_CSR,
+ sizeof(PCICFG_MSIX_MSG_ADDR_LO_CSR) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _PCICFG_ANON_18_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_18_RSVD, *PPCICFG_ANON_18_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_18_RSVD,
+ sizeof(PCICFG_ANON_18_RSVD) == 4);
+
+#else
+
+typedef struct _PCICFG_ANON_18_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_18_RSVD, *PPCICFG_ANON_18_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_18_RSVD,
+ sizeof(PCICFG_ANON_18_RSVD) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _PCICFG_ANON_19_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_19_RSVD, *PPCICFG_ANON_19_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_19_RSVD,
+ sizeof(PCICFG_ANON_19_RSVD) == 4);
+
+#else
+
+typedef struct _PCICFG_ANON_19_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_19_RSVD, *PPCICFG_ANON_19_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_19_RSVD,
+ sizeof(PCICFG_ANON_19_RSVD) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _PCICFG_ANON_20_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[25]; /* DWORDS 1 to 25 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[26]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_20_RSVD, *PPCICFG_ANON_20_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_20_RSVD,
+ sizeof(PCICFG_ANON_20_RSVD) == 104);
+
+#else
+
+typedef struct _PCICFG_ANON_20_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[25]; /* DWORDS 1 to 25 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[26]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_20_RSVD, *PPCICFG_ANON_20_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_20_RSVD,
+ sizeof(PCICFG_ANON_20_RSVD) == 104);
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _PCICFG_ANON_21_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[1919]; /* DWORDS 1 to 1919 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[1920]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_21_RSVD, *PPCICFG_ANON_21_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_21_RSVD,
+ sizeof(PCICFG_ANON_21_RSVD) == 7680);
+
+#else
+
+typedef struct _PCICFG_ANON_21_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[1919]; /* DWORDS 1 to 1919 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[1920]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_21_RSVD, *PPCICFG_ANON_21_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_21_RSVD,
+ sizeof(PCICFG_ANON_21_RSVD) == 7680);
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _PCICFG_ANON_22_MESSAGE {
+ union {
+ struct {
+ PCICFG_MSIX_VECTOR_CONTROL_CSR vec_ctrl;
+ PCICFG_MSIX_MSG_DATA_CSR msg_data;
+ PCICFG_MSIX_MSG_ADDR_HI_CSR addr_hi;
+ PCICFG_MSIX_MSG_ADDR_LO_CSR addr_low;
+ } SG_PACK; /* unnamed struct */
+ u32 dw[4]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_22_MESSAGE, *PPCICFG_ANON_22_MESSAGE;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_22_MESSAGE,
+ sizeof(PCICFG_ANON_22_MESSAGE) == 16);
+
+#else
+
+typedef struct _PCICFG_ANON_22_MESSAGE {
+ union {
+ struct {
+ PCICFG_MSIX_VECTOR_CONTROL_CSR vec_ctrl;
+ PCICFG_MSIX_MSG_DATA_CSR msg_data;
+ PCICFG_MSIX_MSG_ADDR_HI_CSR addr_hi;
+ PCICFG_MSIX_MSG_ADDR_LO_CSR addr_low;
+ } SG_PACK; /* unnamed struct */
+ u32 dw[4]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_22_MESSAGE, *PPCICFG_ANON_22_MESSAGE;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_22_MESSAGE,
+ sizeof(PCICFG_ANON_22_MESSAGE) == 16);
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _PCICFG_ANON_23_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[895]; /* DWORDS 1 to 895 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[896]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_23_RSVD, *PPCICFG_ANON_23_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_23_RSVD,
+ sizeof(PCICFG_ANON_23_RSVD) == 3584);
+
+#else
+
+typedef struct _PCICFG_ANON_23_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[895]; /* DWORDS 1 to 895 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[896]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_23_RSVD, *PPCICFG_ANON_23_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_23_RSVD,
+ sizeof(PCICFG_ANON_23_RSVD) == 3584);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * These PCI Configuration Space registers are for the Storage Function
+ * of BladeEngine (Function 0). In the memory map of the registers
+ * below their table, registers that are physically common to Functions
+ * 0 and 1 are highlighted in pink.<BR> under the mnemonic column.
+ *
+ */
+typedef struct _PCICFG0_CSRMAP {
+ union {
+ struct {
+ PCICFG_ID_CSR id;
+ u32 rsvd0[1]; /* DWORDS 1 to 1 */
+ u32 rsvd1[1]; /* DWORDS 2 to 2 */
+ u32 rsvd2[1]; /* DWORDS 3 to 3 */
+ PCICFG_IOBAR_CSR iobar;
+ PCICFG_MEMBAR0_CSR membar0;
+ PCICFG_MEMBAR1_LO_CSR membar1_lo;
+ PCICFG_MEMBAR1_HI_CSR membar1_hi;
+ PCICFG_MEMBAR2_LO_CSR membar2_lo;
+ PCICFG_MEMBAR2_HI_CSR membar2_hi;
+ u32 rsvd3[1]; /* DWORDS 10 to 10 */
+ PCICFG_SUBSYSTEM_ID_F0_CSR subsystem_id;
+ u32 rsvd4[1]; /* DWORDS 12 to 12 */
+ u32 rsvd5[1]; /* DWORDS 13 to 13 */
+ u32 rsvd6[1]; /* DWORDS 14 to 14 */
+ u32 rsvd7[1]; /* DWORDS 15 to 15 */
+ PCICFG_SEMAPHORE_CSR semaphore[4];
+ PCICFG_SOFT_RESET_CSR soft_reset;
+ u32 rsvd8[1]; /* DWORDS 21 to 21 */
+ PCICFG_SCRATCHPAD_CSR scratchpad;
+ u32 rsvd9[1]; /* DWORDS 23 to 23 */
+ u32 rsvd10[1]; /* DWORDS 24 to 24 */
+ u32 rsvd11[1]; /* DWORDS 25 to 25 */
+ u32 rsvd12[1]; /* DWORDS 26 to 26 */
+ u32 rsvd13[1]; /* DWORDS 27 to 27 */
+ u32 rsvd14[2]; /* DWORDS 28 to 29 */
+ u32 rsvd15[1]; /* DWORDS 30 to 30 */
+ u32 rsvd16[1]; /* DWORDS 31 to 31 */
+ u32 rsvd17[8]; /* DWORDS 32 to 39 */
+ PCICFG_UE_STATUS_LOW_CSR ue_status_low;
+ PCICFG_UE_STATUS_HI_CSR ue_status_hi;
+ PCICFG_UE_STATUS_LOW_MASK_CSR ue_status_low_mask;
+ PCICFG_UE_STATUS_HI_MASK_CSR ue_status_hi_mask;
+ PCICFG_ONLINE0_CSR online0;
+ PCICFG_ONLINE1_CSR online1;
+ u32 rsvd18[1]; /* DWORDS 46 to 46 */
+ u32 rsvd19[1]; /* DWORDS 47 to 47 */
+ u32 rsvd20[1]; /* DWORDS 48 to 48 */
+ u32 rsvd21[1]; /* DWORDS 49 to 49 */
+ PCICFG_HOST_TIMER_INT_CTRL_CSR host_timer_int_ctrl;
+ u32 rsvd22[1]; /* DWORDS 51 to 51 */
+ PCICFG_PCIE_CAP_CSR pcie_cap;
+ PCICFG_PCIE_DEVCAP_CSR pcie_devcap;
+ PCICFG_PCIE_CONTROL_STATUS_CSR pcie_control_status;
+ PCICFG_PCIE_LINK_CAP_CSR pcie_link_cap;
+ PCICFG_PCIE_LINK_STATUS_CSR pcie_link_status;
+ PCICFG_MSI_CSR msi;
+ PCICFG_MSIX_TABLE_CSR msix_table_offset;
+ PCICFG_MSIX_PBA_CSR msix_pba_offset;
+ u32 rsvd23[1]; /* DWORDS 60 to 60 */
+ u32 rsvd24[1]; /* DWORDS 61 to 61 */
+ u32 rsvd25[1]; /* DWORDS 62 to 62 */
+ u32 rsvd26[1]; /* DWORDS 63 to 63 */
+ u32 rsvd27[1]; /* DWORDS 64 to 64 */
+ u32 rsvd28[1]; /* DWORDS 65 to 65 */
+ u32 rsvd29[1]; /* DWORDS 66 to 66 */
+ u32 rsvd30[1]; /* DWORDS 67 to 67 */
+ u32 rsvd31[1]; /* DWORDS 68 to 68 */
+ u32 rsvd32[1]; /* DWORDS 69 to 69 */
+ u32 rsvd33[1]; /* DWORDS 70 to 70 */
+ u32 rsvd34[1]; /* DWORDS 71 to 71 */
+ u32 rsvd35[1]; /* DWORDS 72 to 72 */
+ u32 rsvd36[1]; /* DWORDS 73 to 73 */
+ u32 rsvd37[1]; /* DWORDS 74 to 74 */
+ u32 rsvd38[1]; /* DWORDS 75 to 75 */
+ u32 rsvd39[1]; /* DWORDS 76 to 76 */
+ u32 rsvd40[1]; /* DWORDS 77 to 77 */
+ u32 rsvd41[1]; /* DWORDS 78 to 78 */
+ u32 rsvd42[1]; /* DWORDS 79 to 79 */
+ u32 rsvd43[1]; /* DWORDS 80 to 80 */
+ u32 rsvd44[1]; /* DWORDS 81 to 81 */
+ u32 rsvd45[1]; /* DWORDS 82 to 82 */
+ u32 rsvd46[1]; /* DWORDS 83 to 83 */
+ u32 rsvd47[1]; /* DWORDS 84 to 84 */
+ u32 rsvd48[1]; /* DWORDS 85 to 85 */
+ u32 rsvd49[1]; /* DWORDS 86 to 86 */
+ u32 rsvd50[1]; /* DWORDS 87 to 87 */
+ u32 rsvd51[1]; /* DWORDS 88 to 88 */
+ u32 rsvd52[1]; /* DWORDS 89 to 89 */
+ u32 rsvd53[1]; /* DWORDS 90 to 90 */
+ u32 rsvd54[1]; /* DWORDS 91 to 91 */
+ u32 rsvd55[1]; /* DWORDS 92 to 92 */
+ u32 rsvd56[26]; /* DWORDS 93 to 118 */
+ u32 rsvd57[1]; /* DWORDS 119 to 119 */
+ u32 rsvd58[1]; /* DWORDS 120 to 120 */
+ u32 rsvd59[1]; /* DWORDS 121 to 121 */
+ u32 rsvd60[1]; /* DWORDS 122 to 122 */
+ u32 rsvd61[1]; /* DWORDS 123 to 123 */
+ u32 rsvd62[1]; /* DWORDS 124 to 124 */
+ u32 rsvd63[1]; /* DWORDS 125 to 125 */
+ u32 rsvd64[1]; /* DWORDS 126 to 126 */
+ u32 rsvd65[1]; /* DWORDS 127 to 127 */
+ u32 rsvd66[1920]; /* DWORDS 128 to 2047 */
+ PCICFG_ANON_22_MESSAGE message[32];
+ u32 rsvd67[896]; /* DWORDS 2176 to 3071 */
+ u32 rsvd68[1]; /* DWORDS 3072 to 3072 */
+ u32 rsvd69[1023]; /* DWORDS 3073 to 4095 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[4096]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG0_CSRMAP, *PPCICFG0_CSRMAP;
+
+SG_C_ASSERT(__sizeof__PCICFG0_CSRMAP, sizeof(PCICFG0_CSRMAP) == 16384);
+
+#else
+ /*
+ * These PCI Configuration Space registers are for the Storage Function
+ * of BladeEngine (Function 0). In the memory map of the registers
+ * below their table, registers that are physically common to Functions
+ * 0 and 1 are highlighted in pink.<BR> under the mnemonic column.
+ *
+ */
+typedef struct _PCICFG0_CSRMAP {
+ union {
+ struct {
+ PCICFG_ID_CSR id;
+ u32 rsvd0[1]; /* DWORDS 1 to 1 */
+ u32 rsvd1[1]; /* DWORDS 2 to 2 */
+ u32 rsvd2[1]; /* DWORDS 3 to 3 */
+ PCICFG_IOBAR_CSR iobar;
+ PCICFG_MEMBAR0_CSR membar0;
+ PCICFG_MEMBAR1_LO_CSR membar1_lo;
+ PCICFG_MEMBAR1_HI_CSR membar1_hi;
+ PCICFG_MEMBAR2_LO_CSR membar2_lo;
+ PCICFG_MEMBAR2_HI_CSR membar2_hi;
+ u32 rsvd3[1]; /* DWORDS 10 to 10 */
+ PCICFG_SUBSYSTEM_ID_F0_CSR subsystem_id;
+ u32 rsvd4[1]; /* DWORDS 12 to 12 */
+ u32 rsvd5[1]; /* DWORDS 13 to 13 */
+ u32 rsvd6[1]; /* DWORDS 14 to 14 */
+ u32 rsvd7[1]; /* DWORDS 15 to 15 */
+ PCICFG_SEMAPHORE_CSR semaphore[4];
+ PCICFG_SOFT_RESET_CSR soft_reset;
+ u32 rsvd8[1]; /* DWORDS 21 to 21 */
+ PCICFG_SCRATCHPAD_CSR scratchpad;
+ u32 rsvd9[1]; /* DWORDS 23 to 23 */
+ u32 rsvd10[1]; /* DWORDS 24 to 24 */
+ u32 rsvd11[1]; /* DWORDS 25 to 25 */
+ u32 rsvd12[1]; /* DWORDS 26 to 26 */
+ u32 rsvd13[1]; /* DWORDS 27 to 27 */
+ u32 rsvd14[2]; /* DWORDS 28 to 29 */
+ u32 rsvd15[1]; /* DWORDS 30 to 30 */
+ u32 rsvd16[1]; /* DWORDS 31 to 31 */
+ u32 rsvd17[8]; /* DWORDS 32 to 39 */
+ PCICFG_UE_STATUS_LOW_CSR ue_status_low;
+ PCICFG_UE_STATUS_HI_CSR ue_status_hi;
+ PCICFG_UE_STATUS_LOW_MASK_CSR ue_status_low_mask;
+ PCICFG_UE_STATUS_HI_MASK_CSR ue_status_hi_mask;
+ PCICFG_ONLINE0_CSR online0;
+ PCICFG_ONLINE1_CSR online1;
+ u32 rsvd18[1]; /* DWORDS 46 to 46 */
+ u32 rsvd19[1]; /* DWORDS 47 to 47 */
+ u32 rsvd20[1]; /* DWORDS 48 to 48 */
+ u32 rsvd21[1]; /* DWORDS 49 to 49 */
+ PCICFG_HOST_TIMER_INT_CTRL_CSR host_timer_int_ctrl;
+ u32 rsvd22[1]; /* DWORDS 51 to 51 */
+ PCICFG_PCIE_CAP_CSR pcie_cap;
+ PCICFG_PCIE_DEVCAP_CSR pcie_devcap;
+ PCICFG_PCIE_CONTROL_STATUS_CSR pcie_control_status;
+ PCICFG_PCIE_LINK_CAP_CSR pcie_link_cap;
+ PCICFG_PCIE_LINK_STATUS_CSR pcie_link_status;
+ PCICFG_MSI_CSR msi;
+ PCICFG_MSIX_TABLE_CSR msix_table_offset;
+ PCICFG_MSIX_PBA_CSR msix_pba_offset;
+ u32 rsvd23[1]; /* DWORDS 60 to 60 */
+ u32 rsvd24[1]; /* DWORDS 61 to 61 */
+ u32 rsvd25[1]; /* DWORDS 62 to 62 */
+ u32 rsvd26[1]; /* DWORDS 63 to 63 */
+ u32 rsvd27[1]; /* DWORDS 64 to 64 */
+ u32 rsvd28[1]; /* DWORDS 65 to 65 */
+ u32 rsvd29[1]; /* DWORDS 66 to 66 */
+ u32 rsvd30[1]; /* DWORDS 67 to 67 */
+ u32 rsvd31[1]; /* DWORDS 68 to 68 */
+ u32 rsvd32[1]; /* DWORDS 69 to 69 */
+ u32 rsvd33[1]; /* DWORDS 70 to 70 */
+ u32 rsvd34[1]; /* DWORDS 71 to 71 */
+ u32 rsvd35[1]; /* DWORDS 72 to 72 */
+ u32 rsvd36[1]; /* DWORDS 73 to 73 */
+ u32 rsvd37[1]; /* DWORDS 74 to 74 */
+ u32 rsvd38[1]; /* DWORDS 75 to 75 */
+ u32 rsvd39[1]; /* DWORDS 76 to 76 */
+ u32 rsvd40[1]; /* DWORDS 77 to 77 */
+ u32 rsvd41[1]; /* DWORDS 78 to 78 */
+ u32 rsvd42[1]; /* DWORDS 79 to 79 */
+ u32 rsvd43[1]; /* DWORDS 80 to 80 */
+ u32 rsvd44[1]; /* DWORDS 81 to 81 */
+ u32 rsvd45[1]; /* DWORDS 82 to 82 */
+ u32 rsvd46[1]; /* DWORDS 83 to 83 */
+ u32 rsvd47[1]; /* DWORDS 84 to 84 */
+ u32 rsvd48[1]; /* DWORDS 85 to 85 */
+ u32 rsvd49[1]; /* DWORDS 86 to 86 */
+ u32 rsvd50[1]; /* DWORDS 87 to 87 */
+ u32 rsvd51[1]; /* DWORDS 88 to 88 */
+ u32 rsvd52[1]; /* DWORDS 89 to 89 */
+ u32 rsvd53[1]; /* DWORDS 90 to 90 */
+ u32 rsvd54[1]; /* DWORDS 91 to 91 */
+ u32 rsvd55[1]; /* DWORDS 92 to 92 */
+ u32 rsvd56[26]; /* DWORDS 93 to 118 */
+ u32 rsvd57[1]; /* DWORDS 119 to 119 */
+ u32 rsvd58[1]; /* DWORDS 120 to 120 */
+ u32 rsvd59[1]; /* DWORDS 121 to 121 */
+ u32 rsvd60[1]; /* DWORDS 122 to 122 */
+ u32 rsvd61[1]; /* DWORDS 123 to 123 */
+ u32 rsvd62[1]; /* DWORDS 124 to 124 */
+ u32 rsvd63[1]; /* DWORDS 125 to 125 */
+ u32 rsvd64[1]; /* DWORDS 126 to 126 */
+ u32 rsvd65[1]; /* DWORDS 127 to 127 */
+ u32 rsvd66[1920]; /* DWORDS 128 to 2047 */
+ PCICFG_ANON_22_MESSAGE message[32];
+ u32 rsvd67[896]; /* DWORDS 2176 to 3071 */
+ u32 rsvd68[1]; /* DWORDS 3072 to 3072 */
+ u32 rsvd69[1023]; /* DWORDS 3073 to 4095 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[4096]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG0_CSRMAP, *PPCICFG0_CSRMAP;
+
+SG_C_ASSERT(__sizeof__PCICFG0_CSRMAP, sizeof(PCICFG0_CSRMAP) == 16384);
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _PCICFG_ANON_24_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_24_RSVD, *PPCICFG_ANON_24_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_24_RSVD,
+ sizeof(PCICFG_ANON_24_RSVD) == 4);
+
+#else
+
+typedef struct _PCICFG_ANON_24_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_24_RSVD, *PPCICFG_ANON_24_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_24_RSVD,
+ sizeof(PCICFG_ANON_24_RSVD) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _PCICFG_ANON_25_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_25_RSVD, *PPCICFG_ANON_25_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_25_RSVD,
+ sizeof(PCICFG_ANON_25_RSVD) == 4);
+
+#else
+
+typedef struct _PCICFG_ANON_25_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_25_RSVD, *PPCICFG_ANON_25_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_25_RSVD,
+ sizeof(PCICFG_ANON_25_RSVD) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _PCICFG_ANON_26_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_26_RSVD, *PPCICFG_ANON_26_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_26_RSVD,
+ sizeof(PCICFG_ANON_26_RSVD) == 4);
+
+#else
+
+typedef struct _PCICFG_ANON_26_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_26_RSVD, *PPCICFG_ANON_26_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_26_RSVD,
+ sizeof(PCICFG_ANON_26_RSVD) == 4);
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _PCICFG_ANON_27_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[1]; /* DWORDS 1 to 1 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[2]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_27_RSVD, *PPCICFG_ANON_27_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_27_RSVD,
+ sizeof(PCICFG_ANON_27_RSVD) == 8);
+
+#else
+
+typedef struct _PCICFG_ANON_27_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[1]; /* DWORDS 1 to 1 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[2]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_27_RSVD, *PPCICFG_ANON_27_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_27_RSVD,
+ sizeof(PCICFG_ANON_27_RSVD) == 8);
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _PCICFG_ANON_28_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[3]; /* DWORDS 1 to 3 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[4]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_28_RSVD, *PPCICFG_ANON_28_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_28_RSVD,
+ sizeof(PCICFG_ANON_28_RSVD) == 16);
+
+#else
+
+typedef struct _PCICFG_ANON_28_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[3]; /* DWORDS 1 to 3 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[4]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_28_RSVD, *PPCICFG_ANON_28_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_28_RSVD,
+ sizeof(PCICFG_ANON_28_RSVD) == 16);
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _PCICFG_ANON_29_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[36]; /* DWORDS 1 to 36 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[37]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_29_RSVD, *PPCICFG_ANON_29_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_29_RSVD,
+ sizeof(PCICFG_ANON_29_RSVD) == 148);
+
+#else
+
+typedef struct _PCICFG_ANON_29_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[36]; /* DWORDS 1 to 36 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[37]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_29_RSVD, *PPCICFG_ANON_29_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_29_RSVD,
+ sizeof(PCICFG_ANON_29_RSVD) == 148);
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _PCICFG_ANON_30_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[1930]; /* DWORDS 1 to 1930 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[1931]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_30_RSVD, *PPCICFG_ANON_30_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_30_RSVD,
+ sizeof(PCICFG_ANON_30_RSVD) == 7724);
+
+#else
+
+typedef struct _PCICFG_ANON_30_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[1930]; /* DWORDS 1 to 1930 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[1931]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_30_RSVD, *PPCICFG_ANON_30_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_30_RSVD,
+ sizeof(PCICFG_ANON_30_RSVD) == 7724);
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _PCICFG_ANON_31_MESSAGE {
+ union {
+ struct {
+ PCICFG_MSIX_VECTOR_CONTROL_CSR vec_ctrl;
+ PCICFG_MSIX_MSG_DATA_CSR msg_data;
+ PCICFG_MSIX_MSG_ADDR_HI_CSR addr_hi;
+ PCICFG_MSIX_MSG_ADDR_LO_CSR addr_low;
+ } SG_PACK; /* unnamed struct */
+ u32 dw[4]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_31_MESSAGE, *PPCICFG_ANON_31_MESSAGE;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_31_MESSAGE,
+ sizeof(PCICFG_ANON_31_MESSAGE) == 16);
+
+#else
+
+typedef struct _PCICFG_ANON_31_MESSAGE {
+ union {
+ struct {
+ PCICFG_MSIX_VECTOR_CONTROL_CSR vec_ctrl;
+ PCICFG_MSIX_MSG_DATA_CSR msg_data;
+ PCICFG_MSIX_MSG_ADDR_HI_CSR addr_hi;
+ PCICFG_MSIX_MSG_ADDR_LO_CSR addr_low;
+ } SG_PACK; /* unnamed struct */
+ u32 dw[4]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_31_MESSAGE, *PPCICFG_ANON_31_MESSAGE;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_31_MESSAGE,
+ sizeof(PCICFG_ANON_31_MESSAGE) == 16);
+#endif
+
+#if defined(__BIG_ENDIAN)
+
+typedef struct _PCICFG_ANON_32_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[895]; /* DWORDS 1 to 895 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[896]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_32_RSVD, *PPCICFG_ANON_32_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_32_RSVD,
+ sizeof(PCICFG_ANON_32_RSVD) == 3584);
+
+#else
+
+typedef struct _PCICFG_ANON_32_RSVD {
+ union {
+ struct {
+ u32 rsvd0[1]; /* DWORDS 0 to 0 */
+ u32 rsvd1[895]; /* DWORDS 1 to 895 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[896]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG_ANON_32_RSVD, *PPCICFG_ANON_32_RSVD;
+
+SG_C_ASSERT(__sizeof__PCICFG_ANON_32_RSVD,
+ sizeof(PCICFG_ANON_32_RSVD) == 3584);
+#endif
+
+#if defined(__BIG_ENDIAN)
+ /*
+ * This PCI configuration space register map is for the Networking Function
+ * of BladeEngine (Function 1). For more detailed descriptions of
+ * the fields below click the link under the mnemonic column. Registers
+ * highlighted in pink color are physically shared between both
+ * Functions (0 and 1).
+ */
+typedef struct _PCICFG1_CSRMAP {
+ union {
+ struct {
+ PCICFG_ID_CSR id;
+ u32 rsvd0[1]; /* DWORDS 1 to 1 */
+ u32 rsvd1[1]; /* DWORDS 2 to 2 */
+ u32 rsvd2[1]; /* DWORDS 3 to 3 */
+ PCICFG_IOBAR_CSR iobar;
+ PCICFG_MEMBAR0_CSR membar0;
+ PCICFG_MEMBAR1_LO_CSR membar1_lo;
+ PCICFG_MEMBAR1_HI_CSR membar1_hi;
+ PCICFG_MEMBAR2_LO_CSR membar2_lo;
+ PCICFG_MEMBAR2_HI_CSR membar2_hi;
+ u32 rsvd3[1]; /* DWORDS 10 to 10 */
+ PCICFG_SUBSYSTEM_ID_F1_CSR subsystem_id;
+ u32 rsvd4[1]; /* DWORDS 12 to 12 */
+ u32 rsvd5[1]; /* DWORDS 13 to 13 */
+ u32 rsvd6[1]; /* DWORDS 14 to 14 */
+ u32 rsvd7[1]; /* DWORDS 15 to 15 */
+ PCICFG_SEMAPHORE_CSR semaphore[4];
+ PCICFG_SOFT_RESET_CSR soft_reset;
+ u32 rsvd8[1]; /* DWORDS 21 to 21 */
+ PCICFG_SCRATCHPAD_CSR scratchpad;
+ u32 rsvd9[1]; /* DWORDS 23 to 23 */
+ u32 rsvd10[1]; /* DWORDS 24 to 24 */
+ u32 rsvd11[1]; /* DWORDS 25 to 25 */
+ u32 rsvd12[1]; /* DWORDS 26 to 26 */
+ u32 rsvd13[1]; /* DWORDS 27 to 27 */
+ u32 rsvd14[2]; /* DWORDS 28 to 29 */
+ u32 rsvd15[1]; /* DWORDS 30 to 30 */
+ u32 rsvd16[1]; /* DWORDS 31 to 31 */
+ u32 rsvd17[8]; /* DWORDS 32 to 39 */
+ PCICFG_UE_STATUS_LOW_CSR ue_status_low;
+ PCICFG_UE_STATUS_HI_CSR ue_status_hi;
+ PCICFG_UE_STATUS_LOW_MASK_CSR ue_status_low_mask;
+ PCICFG_UE_STATUS_HI_MASK_CSR ue_status_hi_mask;
+ PCICFG_ONLINE0_CSR online0;
+ PCICFG_ONLINE1_CSR online1;
+ u32 rsvd18[1]; /* DWORDS 46 to 46 */
+ u32 rsvd19[1]; /* DWORDS 47 to 47 */
+ u32 rsvd20[1]; /* DWORDS 48 to 48 */
+ u32 rsvd21[1]; /* DWORDS 49 to 49 */
+ PCICFG_HOST_TIMER_INT_CTRL_CSR host_timer_int_ctrl;
+ u32 rsvd22[1]; /* DWORDS 51 to 51 */
+ PCICFG_PCIE_CAP_CSR pcie_cap;
+ PCICFG_PCIE_DEVCAP_CSR pcie_devcap;
+ PCICFG_PCIE_CONTROL_STATUS_CSR pcie_control_status;
+ PCICFG_PCIE_LINK_CAP_CSR pcie_link_cap;
+ PCICFG_PCIE_LINK_STATUS_CSR pcie_link_status;
+ PCICFG_MSI_CSR msi;
+ PCICFG_MSIX_TABLE_CSR msix_table_offset;
+ PCICFG_MSIX_PBA_CSR msix_pba_offset;
+ u32 rsvd23[2]; /* DWORDS 60 to 61 */
+ u32 rsvd24[1]; /* DWORDS 62 to 62 */
+ u32 rsvd25[1]; /* DWORDS 63 to 63 */
+ u32 rsvd26[1]; /* DWORDS 64 to 64 */
+ u32 rsvd27[1]; /* DWORDS 65 to 65 */
+ u32 rsvd28[1]; /* DWORDS 66 to 66 */
+ u32 rsvd29[1]; /* DWORDS 67 to 67 */
+ u32 rsvd30[1]; /* DWORDS 68 to 68 */
+ u32 rsvd31[1]; /* DWORDS 69 to 69 */
+ u32 rsvd32[1]; /* DWORDS 70 to 70 */
+ u32 rsvd33[1]; /* DWORDS 71 to 71 */
+ u32 rsvd34[1]; /* DWORDS 72 to 72 */
+ u32 rsvd35[1]; /* DWORDS 73 to 73 */
+ u32 rsvd36[1]; /* DWORDS 74 to 74 */
+ u32 rsvd37[4]; /* DWORDS 75 to 78 */
+ u32 rsvd38[1]; /* DWORDS 79 to 79 */
+ u32 rsvd39[37]; /* DWORDS 80 to 116 */
+ u32 rsvd40[1931]; /* DWORDS 117 to 2047 */
+ PCICFG_ANON_31_MESSAGE message[32];
+ u32 rsvd41[896]; /* DWORDS 2176 to 3071 */
+ u32 rsvd42[1]; /* DWORDS 3072 to 3072 */
+ u32 rsvd43[1023]; /* DWORDS 3073 to 4095 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[4096]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG1_CSRMAP, *PPCICFG1_CSRMAP;
+
+SG_C_ASSERT(__sizeof__PCICFG1_CSRMAP, sizeof(PCICFG1_CSRMAP) == 16384);
+
+#else
+ /*
+ * This PCI configuration space register map is for the Networking Function
+ * of BladeEngine (Function 1). For more detailed descriptions of
+ * the fields below click the link under the mnemonic column. Registers
+ * highlighted in pink color are physically shared between both
+ * Functions (0 and 1).
+ */
+typedef struct _PCICFG1_CSRMAP {
+ union {
+ struct {
+ PCICFG_ID_CSR id;
+ u32 rsvd0[1]; /* DWORDS 1 to 1 */
+ u32 rsvd1[1]; /* DWORDS 2 to 2 */
+ u32 rsvd2[1]; /* DWORDS 3 to 3 */
+ PCICFG_IOBAR_CSR iobar;
+ PCICFG_MEMBAR0_CSR membar0;
+ PCICFG_MEMBAR1_LO_CSR membar1_lo;
+ PCICFG_MEMBAR1_HI_CSR membar1_hi;
+ PCICFG_MEMBAR2_LO_CSR membar2_lo;
+ PCICFG_MEMBAR2_HI_CSR membar2_hi;
+ u32 rsvd3[1]; /* DWORDS 10 to 10 */
+ PCICFG_SUBSYSTEM_ID_F1_CSR subsystem_id;
+ u32 rsvd4[1]; /* DWORDS 12 to 12 */
+ u32 rsvd5[1]; /* DWORDS 13 to 13 */
+ u32 rsvd6[1]; /* DWORDS 14 to 14 */
+ u32 rsvd7[1]; /* DWORDS 15 to 15 */
+ PCICFG_SEMAPHORE_CSR semaphore[4];
+ PCICFG_SOFT_RESET_CSR soft_reset;
+ u32 rsvd8[1]; /* DWORDS 21 to 21 */
+ PCICFG_SCRATCHPAD_CSR scratchpad;
+ u32 rsvd9[1]; /* DWORDS 23 to 23 */
+ u32 rsvd10[1]; /* DWORDS 24 to 24 */
+ u32 rsvd11[1]; /* DWORDS 25 to 25 */
+ u32 rsvd12[1]; /* DWORDS 26 to 26 */
+ u32 rsvd13[1]; /* DWORDS 27 to 27 */
+ u32 rsvd14[2]; /* DWORDS 28 to 29 */
+ u32 rsvd15[1]; /* DWORDS 30 to 30 */
+ u32 rsvd16[1]; /* DWORDS 31 to 31 */
+ u32 rsvd17[8]; /* DWORDS 32 to 39 */
+ PCICFG_UE_STATUS_LOW_CSR ue_status_low;
+ PCICFG_UE_STATUS_HI_CSR ue_status_hi;
+ PCICFG_UE_STATUS_LOW_MASK_CSR ue_status_low_mask;
+ PCICFG_UE_STATUS_HI_MASK_CSR ue_status_hi_mask;
+ PCICFG_ONLINE0_CSR online0;
+ PCICFG_ONLINE1_CSR online1;
+ u32 rsvd18[1]; /* DWORDS 46 to 46 */
+ u32 rsvd19[1]; /* DWORDS 47 to 47 */
+ u32 rsvd20[1]; /* DWORDS 48 to 48 */
+ u32 rsvd21[1]; /* DWORDS 49 to 49 */
+ PCICFG_HOST_TIMER_INT_CTRL_CSR host_timer_int_ctrl;
+ u32 rsvd22[1]; /* DWORDS 51 to 51 */
+ PCICFG_PCIE_CAP_CSR pcie_cap;
+ PCICFG_PCIE_DEVCAP_CSR pcie_devcap;
+ PCICFG_PCIE_CONTROL_STATUS_CSR pcie_control_status;
+ PCICFG_PCIE_LINK_CAP_CSR pcie_link_cap;
+ PCICFG_PCIE_LINK_STATUS_CSR pcie_link_status;
+ PCICFG_MSI_CSR msi;
+ PCICFG_MSIX_TABLE_CSR msix_table_offset;
+ PCICFG_MSIX_PBA_CSR msix_pba_offset;
+ u32 rsvd23[2]; /* DWORDS 60 to 61 */
+ u32 rsvd24[1]; /* DWORDS 62 to 62 */
+ u32 rsvd25[1]; /* DWORDS 63 to 63 */
+ u32 rsvd26[1]; /* DWORDS 64 to 64 */
+ u32 rsvd27[1]; /* DWORDS 65 to 65 */
+ u32 rsvd28[1]; /* DWORDS 66 to 66 */
+ u32 rsvd29[1]; /* DWORDS 67 to 67 */
+ u32 rsvd30[1]; /* DWORDS 68 to 68 */
+ u32 rsvd31[1]; /* DWORDS 69 to 69 */
+ u32 rsvd32[1]; /* DWORDS 70 to 70 */
+ u32 rsvd33[1]; /* DWORDS 71 to 71 */
+ u32 rsvd34[1]; /* DWORDS 72 to 72 */
+ u32 rsvd35[1]; /* DWORDS 73 to 73 */
+ u32 rsvd36[1]; /* DWORDS 74 to 74 */
+ u32 rsvd37[4]; /* DWORDS 75 to 78 */
+ u32 rsvd38[1]; /* DWORDS 79 to 79 */
+ u32 rsvd39[37]; /* DWORDS 80 to 116 */
+ u32 rsvd40[1931]; /* DWORDS 117 to 2047 */
+ PCICFG_ANON_31_MESSAGE message[32];
+ u32 rsvd41[896]; /* DWORDS 2176 to 3071 */
+ u32 rsvd42[1]; /* DWORDS 3072 to 3072 */
+ u32 rsvd43[1023]; /* DWORDS 3073 to 4095 */
+ } SG_PACK; /* unnamed struct */
+ u32 dw[4096]; /* dword union */
+ }; /* unnamed union */
+} SG_PACK PCICFG1_CSRMAP, *PPCICFG1_CSRMAP;
+
+SG_C_ASSERT(__sizeof__PCICFG1_CSRMAP, sizeof(PCICFG1_CSRMAP) == 16384);
+#endif
+
+#ifdef SG_PRAGMA_PACK
+#pragma pack(pop)
+#endif
+
+#endif /* __pcicfg_bmap_h__ */
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