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Date: Thu, 15 May 2008 02:44:31 -0700
From: "Subbu Seetharaman" <subbus@...verengines.com>
To: netdev@...r.kernel.org
Subject: [PATCH 11/15] BE NIC driver - f/w header files
Signed-off-by: Subbu Seetharaman <subbus@...verengines.com>
---
drivers/message/beclib/fw/amap/ioctl_common.h | 1614 +++++++++++++++++++++++++
drivers/message/beclib/fw/amap/pcicfg.h | 839 +++++++++++++
2 files changed, 2453 insertions(+), 0 deletions(-)
create mode 100644 drivers/message/beclib/fw/amap/ioctl_common.h
create mode 100644 drivers/message/beclib/fw/amap/pcicfg.h
diff --git a/drivers/message/beclib/fw/amap/ioctl_common.h b/drivers/message/beclib/fw/amap/ioctl_common.h
new file mode 100644
index 0000000..56663eb
--- /dev/null
+++ b/drivers/message/beclib/fw/amap/ioctl_common.h
@@ -0,0 +1,1614 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@...verengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __ioctl_common_amap_h__
+#define __ioctl_common_amap_h__
+#include "ioctl_types.h"
+#include "ioctl_hdr.h"
+#include "ioctl_defs.h"
+#include "host_struct.h"
+
+/* --- PHY_LINK_DUPLEX_ENUM --- */
+#define PHY_LINK_DUPLEX_NONE (0)
+#define PHY_LINK_DUPLEX_HALF (1)
+#define PHY_LINK_DUPLEX_FULL (2)
+
+/* --- PHY_LINK_SPEED_ENUM --- */
+#define PHY_LINK_SPEED_ZERO (0) /* No link. */
+#define PHY_LINK_SPEED_10MBPS (1) /* 10 Mbps */
+#define PHY_LINK_SPEED_100MBPS (2) /* 100 Mbps */
+#define PHY_LINK_SPEED_1GBPS (3) /* 1 Gbps */
+#define PHY_LINK_SPEED_10GBPS (4) /* 10 Gbps */
+
+/* --- PHY_LINK_FAULT_ENUM --- */
+#define PHY_LINK_FAULT_NONE (0) /* No fault status
+ available or detected */
+#define PHY_LINK_FAULT_LOCAL (1) /* Local fault detected */
+#define PHY_LINK_FAULT_REMOTE (2) /* Remote fault detected */
+
+/* --- BE_ULP_MASK --- */
+#define BE_ULP0_MASK (1)
+#define BE_ULP1_MASK (2)
+#define BE_ULP2_MASK (4)
+
+/* --- NTWK_ACTIVE_PORT --- */
+#define NTWK_PORT_A (0) /* Port A is currently active */
+#define NTWK_PORT_B (1) /* Port B is currently active */
+#define NTWK_NO_ACTIVE_PORT (15) /* Both ports have lost link */
+
+/* --- NTWK_LINK_TYPE --- */
+#define NTWK_LINK_TYPE_PHYSICAL (0) /* link up/down event
+ applies to BladeEngine's
+ Physical Ports
+ */
+#define NTWK_LINK_TYPE_VIRTUAL (1) /* Virtual link up/down event
+ reported by BladeExchange.
+ This applies only when the
+ VLD feature is enabled
+ */
+
+struct BE_BE_LINK_STATUS_AMAP {
+ struct BE_UEXACT8_AMAP mac0_duplex;
+ struct BE_UEXACT8_AMAP mac0_speed;
+ struct BE_UEXACT8_AMAP mac1_duplex;
+ struct BE_UEXACT8_AMAP mac1_speed;
+ struct BE_UEXACT8_AMAP mgmt_mac_duplex;
+ struct BE_UEXACT8_AMAP mgmt_mac_speed;
+ struct BE_UEXACT8_AMAP active_port;
+ BE_BIT rsvd0[8]; /* DWORD 1 */
+ struct BE_UEXACT8_AMAP mac0_fault;
+ struct BE_UEXACT8_AMAP mac1_fault;
+ BE_BIT rsvd1[16]; /* DWORD 2 */
+} SG_PACK;
+struct BE_LINK_STATUS_AMAP {
+ u32 dw[3];
+};
+
+struct BE_IOCTL_COMMON_ANON_170_REQUEST_AMAP {
+ BE_BIT rsvd0[32]; /* DWORD 0 */
+} SG_PACK;
+struct IOCTL_COMMON_ANON_170_REQUEST_AMAP {
+ u32 dw[1];
+};
+
+union BE_LINK_STATUS_QUERY_PARAMS_AMAP {
+ struct BE_BE_LINK_STATUS_AMAP response;
+ struct BE_IOCTL_COMMON_ANON_170_REQUEST_AMAP request;
+} SG_PACK;
+struct LINK_STATUS_QUERY_PARAMS_AMAP {
+ u32 dw[3];
+};
+
+/*
+ * Queries the the link status for all ports.
+ * The valid values below DO NOT indicate that a particular duplex
+ * or speed is supported by BladeEngine. These enumerations simply list all
+ * possible duplexes and speeds for any port. Consult BladeEngine product
+ * documentation for the supported parameters.
+ */
+struct BE_IOCTL_COMMON_NTWK_LINK_STATUS_QUERY_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_LINK_STATUS_QUERY_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_NTWK_LINK_STATUS_QUERY_AMAP {
+ u32 dw[7];
+};
+
+/*
+ * --- IOCTL_MAC_TYPE_ENUM ---
+ * This enum defines the types of MAC addresses in the RXF MAC Address Table.
+ */
+#define MAC_ADDRESS_TYPE_STORAGE (0) /* Storage MAC Address */
+#define MAC_ADDRESS_TYPE_NETWORK (1) /* Network MAC Address */
+#define MAC_ADDRESS_TYPE_PD (2) /* Protection Domain MAC Addr */
+#define MAC_ADDRESS_TYPE_MANAGEMENT (3) /* Managment MAC Address */
+
+struct BE_IOCTL_COMMON_ANON_171_REQUEST_AMAP {
+ struct BE_UEXACT8_AMAP type;
+ struct BE_UEXACT8_AMAP port;
+ struct BE_UEXACT8_AMAP mac1;
+ struct BE_UEXACT8_AMAP permanent;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_171_REQUEST_AMAP {
+ u32 dw[1];
+};
+
+struct BE_IOCTL_COMMON_ANON_172_RESPONSE_AMAP {
+ struct BE_MAC_ADDRESS_FORMAT_AMAP mac;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_172_RESPONSE_AMAP {
+ u32 dw[2];
+};
+
+union BE_NTWK_MAC_QUERY_PARAMS_AMAP {
+ struct BE_IOCTL_COMMON_ANON_171_REQUEST_AMAP request;
+ struct BE_IOCTL_COMMON_ANON_172_RESPONSE_AMAP response;
+} SG_PACK;
+struct NTWK_MAC_QUERY_PARAMS_AMAP {
+ u32 dw[2];
+};
+
+/* Queries one MAC address. */
+struct BE_IOCTL_COMMON_NTWK_MAC_QUERY_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_NTWK_MAC_QUERY_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_NTWK_MAC_QUERY_AMAP {
+ u32 dw[6];
+};
+
+struct BE_MAC_SET_PARAMS_IN_AMAP {
+ struct BE_UEXACT8_AMAP type;
+ struct BE_UEXACT8_AMAP port;
+ struct BE_UEXACT8_AMAP mac1;
+ struct BE_UEXACT8_AMAP invalidate;
+ struct BE_MAC_ADDRESS_FORMAT_AMAP mac;
+} SG_PACK;
+struct MAC_SET_PARAMS_IN_AMAP {
+ u32 dw[3];
+};
+
+struct BE_MAC_SET_PARAMS_OUT_AMAP {
+ BE_BIT rsvd0[32]; /* DWORD 0 */
+} SG_PACK;
+struct MAC_SET_PARAMS_OUT_AMAP {
+ u32 dw[1];
+};
+
+union BE_MAC_SET_PARAMS_AMAP {
+ struct BE_MAC_SET_PARAMS_IN_AMAP request;
+ struct BE_MAC_SET_PARAMS_OUT_AMAP response;
+} SG_PACK;
+struct MAC_SET_PARAMS_AMAP {
+ u32 dw[3];
+};
+
+/* Sets a MAC address. */
+struct BE_IOCTL_COMMON_NTWK_MAC_SET_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_MAC_SET_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_NTWK_MAC_SET_AMAP {
+ u32 dw[7];
+};
+
+/* MAC address list. */
+struct BE_NTWK_MULTICAST_MAC_LIST_AMAP {
+ struct BE_UEXACT8_AMAP byte[6];
+} SG_PACK;
+struct NTWK_MULTICAST_MAC_LIST_AMAP {
+ u32 dw[2];
+};
+
+struct BE_IOCTL_COMMON_NTWK_MULTICAST_SET_REQUEST_PAYLOAD_AMAP {
+ struct BE_UEXACT16_AMAP num_mac;
+ struct BE_UEXACT8_AMAP promiscuous;
+ BE_BIT rsvd0[8]; /* DWORD 0 */
+ struct BE_NTWK_MULTICAST_MAC_LIST_AMAP mac[32];
+} SG_PACK;
+struct IOCTL_COMMON_NTWK_MULTICAST_SET_REQUEST_PAYLOAD_AMAP {
+ u32 dw[49];
+};
+
+struct BE_IOCTL_COMMON_ANON_174_RESPONSE_AMAP {
+ BE_BIT rsvd0[32]; /* DWORD 0 */
+} SG_PACK;
+struct IOCTL_COMMON_ANON_174_RESPONSE_AMAP {
+ u32 dw[1];
+};
+
+union BE_IOCTL_COMMON_ANON_173_PARAMS_AMAP {
+ struct BE_IOCTL_COMMON_NTWK_MULTICAST_SET_REQUEST_PAYLOAD_AMAP request;
+ struct BE_IOCTL_COMMON_ANON_174_RESPONSE_AMAP response;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_173_PARAMS_AMAP {
+ u32 dw[49];
+};
+
+/*
+ * Sets multicast address hash. The MPU will merge the MAC address
+ * lists from all clients, including the networking and storage functions.
+ * This ioctl may fail if the final merged list of MAC addresses
+ * exceeds 32 entries.
+ */
+struct BE_IOCTL_COMMON_NTWK_MULTICAST_SET_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_IOCTL_COMMON_ANON_173_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_NTWK_MULTICAST_SET_AMAP {
+ u32 dw[53];
+};
+
+struct BE_IOCTL_COMMON_NTWK_VLAN_CONFIG_REQUEST_PAYLOAD_AMAP {
+ struct BE_UEXACT16_AMAP num_vlan;
+ struct BE_UEXACT8_AMAP promiscuous;
+ BE_BIT rsvd0[8]; /* DWORD 0 */
+ struct BE_UEXACT16_AMAP vlan_tag[32];
+} SG_PACK;
+struct IOCTL_COMMON_NTWK_VLAN_CONFIG_REQUEST_PAYLOAD_AMAP {
+ u32 dw[17];
+};
+
+struct BE_IOCTL_COMMON_ANON_176_RESPONSE_AMAP {
+ BE_BIT rsvd0[32]; /* DWORD 0 */
+} SG_PACK;
+struct IOCTL_COMMON_ANON_176_RESPONSE_AMAP {
+ u32 dw[1];
+};
+
+union BE_IOCTL_COMMON_ANON_175_PARAMS_AMAP {
+ struct BE_IOCTL_COMMON_NTWK_VLAN_CONFIG_REQUEST_PAYLOAD_AMAP request;
+ struct BE_IOCTL_COMMON_ANON_176_RESPONSE_AMAP response;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_175_PARAMS_AMAP {
+ u32 dw[17];
+};
+
+/*
+ * Sets VLAN tag filter. The MPU will merge the VLAN tag list from all
+ * clients, including the networking and storage functions. This ioctl may
+ * fail if the final vlan_tag array (from all functions) is longer than 32
+ * entries.
+ */
+struct BE_IOCTL_COMMON_NTWK_VLAN_CONFIG_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_IOCTL_COMMON_ANON_175_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_NTWK_VLAN_CONFIG_AMAP {
+ u32 dw[21];
+};
+
+struct BE_IOCTL_COMMON_ANON_178_REQUEST_AMAP {
+ struct BE_UEXACT16_AMAP num_pages;
+ struct BE_UEXACT16_AMAP type;
+ struct BE_PHYS_ADDR_AMAP scratch_pa;
+ struct BE_VIRT_ADDR_AMAP sratch_va;
+ struct BE_VIRT_ADDR_AMAP pages_va;
+ struct BE_PHYS_ADDR_AMAP pages[16];
+} SG_PACK;
+struct IOCTL_COMMON_ANON_178_REQUEST_AMAP {
+ u32 dw[39];
+};
+
+struct BE_IOCTL_COMMON_ANON_179_RESPONSE_AMAP {
+ struct BE_UEXACT32_AMAP num_used;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_179_RESPONSE_AMAP {
+ u32 dw[1];
+};
+
+union BE_IOCTL_COMMON_ANON_177_PARAMS_AMAP {
+ struct BE_IOCTL_COMMON_ANON_178_REQUEST_AMAP request;
+ struct BE_IOCTL_COMMON_ANON_179_RESPONSE_AMAP response;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_177_PARAMS_AMAP {
+ u32 dw[39];
+};
+
+/*
+ * Posts template headers buffers. These should be posted
+ * before any connections are offloaded. Each buffer holds 32 template
+ * headers at 128 bytes each. This may be issued multiple
+ * times to post the template header buffers in smaller pieces. This allows
+ * the driver to delay allocating template header buffers until the
+ * connections are actually used.
+ * Only protection domain 0 may post template header buffers.
+ */
+struct BE_IOCTL_COMMON_ADD_TEMPLATE_HEADER_BUFFERS_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_IOCTL_COMMON_ANON_177_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_ADD_TEMPLATE_HEADER_BUFFERS_AMAP {
+ u32 dw[43];
+};
+
+struct BE_IOCTL_COMMON_ANON_181_REQUEST_AMAP {
+ struct BE_UEXACT16_AMAP type;
+ BE_BIT rsvd0[16]; /* DWORD 0 */
+} SG_PACK;
+struct IOCTL_COMMON_ANON_181_REQUEST_AMAP {
+ u32 dw[1];
+};
+
+struct BE_IOCTL_COMMON_ANON_182_RESPONSE_AMAP {
+ struct BE_UEXACT32_AMAP num_removed;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_182_RESPONSE_AMAP {
+ u32 dw[1];
+};
+
+union BE_IOCTL_COMMON_ANON_180_PARAMS_AMAP {
+ struct BE_IOCTL_COMMON_ANON_181_REQUEST_AMAP request;
+ struct BE_IOCTL_COMMON_ANON_182_RESPONSE_AMAP response;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_180_PARAMS_AMAP {
+ u32 dw[1];
+};
+
+/*
+ * Frees all template header buffers for the given type. Only protection
+ * domain 0 may issue this request. The IOCTL may fail if any rings which
+ * use these template headers are still in use.
+ */
+struct BE_IOCTL_COMMON_REMOVE_TEMPLATE_HEADER_BUFFERS_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_IOCTL_COMMON_ANON_180_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_REMOVE_TEMPLATE_HEADER_BUFFERS_AMAP {
+ u32 dw[5];
+};
+
+struct BE_IOCTL_COMMON_ANON_184_REQUEST_AMAP {
+ struct BE_UEXACT16_AMAP num;
+ struct BE_UEXACT8_AMAP shared;
+ BE_BIT rsvd0[8]; /* DWORD 0 */
+ struct BE_VIRT_ADDR_AMAP va;
+ struct BE_PHYS_ADDR_AMAP page_tables[26];
+} SG_PACK;
+struct IOCTL_COMMON_ANON_184_REQUEST_AMAP {
+ u32 dw[55];
+};
+
+struct BE_IOCTL_COMMON_ANON_185_RESPONSE_AMAP {
+ struct BE_UEXACT16_AMAP num_added;
+ struct BE_UEXACT16_AMAP num_total;
+ struct BE_UEXACT16_AMAP num_free;
+ BE_BIT rsvd0[16]; /* DWORD 1 */
+} SG_PACK;
+struct IOCTL_COMMON_ANON_185_RESPONSE_AMAP {
+ u32 dw[2];
+};
+
+union BE_IOCTL_COMMON_ANON_183_PARAMS_AMAP {
+ struct BE_IOCTL_COMMON_ANON_184_REQUEST_AMAP request;
+ struct BE_IOCTL_COMMON_ANON_185_RESPONSE_AMAP response;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_183_PARAMS_AMAP {
+ u32 dw[55];
+};
+
+/*
+ * Posts page tables for the UT. This command may be issued multiple times
+ * to add page tables to the chip.
+ */
+struct BE_IOCTL_COMMON_ADD_PAGE_TABLES_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_IOCTL_COMMON_ANON_183_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_ADD_PAGE_TABLES_AMAP {
+ u32 dw[59];
+};
+
+struct BE_IOCTL_COMMON_ANON_187_REQUEST_AMAP {
+ struct BE_UEXACT16_AMAP num;
+ BE_BIT rsvd0[16]; /* DWORD 0 */
+} SG_PACK;
+struct IOCTL_COMMON_ANON_187_REQUEST_AMAP {
+ u32 dw[1];
+};
+
+struct BE_IOCTL_COMMON_ANON_188_RESPONSE_AMAP {
+ struct BE_UEXACT16_AMAP actual_num;
+ struct BE_UEXACT16_AMAP total_num;
+ struct BE_PHYS_ADDR_AMAP page_tables[27];
+} SG_PACK;
+struct IOCTL_COMMON_ANON_188_RESPONSE_AMAP {
+ u32 dw[55];
+};
+
+union BE_IOCTL_COMMON_ANON_186_PARAMS_AMAP {
+ struct BE_IOCTL_COMMON_ANON_187_REQUEST_AMAP request;
+ struct BE_IOCTL_COMMON_ANON_188_RESPONSE_AMAP response;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_186_PARAMS_AMAP {
+ u32 dw[55];
+};
+
+/*
+ * Removes free page tables from the chip. Only page tables that are unused
+ * may be removed. Page tables may not be removed in the same order as they
+ * are posted. This ioctl returns a list of physical addresses for the page
+ * tables that were removed.
+ */
+struct BE_IOCTL_COMMON_REMOVE_PAGE_TABLES_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_IOCTL_COMMON_ANON_186_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_REMOVE_PAGE_TABLES_AMAP {
+ u32 dw[59];
+};
+
+/* --- IOCTL_RING_TYPE_ENUM --- */
+#define IOCTL_RING_TYPE_ETH_RX (1) /* Ring created with */
+ /* IOCTL_COMMON_ETH_RX_CREATE. */
+#define IOCTL_RING_TYPE_ETH_TX (2) /* Ring created with */
+ /* IOCTL_COMMON_ETH_TX_CREATE. */
+#define IOCTL_RING_TYPE_ISCSI_WRBQ (3) /* Ring created with */
+ /* IOCTL_COMMON_ISCSI_WRBQ_CREATE. */
+#define IOCTL_RING_TYPE_ISCSI_DEFQ (4) /* Ring created with */
+ /* IOCTL_COMMON_ISCSI_DEFQ_CREATE. */
+#define IOCTL_RING_TYPE_TPM_WRBQ (5) /* Ring created with */
+ /* IOCTL_COMMON_TPM_WRBQ_CREATE. */
+#define IOCTL_RING_TYPE_TPM_DEFQ (6) /* Ring created with */
+ /* IOCTL_COMMONTPM_TDEFQ_CREATE. */
+#define IOCTL_RING_TYPE_TPM_RQ (7) /* Ring created with */
+ /* IOCTL_COMMON_TPM_RQ_CREATE. */
+#define IOCTL_RING_TYPE_MCC (8) /* Ring created with */
+ /* IOCTL_COMMON_MCC_CREATE. */
+#define IOCTL_RING_TYPE_CQ (9) /* Ring created with */
+ /* IOCTL_COMMON_CQ_CREATE. */
+#define IOCTL_RING_TYPE_EQ (10) /* Ring created with */
+ /* IOCTL_COMMON_EQ_CREATE. */
+#define IOCTL_RING_TYPE_QP (11) /* Ring created with */
+ /* IOCTL_RDMA_QP_CREATE. */
+
+struct BE_RING_DESTROY_REQUEST_AMAP {
+ struct BE_UEXACT16_AMAP ring_type;
+ struct BE_UEXACT16_AMAP id;
+ struct BE_UEXACT8_AMAP bypass_flush;
+ BE_BIT rsvd0[8]; /* DWORD 1 */
+ BE_BIT rsvd1[16]; /* DWORD 1 */
+} SG_PACK;
+struct RING_DESTROY_REQUEST_AMAP {
+ u32 dw[2];
+};
+
+struct BE_IOCTL_COMMON_ANON_190_RESPONSE_AMAP {
+ BE_BIT rsvd0[32]; /* DWORD 0 */
+} SG_PACK;
+struct IOCTL_COMMON_ANON_190_RESPONSE_AMAP {
+ u32 dw[1];
+};
+
+union BE_IOCTL_COMMON_ANON_189_PARAMS_AMAP {
+ struct BE_RING_DESTROY_REQUEST_AMAP request;
+ struct BE_IOCTL_COMMON_ANON_190_RESPONSE_AMAP response;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_189_PARAMS_AMAP {
+ u32 dw[2];
+};
+
+/*
+ * IOCTL for destroying any ring. The connection(s) using the ring should
+ * be quiesced before destroying the ring.
+ */
+struct BE_IOCTL_COMMON_RING_DESTROY_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_IOCTL_COMMON_ANON_189_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_RING_DESTROY_AMAP {
+ u32 dw[6];
+};
+
+struct BE_IOCTL_COMMON_ANON_192_REQUEST_AMAP {
+ struct BE_UEXACT16_AMAP num_pages;
+ BE_BIT rsvd0[16]; /* DWORD 0 */
+ struct BE_CQ_CONTEXT_AMAP context;
+ struct BE_PHYS_ADDR_AMAP pages[4];
+} SG_PACK;
+struct IOCTL_COMMON_ANON_192_REQUEST_AMAP {
+ u32 dw[11];
+};
+
+struct BE_IOCTL_COMMON_ANON_193_RESPONSE_AMAP {
+ struct BE_UEXACT16_AMAP cq_id;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_193_RESPONSE_AMAP {
+ u32 dw[1];
+};
+
+union BE_IOCTL_COMMON_ANON_191_PARAMS_AMAP {
+ struct BE_IOCTL_COMMON_ANON_192_REQUEST_AMAP request;
+ struct BE_IOCTL_COMMON_ANON_193_RESPONSE_AMAP response;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_191_PARAMS_AMAP {
+ u32 dw[11];
+};
+
+/*
+ * IOCTL for creating a completion queue. A Completion Queue must span
+ * at least 1 page and at most 4 pages. Each completion queue entry
+ * is 16 bytes regardless of CQ entry format. Thus the ring must be at
+ * least 256 entries deep (corresponding to 1 page) and can be at most 1024
+ * entries deep (corresponding to 4 pages). The number of pages posted must
+ * contain the CQ ring size as encoded in the context.
+ */
+struct BE_IOCTL_COMMON_CQ_CREATE_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_IOCTL_COMMON_ANON_191_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_CQ_CREATE_AMAP {
+ u32 dw[15];
+};
+
+struct BE_IOCTL_COMMON_ANON_195_REQUEST_AMAP {
+ struct BE_UEXACT16_AMAP num_pages;
+ struct BE_UEXACT16_AMAP new_cq_len;
+ struct BE_UEXACT32_AMAP cq_threshold;
+ struct BE_PHYS_ADDR_AMAP pages[8];
+} SG_PACK;
+struct IOCTL_COMMON_ANON_195_REQUEST_AMAP {
+ u32 dw[18];
+};
+
+struct BE_IOCTL_COMMON_ANON_196_RESPONSE_AMAP {
+ struct BE_UEXACT16_AMAP pidx_old;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_196_RESPONSE_AMAP {
+ u32 dw[1];
+};
+
+union BE_IOCTL_COMMON_ANON_194_PARAMS_AMAP {
+ struct BE_IOCTL_COMMON_ANON_195_REQUEST_AMAP request;
+ struct BE_IOCTL_COMMON_ANON_196_RESPONSE_AMAP response;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_194_PARAMS_AMAP {
+ u32 dw[18];
+};
+
+/*
+ * IOCTL to modify select attributes of a completion queue without needing to
+ * destroy and create a new one.
+ */
+struct BE_IOCTL_COMMON_CQ_MODIFY_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_IOCTL_COMMON_ANON_194_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_CQ_MODIFY_AMAP {
+ u32 dw[22];
+};
+
+struct BE_IOCTL_COMMON_ANON_198_REQUEST_AMAP {
+ struct BE_UEXACT16_AMAP num_pages;
+ BE_BIT rsvd0[16]; /* DWORD 0 */
+ struct BE_EQ_CONTEXT_AMAP context;
+ struct BE_PHYS_ADDR_AMAP pages[8];
+} SG_PACK;
+struct IOCTL_COMMON_ANON_198_REQUEST_AMAP {
+ u32 dw[21];
+};
+
+struct BE_IOCTL_COMMON_ANON_199_RESPONSE_AMAP {
+ struct BE_UEXACT16_AMAP eq_id;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_199_RESPONSE_AMAP {
+ u32 dw[1];
+};
+
+union BE_IOCTL_COMMON_ANON_197_PARAMS_AMAP {
+ struct BE_IOCTL_COMMON_ANON_198_REQUEST_AMAP request;
+ struct BE_IOCTL_COMMON_ANON_199_RESPONSE_AMAP response;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_197_PARAMS_AMAP {
+ u32 dw[21];
+};
+
+/*
+ * IOCTL for creating a event queue. An Event Queue must span
+ * at least 1 page and at most 8 pages. The number of pages posted must
+ * contain the EQ ring. The ring is defined by the size of the EQ entries
+ * (encoded in the context) and the number of EQ entries (also encoded in the
+ * context).
+ */
+struct BE_IOCTL_COMMON_EQ_CREATE_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_IOCTL_COMMON_ANON_197_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_EQ_CREATE_AMAP {
+ u32 dw[25];
+};
+
+struct BE_IOCTL_COMMON_ANON_201_REQUEST_AMAP {
+ struct BE_UEXACT16_AMAP cq_id;
+ struct BE_UEXACT16_AMAP bcmc_cq_id;
+ struct BE_UEXACT16_AMAP num_pages;
+ BE_BIT rsvd0[16]; /* DWORD 1 */
+ struct BE_PHYS_ADDR_AMAP pages[2];
+} SG_PACK;
+struct IOCTL_COMMON_ANON_201_REQUEST_AMAP {
+ u32 dw[6];
+};
+
+struct BE_IOCTL_COMMON_ANON_202_RESPONSE_AMAP {
+ struct BE_UEXACT16_AMAP id;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_202_RESPONSE_AMAP {
+ u32 dw[1];
+};
+
+union BE_IOCTL_COMMON_ANON_200_PARAMS_AMAP {
+ struct BE_IOCTL_COMMON_ANON_201_REQUEST_AMAP request;
+ struct BE_IOCTL_COMMON_ANON_202_RESPONSE_AMAP response;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_200_PARAMS_AMAP {
+ u32 dw[6];
+};
+
+/*
+ * IOCTL for creating Ethernet receive ring.
+ * An ERX ring contains [link]ETH_RX_D[/link] entries (8 bytes each).
+ * An ERX ring must be 1024 entries deep (corresponding to 2 pages).
+ */
+struct BE_IOCTL_COMMON_ETH_RX_CREATE_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_IOCTL_COMMON_ANON_200_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_ETH_RX_CREATE_AMAP {
+ u32 dw[10];
+};
+
+/* --- ETH_TX_RING_TYPE_ENUM --- */
+#define ETH_TX_RING_TYPE_FORWARDING (1) /* Ethernet ring for
+ forwarding packets */
+#define ETH_TX_RING_TYPE_STANDARD (2) /* Ethernet ring for sending
+ network packets. */
+#define ETH_TX_RING_TYPE_BOUND (3) /* Ethernet ring bound to the
+ port specified in the IOCTL
+ header.port_number field.
+ Rings of this type are
+ NOT subject to the
+ failover logic implemented
+ in the BladeEngine.
+ */
+
+struct BE_IOCTL_COMMON_ANON_204_REQUEST_AMAP {
+ struct BE_UEXACT16_AMAP num_pages;
+ struct BE_UEXACT8_AMAP ulp_num;
+ struct BE_UEXACT8_AMAP type;
+ struct BE_ETX_CONTEXT_AMAP context;
+ struct BE_PHYS_ADDR_AMAP pages[8];
+} SG_PACK;
+struct IOCTL_COMMON_ANON_204_REQUEST_AMAP {
+ u32 dw[33];
+};
+
+struct BE_IOCTL_COMMON_ANON_205_RESPONSE_AMAP {
+ struct BE_UEXACT16_AMAP cid;
+ struct BE_UEXACT8_AMAP ulp_num;
+ BE_BIT rsvd0[8]; /* DWORD 0 */
+} SG_PACK;
+struct IOCTL_COMMON_ANON_205_RESPONSE_AMAP {
+ u32 dw[1];
+};
+
+union BE_IOCTL_COMMON_ANON_203_PARAMS_AMAP {
+ struct BE_IOCTL_COMMON_ANON_204_REQUEST_AMAP request;
+ struct BE_IOCTL_COMMON_ANON_205_RESPONSE_AMAP response;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_203_PARAMS_AMAP {
+ u32 dw[33];
+};
+
+/*
+ * IOCTL for creating an Ethernet transmit ring.
+ * An ETX ring contains [link]ETH_WRB[/link] entries (16 bytes each).
+ * An ETX ring must be at least 256 entries deep (corresponding to 1 page)
+ * and at most 2k entries deep (corresponding to 8 pages).
+ */
+struct BE_IOCTL_COMMON_ETH_TX_CREATE_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_IOCTL_COMMON_ANON_203_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_ETH_TX_CREATE_AMAP {
+ u32 dw[37];
+};
+
+struct BE_IOCTL_COMMON_ANON_222_REQUEST_AMAP {
+ struct BE_UEXACT16_AMAP num_pages;
+ BE_BIT rsvd0[16]; /* DWORD 0 */
+ struct BE_MCC_RING_CONTEXT_AMAP context;
+ struct BE_PHYS_ADDR_AMAP pages[8];
+} SG_PACK;
+struct IOCTL_COMMON_ANON_222_REQUEST_AMAP {
+ u32 dw[21];
+};
+
+struct BE_IOCTL_COMMON_ANON_223_RESPONSE_AMAP {
+ struct BE_UEXACT16_AMAP id;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_223_RESPONSE_AMAP {
+ u32 dw[1];
+};
+union BE_IOCTL_COMMON_ANON_221_PARAMS_AMAP {
+ struct BE_IOCTL_COMMON_ANON_222_REQUEST_AMAP request;
+ struct BE_IOCTL_COMMON_ANON_223_RESPONSE_AMAP response;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_221_PARAMS_AMAP {
+ u32 dw[21];
+};
+
+/*
+ * IOCTL for creating the MCC ring. An MCC ring
+ * must be at least 16 entries deep (corresponding to 1 page) and at most 128
+ * entries deep (corresponding to 8 pages).
+ */
+struct BE_IOCTL_COMMON_MCC_CREATE_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_IOCTL_COMMON_ANON_221_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_MCC_CREATE_AMAP {
+ u32 dw[25];
+};
+
+struct BE_GET_QOS_IN_AMAP {
+ struct BE_UEXACT32_AMAP qos_params_rsvd;
+} SG_PACK;
+struct GET_QOS_IN_AMAP {
+ u32 dw[1];
+};
+
+struct BE_GET_QOS_OUT_AMAP {
+ struct BE_UEXACT32_AMAP max_bits_per_second_NIC;
+ struct BE_UEXACT32_AMAP max_packets_per_second_NIC;
+ struct BE_UEXACT32_AMAP max_ios_per_second_iSCSI;
+ struct BE_UEXACT32_AMAP max_bytes_per_second_iSCSI;
+ struct BE_UEXACT16_AMAP domain_VLAN_tag;
+ struct BE_UEXACT16_AMAP fabric_domain_ID;
+ struct BE_UEXACT32_AMAP qos_params_oem[4];
+} SG_PACK;
+struct GET_QOS_OUT_AMAP {
+ u32 dw[9];
+};
+
+union BE_GET_QOS_PARAMS_AMAP {
+ struct BE_GET_QOS_IN_AMAP request;
+ struct BE_GET_QOS_OUT_AMAP response;
+} SG_PACK;
+struct GET_QOS_PARAMS_AMAP {
+ u32 dw[9];
+};
+
+/* QOS/Bandwidth settings per domain. Applicable only in VMs. */
+struct BE_IOCTL_COMMON_GET_QOS_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_GET_QOS_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_GET_QOS_AMAP {
+ u32 dw[13];
+};
+
+/* --- IOCTL_COMMON_QOS_TYPE_ENUM --- */
+#define QOS_BITS_NIC (1) /* max_bits_per_second_NIC */
+ /* field is valid. */
+#define QOS_PKTS_NIC (2) /* max_packets_per_second_NIC */
+ /* field is valid. */
+#define QOS_IOPS_ISCSI (4) /* max_ios_per_second_iSCSI */
+ /*field is valid. */
+#define QOS_VLAN_TAG (8) /* domain_VLAN_tag field
+ is valid. */
+#define QOS_FABRIC_ID (16) /* fabric_domain_ID field
+ is valid. */
+#define QOS_OEM_PARAMS (32) /* qos_params_oem field
+ is valid. */
+#define QOS_TPUT_ISCSI (64) /* max_bytes_per_second_iSCSI
+ field is valid. */
+
+struct BE_SET_QOS_IN_AMAP {
+ struct BE_UEXACT32_AMAP valid_flags;
+ struct BE_UEXACT32_AMAP max_bits_per_second_NIC;
+ struct BE_UEXACT32_AMAP max_packets_per_second_NIC;
+ struct BE_UEXACT32_AMAP max_ios_per_second_iSCSI;
+ struct BE_UEXACT32_AMAP max_bytes_per_second_iSCSI;
+ struct BE_UEXACT16_AMAP domain_VLAN_tag;
+ struct BE_UEXACT16_AMAP fabric_domain_ID;
+ struct BE_UEXACT32_AMAP qos_params_oem[4];
+} SG_PACK;
+struct SET_QOS_IN_AMAP {
+ u32 dw[10];
+};
+
+struct BE_SET_QOS_OUT_AMAP {
+ struct BE_UEXACT32_AMAP qos_params_rsvd;
+} SG_PACK;
+struct SET_QOS_OUT_AMAP {
+ u32 dw[1];
+};
+
+union BE_SET_QOS_PARAMS_AMAP {
+ struct BE_SET_QOS_IN_AMAP request;
+ struct BE_SET_QOS_OUT_AMAP response;
+} SG_PACK;
+struct SET_QOS_PARAMS_AMAP {
+ u32 dw[10];
+};
+
+/* QOS/Bandwidth settings per domain. Applicable only in VMs. */
+struct BE_IOCTL_COMMON_SET_QOS_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_SET_QOS_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_SET_QOS_AMAP {
+ u32 dw[14];
+};
+
+struct BE_SET_FRAME_SIZE_IN_AMAP {
+ struct BE_UEXACT32_AMAP max_tx_frame_size;
+ struct BE_UEXACT32_AMAP max_rx_frame_size;
+} SG_PACK;
+struct SET_FRAME_SIZE_IN_AMAP {
+ u32 dw[2];
+};
+
+struct BE_SET_FRAME_SIZE_OUT_AMAP {
+ struct BE_UEXACT32_AMAP chip_max_tx_frame_size;
+ struct BE_UEXACT32_AMAP chip_max_rx_frame_size;
+} SG_PACK;
+struct SET_FRAME_SIZE_OUT_AMAP {
+ u32 dw[2];
+};
+
+union BE_SET_FRAME_SIZE_PARAMS_AMAP {
+ struct BE_SET_FRAME_SIZE_IN_AMAP request;
+ struct BE_SET_FRAME_SIZE_OUT_AMAP response;
+} SG_PACK;
+struct SET_FRAME_SIZE_PARAMS_AMAP {
+ u32 dw[2];
+};
+
+/* Set frame size IOCTL. Only host domain may issue this IOCTL. */
+struct BE_IOCTL_COMMON_SET_FRAME_SIZE_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_SET_FRAME_SIZE_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_SET_FRAME_SIZE_AMAP {
+ u32 dw[6];
+};
+
+/*
+ * --- FAILOVER_CONFIG_ENUM ---
+ * Failover configuration setting used in IOCTL_COMMON_FORCE_FAILOVER
+ */
+#define FAILOVER_CONFIG_NO_CHANGE (0) /* No change to automatic */
+ /* port failover setting. */
+#define FAILOVER_CONFIG_ON (1) /* Automatic port failover
+ on link down is enabled. */
+#define FAILOVER_CONFIG_OFF (2) /* Automatic port failover
+ on link down is disabled. */
+
+/*
+ * --- FAILOVER_PORT_ENUM ---
+ * Failover port setting used in IOCTL_COMMON_FORCE_FAILOVER
+ */
+#define FAILOVER_PORT_A (0) /* Selects port A. */
+#define FAILOVER_PORT_B (1) /* Selects port B. */
+#define FAILOVER_PORT_NONE (15) /* No port change requested. */
+
+struct BE_FORCE_FAILOVER_IN_AMAP {
+ struct BE_UEXACT32_AMAP move_to_port;
+ struct BE_UEXACT32_AMAP failover_config;
+} SG_PACK;
+struct FORCE_FAILOVER_IN_AMAP {
+ u32 dw[2];
+};
+
+struct BE_IOCTL_COMMON_ANON_231_RESPONSE_AMAP {
+ BE_BIT rsvd0[32]; /* DWORD 0 */
+} SG_PACK;
+struct IOCTL_COMMON_ANON_231_RESPONSE_AMAP {
+ u32 dw[1];
+};
+
+union BE_IOCTL_COMMON_ANON_230_PARAMS_AMAP {
+ struct BE_FORCE_FAILOVER_IN_AMAP request;
+ struct BE_IOCTL_COMMON_ANON_231_RESPONSE_AMAP response;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_230_PARAMS_AMAP {
+ u32 dw[2];
+};
+
+/*
+ * Use this IOCTL to control failover in BladeEngine. It may be used to
+ * failback to a restored port or to forcibly move traffic from one port to
+ * another. It may also be used to enable or disable the automatic failover
+ * feature. This IOCTL can only be issued by domain 0.
+ */
+struct BE_IOCTL_COMMON_FORCE_FAILOVER_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_IOCTL_COMMON_ANON_230_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_FORCE_FAILOVER_AMAP {
+ u32 dw[6];
+};
+
+struct BE_QUERY_MAX_IOCTL_BUFFER_SIZE_PARAMS_OUT_AMAP {
+ struct BE_UEXACT32_AMAP max_ioctl_buffer_size;
+} SG_PACK;
+struct QUERY_MAX_IOCTL_BUFFER_SIZE_PARAMS_OUT_AMAP {
+ u32 dw[1];
+};
+
+/*
+ * IOCTL_QUERY_MAX_IOCTL_BUFFER_SIZE MILI uses this IOCTL to
+ * find out the maximum buffer size that can be accepted by the host OS or the
+ * OSM. During MILI initialization, MILI should send this IOCTL to find out
+ * the maximum IOCTL buffer size allowed. For all the IOCTLs in the future,
+ * MILI should not allocate a buffer larger than this value. In
+ * Windows, the OS doesn't deliver the IOCTL request when the buffer size
+ * allocated by MILI is larger than the maximum I/O size allowed by OSM.
+ */
+struct BE_IOCTL_COMMON_QUERY_MAX_IOCTL_BUFFER_SIZE_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ struct BE_QUERY_MAX_IOCTL_BUFFER_SIZE_PARAMS_OUT_AMAP response;
+} SG_PACK;
+struct IOCTL_COMMON_QUERY_MAX_IOCTL_BUFFER_SIZE_AMAP {
+ u32 dw[5];
+};
+
+/*
+ * --- MGMT_FLASHROM_OPCODE ---
+ * Flash ROM operation code
+ */
+#define MGMT_FLASHROM_OPCODE_FLASH (1) /* Commit downloaded data
+ to Flash ROM */
+#define MGMT_FLASHROM_OPCODE_SAVE (2) /* Save downloaded data to
+ ARM's DDR - do not flash */
+#define MGMT_FLASHROM_OPCODE_CLEAR (3) /* Erase specified component
+ from FlashROM */
+#define MGMT_FLASHROM_OPCODE_REPORT (4) /* Read specified component
+ from Flash ROM */
+#define MGMT_FLASHROM_OPCODE_IMAGE_INFO (5) /* Returns size of a
+ component */
+
+/*
+ * --- MGMT_FLASHROM_OPTYPE ---
+ * Flash ROM operation type
+ */
+#define MGMT_FLASHROM_OPTYPE_CODE_FIRMWARE (0) /* Includes ARM firmware,
+ IPSec (optional) and EP
+ firmware */
+#define MGMT_FLASHROM_OPTYPE_CODE_REDBOOT (1)
+#define MGMT_FLASHROM_OPTYPE_CODE_BIOS (2)
+#define MGMT_FLASHROM_OPTYPE_CODE_PXE_BIOS (3)
+#define MGMT_FLASHROM_OPTYPE_CODE_CTRLS (4)
+#define MGMT_FLASHROM_OPTYPE_CFG_IPSEC (5)
+#define MGMT_FLASHROM_OPTYPE_CFG_INI (6)
+#define MGMT_FLASHROM_OPTYPE_ROM_OFFSET_SPECIFIED (7)
+
+struct BE_FLASHROM_PARAMS_AMAP {
+ struct BE_UEXACT32_AMAP op_code;
+ struct BE_UEXACT32_AMAP op_type;
+ struct BE_UEXACT32_AMAP data_buffer_size;
+ struct BE_UEXACT32_AMAP offset;
+ struct BE_UEXACT8_AMAP data_buffer[4];
+} SG_PACK;
+struct FLASHROM_PARAMS_AMAP {
+ u32 dw[5];
+};
+
+struct BE_IOCTL_COMMON_FLASHROM_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ struct BE_FLASHROM_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_FLASHROM_AMAP {
+ u32 dw[9];
+};
+
+/*
+ * --- FLASHROM_TYPE ---
+ * Flash ROM manufacturers supported in the f/w
+ */
+#define INTEL (0)
+#define SPANSION (1)
+#define MICRON (2)
+
+/* --- DDR_CAS_TYPE --- */
+#define CAS_3 (0)
+#define CAS_4 (1)
+#define CAS_5 (2)
+
+/* --- DDR_SIZE_TYPE --- */
+#define SIZE_256MB (0)
+#define SIZE_512MB (1)
+
+/* --- DDR_MODE_TYPE --- */
+#define DDR_NO_ECC (0)
+#define DDR_ECC (1)
+
+/* --- INTERFACE_10GB_TYPE --- */
+#define CX4_TYPE (0)
+#define XFP_TYPE (1)
+
+/* --- BE_CHIP_MAX_MTU --- */
+#define CHIP_MAX_MTU (9000)
+
+/* --- XAUI_STATE_ENUM --- */
+#define XAUI_STATE_ENABLE (0) /* This MUST be the default
+ value for all requests
+ which set/change
+ equalization parameter. */
+#define XAUI_STATE_DISABLE (255) /* The XAUI for both ports
+ may be disabled for EMI
+ tests. There is no
+ provision for turning off
+ individual ports.
+ */
+struct BE_IOCTL_COMMON_ANON_240_REQUEST_AMAP {
+ struct BE_UEXACT64_AMAP context;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_240_REQUEST_AMAP {
+ u32 dw[2];
+};
+
+struct BE_IOCTL_COMMON_ANON_241_RESPONSE_AMAP {
+ struct BE_UEXACT64_AMAP context;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_241_RESPONSE_AMAP {
+ u32 dw[2];
+};
+
+union BE_IOCTL_COMMON_ANON_239_PARAMS_AMAP {
+ struct BE_IOCTL_COMMON_ANON_240_REQUEST_AMAP request;
+ struct BE_IOCTL_COMMON_ANON_241_RESPONSE_AMAP response;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_239_PARAMS_AMAP {
+ u32 dw[2];
+};
+
+/*
+ * This ioctl can be used by clients as a no-operation request. Typical uses
+ * for drivers are as a heartbeat mechanism, or deferred processing catalyst
+ * The ARM will always complete this IOCTL with a good completion. The 64-bit
+ * parameter is not touched by the ARM processor.
+ */
+struct BE_IOCTL_COMMON_NOP_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_IOCTL_COMMON_ANON_239_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_NOP_AMAP {
+ u32 dw[6];
+};
+
+struct BE_NTWK_RX_FILTER_SETTINGS_AMAP {
+ struct BE_UEXACT8_AMAP promiscuous;
+ struct BE_UEXACT8_AMAP ip_cksum;
+ struct BE_UEXACT8_AMAP tcp_cksum;
+ struct BE_UEXACT8_AMAP udp_cksum;
+ struct BE_UEXACT8_AMAP pass_err;
+ struct BE_UEXACT8_AMAP pass_ckerr;
+ struct BE_UEXACT8_AMAP strip_crc;
+ struct BE_UEXACT8_AMAP mcast_en;
+ struct BE_UEXACT8_AMAP bcast_en;
+ struct BE_UEXACT8_AMAP mcast_promiscuous_en;
+ struct BE_UEXACT8_AMAP unicast_en;
+ struct BE_UEXACT8_AMAP vlan_promiscuous;
+} SG_PACK;
+struct NTWK_RX_FILTER_SETTINGS_AMAP {
+ u32 dw[3];
+};
+
+union BE_IOCTL_COMMON_ANON_242_PARAMS_AMAP {
+ struct BE_NTWK_RX_FILTER_SETTINGS_AMAP request;
+ struct BE_NTWK_RX_FILTER_SETTINGS_AMAP response;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_242_PARAMS_AMAP {
+ u32 dw[3];
+};
+
+/*
+ * This IOCTL is used to modify the ethernet receive filter configuration.
+ * Only domain 0 network function drivers may issue this IOCTL.
+ * The applied configuration is returned in the response payload.
+ * Note: Some receive packet filter settings are global on BladeEngine and can
+ * affect both the storage and network function clients that the
+ * BladeEngine hardware and firmware serve. Additionaly, depending on the
+ * revision of BladeEngine, some ethernet receive filter settings are
+ * dependent on others. If a dependency exists between settings for the
+ * BladeEngine revision, and the IOCTL request settings do not meet the
+ * dependency requirement, the invalid settings will not be applied
+ * despite the IOCTL succeeding. For example: a driver may request to
+ * enable broadcast packets, but not enable multicast packets. On early
+ * revisions of BladeEngine, there may be no distinction between broadcast
+ * and multicast filters, so broadcast could
+ * not be enabled without enabling multicast. In this scenario, the IOCTL
+ * would still succeed, but the response payload would indicate the
+ * previously configured broadcast and multicast setting.
+ */
+struct BE_IOCTL_COMMON_NTWK_RX_FILTER_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_IOCTL_COMMON_ANON_242_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_NTWK_RX_FILTER_AMAP {
+ u32 dw[7];
+};
+
+struct BE_IOCTL_COMMON_ANON_244_REQUEST_AMAP {
+ BE_BIT rsvd0[32]; /* DWORD 0 */
+} SG_PACK;
+struct IOCTL_COMMON_ANON_244_REQUEST_AMAP {
+ u32 dw[1];
+};
+
+struct BE_IOCTL_COMMON_GET_FW_VERSION_RESPONSE_PAYLOAD_AMAP {
+ struct BE_EXACT8_AMAP firmware_version_string[32];
+ struct BE_EXACT8_AMAP fw_on_flash_version_string[32];
+} SG_PACK;
+struct IOCTL_COMMON_GET_FW_VERSION_RESPONSE_PAYLOAD_AMAP {
+ u32 dw[16];
+};
+
+union BE_IOCTL_COMMON_ANON_243_PARAMS_AMAP {
+ struct BE_IOCTL_COMMON_ANON_244_REQUEST_AMAP request;
+ struct BE_IOCTL_COMMON_GET_FW_VERSION_RESPONSE_PAYLOAD_AMAP response;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_243_PARAMS_AMAP {
+ u32 dw[16];
+};
+
+/* This IOCTL retrieves the firmware version. */
+struct BE_IOCTL_COMMON_GET_FW_VERSION_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_IOCTL_COMMON_ANON_243_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_GET_FW_VERSION_AMAP {
+ u32 dw[20];
+};
+
+struct BE_IOCTL_COMMON_ANON_246_REQUEST_AMAP {
+ struct BE_UEXACT16_AMAP tx_flow_control;
+ struct BE_UEXACT16_AMAP rx_flow_control;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_246_REQUEST_AMAP {
+ u32 dw[1];
+};
+
+struct BE_IOCTL_COMMON_ANON_247_RESPONSE_AMAP {
+ BE_BIT rsvd0[32]; /* DWORD 0 */
+} SG_PACK;
+struct IOCTL_COMMON_ANON_247_RESPONSE_AMAP {
+ u32 dw[1];
+};
+
+union BE_IOCTL_COMMON_ANON_245_PARAMS_AMAP {
+ struct BE_IOCTL_COMMON_ANON_246_REQUEST_AMAP request;
+ struct BE_IOCTL_COMMON_ANON_247_RESPONSE_AMAP response;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_245_PARAMS_AMAP {
+ u32 dw[1];
+};
+
+/*
+ * This IOCTL is used to program BladeEngine flow control behavior.
+ * Only the host networking driver is allowed to use this IOCTL.
+ */
+struct BE_IOCTL_COMMON_SET_FLOW_CONTROL_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_IOCTL_COMMON_ANON_245_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_SET_FLOW_CONTROL_AMAP {
+ u32 dw[5];
+};
+
+struct BE_IOCTL_COMMON_ANON_249_REQUEST_AMAP {
+ BE_BIT rsvd0[32]; /* DWORD 0 */
+} SG_PACK;
+struct IOCTL_COMMON_ANON_249_REQUEST_AMAP {
+ u32 dw[1];
+};
+
+struct BE_IOCTL_COMMON_ANON_250_RESPONSE_AMAP {
+ struct BE_UEXACT16_AMAP tx_flow_control;
+ struct BE_UEXACT16_AMAP rx_flow_control;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_250_RESPONSE_AMAP {
+ u32 dw[1];
+};
+
+union BE_IOCTL_COMMON_ANON_248_PARAMS_AMAP {
+ struct BE_IOCTL_COMMON_ANON_249_REQUEST_AMAP request;
+ struct BE_IOCTL_COMMON_ANON_250_RESPONSE_AMAP response;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_248_PARAMS_AMAP {
+ u32 dw[1];
+};
+
+/* This IOCTL is used to read BladeEngine flow control settings. */
+struct BE_IOCTL_COMMON_GET_FLOW_CONTROL_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_IOCTL_COMMON_ANON_248_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_GET_FLOW_CONTROL_AMAP {
+ u32 dw[5];
+};
+
+struct BE_IOCTL_COMMON_ANON_255_REQUEST_AMAP {
+ struct BE_UEXACT8_AMAP clear_log;
+ struct BE_UEXACT8_AMAP num_pages;
+ struct BE_UEXACT16_AMAP page_offset;
+ struct BE_PHYS_ADDR_AMAP buffer_addr[27];
+} SG_PACK;
+struct IOCTL_COMMON_ANON_255_REQUEST_AMAP {
+ u32 dw[55];
+};
+
+struct BE_IOCTL_COMMON_ANON_256_RESPONSE_AMAP {
+ struct BE_UEXACT32_AMAP log_size;
+ struct BE_UEXACT32_AMAP bytes_transferred;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_256_RESPONSE_AMAP {
+ u32 dw[2];
+};
+
+union BE_IOCTL_COMMON_ANON_254_PARAMS_AMAP {
+ struct BE_IOCTL_COMMON_ANON_255_REQUEST_AMAP request;
+ struct BE_IOCTL_COMMON_ANON_256_RESPONSE_AMAP response;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_254_PARAMS_AMAP {
+ u32 dw[55];
+};
+
+/*
+ * This IOCTL retrieves a Fault Analaysis Tool (FAT) log. The log data
+ * can be anaylzed by BladeEngine support tools to diagnose faults.
+ * Only host domains may issue this IOCTL.
+ */
+struct BE_IOCTL_COMMON_GET_FAT_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_IOCTL_COMMON_ANON_254_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_GET_FAT_AMAP {
+ u32 dw[59];
+};
+
+struct BE_ENABLE_DISABLE_DOMAINS_PARAMS_IN_AMAP {
+ struct BE_UEXACT8_AMAP domain_function;
+ struct BE_UEXACT8_AMAP enable_disable;
+ BE_BIT rsvd0[16]; /* DWORD 0 */
+} SG_PACK;
+struct ENABLE_DISABLE_DOMAINS_PARAMS_IN_AMAP {
+ u32 dw[1];
+};
+
+struct BE_ENABLE_DISABLE_DOMAINS_PARAMS_OUT_AMAP {
+ BE_BIT rsvd0[32]; /* DWORD 0 */
+} SG_PACK;
+struct ENABLE_DISABLE_DOMAINS_PARAMS_OUT_AMAP {
+ u32 dw[1];
+};
+
+union BE_ENABLE_DISABLE_DOMAINS_PARAMS_AMAP {
+ struct BE_ENABLE_DISABLE_DOMAINS_PARAMS_IN_AMAP request;
+ struct BE_ENABLE_DISABLE_DOMAINS_PARAMS_OUT_AMAP response;
+} SG_PACK;
+struct ENABLE_DISABLE_DOMAINS_PARAMS_AMAP {
+ u32 dw[1];
+};
+
+/*
+ * This IOCTL enables or disables a domain for NIC or iSCSI functionality.
+ * If a particular domain is enabled, management utilities like SMCLP expose a
+ * logicalHBA to the user allowing the QoS, iSCSI (iqn) name etc to be set for
+ * that domain. The domain number is specified in the IOCTL_HEADER. This
+ * IOCTL can only originate from domain 0. This IOCTL may return one of the
+ * following status values in the response
+ * MGMT_STATUS_SUCCESS MGMT_STATUS_FAILED with additional status set to
+ * MGMT_ADDI_STATUS_INVALID_DOMAIN
+ */
+struct BE_IOCTL_COMMON_ENABLE_DISABLE_DOMAINS_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_ENABLE_DISABLE_DOMAINS_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_ENABLE_DISABLE_DOMAINS_AMAP {
+ u32 dw[5];
+};
+
+struct BE_GET_DOMAIN_CONFIG_PARAMS_IN_AMAP {
+ struct BE_UEXACT8_AMAP domain_function;
+ struct BE_UEXACT8_AMAP enable_disable;
+ BE_BIT rsvd0[16]; /* DWORD 0 */
+} SG_PACK;
+struct GET_DOMAIN_CONFIG_PARAMS_IN_AMAP {
+ u32 dw[1];
+};
+
+struct BE_GET_DOMAIN_CONFIG_PARAMS_OUT_AMAP {
+ struct BE_UEXACT16_AMAP domain_bitmap;
+} SG_PACK;
+struct GET_DOMAIN_CONFIG_PARAMS_OUT_AMAP {
+ u32 dw[1];
+};
+
+union BE_GET_DOMAIN_CONFIG_PARAMS_AMAP {
+ struct BE_GET_DOMAIN_CONFIG_PARAMS_IN_AMAP request;
+ struct BE_GET_DOMAIN_CONFIG_PARAMS_OUT_AMAP response;
+} SG_PACK;
+struct GET_DOMAIN_CONFIG_PARAMS_AMAP {
+ u32 dw[1];
+};
+
+/*
+ * This IOCTL returns a bitmap indicating the current status of the NIC or
+ * iSCSI functionality for all the domains supported on a given BladeEngine.
+ * The domain number in the IOCTL header is ignored. This IOCTL can
+ * only originate from domain 0. This IOCTL will always return
+ * MGMT_STATUS_SUCCESS
+ */
+struct BE_IOCTL_COMMON_GET_DOMAIN_CONFIG_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_GET_DOMAIN_CONFIG_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_GET_DOMAIN_CONFIG_AMAP {
+ u32 dw[5];
+};
+
+struct BE_SET_VLD_CONFIG_PARAMS_IN_AMAP {
+ struct BE_UEXACT8_AMAP enable_disable;
+ BE_BIT rsvd0[8]; /* DWORD 0 */
+ BE_BIT rsvd1[16]; /* DWORD 0 */
+} SG_PACK;
+struct SET_VLD_CONFIG_PARAMS_IN_AMAP {
+ u32 dw[1];
+};
+
+struct BE_SET_VLD_CONFIG_PARAMS_OUT_AMAP {
+ BE_BIT rsvd0[32]; /* DWORD 0 */
+} SG_PACK;
+struct SET_VLD_CONFIG_PARAMS_OUT_AMAP {
+ u32 dw[1];
+};
+
+union BE_SET_VLD_CONFIG_PARAMS_AMAP {
+ struct BE_SET_VLD_CONFIG_PARAMS_IN_AMAP request;
+ struct BE_SET_VLD_CONFIG_PARAMS_OUT_AMAP response;
+} SG_PACK;
+struct SET_VLD_CONFIG_PARAMS_AMAP {
+ u32 dw[1];
+};
+
+/*
+ * Enable/Disable Virtual Link Down (VLD) if this feature is enabled on your
+ * BladeEngine. Use IOCTL_COMMON_GET_CNTL_ATTRIBUTES to determine
+ * whether VLD can be enabled. This IOCTL can only originate from domain 0. The
+ * VLD setting applies to the entire BladeEngine and affects all NIC/iSCSI
+ * drivers.
+ */
+struct BE_IOCTL_COMMON_SET_VLD_CONFIG_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_SET_VLD_CONFIG_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_SET_VLD_CONFIG_AMAP {
+ u32 dw[5];
+};
+
+struct BE_GET_VLD_CONFIG_PARAMS_IN_AMAP {
+ BE_BIT rsvd0[32]; /* DWORD 0 */
+} SG_PACK;
+struct GET_VLD_CONFIG_PARAMS_IN_AMAP {
+ u32 dw[1];
+};
+
+struct BE_GET_VLD_CONFIG_PARAMS_OUT_AMAP {
+ struct BE_UEXACT8_AMAP enable_disable;
+ BE_BIT rsvd0[8]; /* DWORD 0 */
+ BE_BIT rsvd1[16]; /* DWORD 0 */
+} SG_PACK;
+struct GET_VLD_CONFIG_PARAMS_OUT_AMAP {
+ u32 dw[1];
+};
+
+union BE_GET_VLD_CONFIG_PARAMS_AMAP {
+ struct BE_GET_VLD_CONFIG_PARAMS_IN_AMAP request;
+ struct BE_GET_VLD_CONFIG_PARAMS_OUT_AMAP response;
+} SG_PACK;
+struct GET_VLD_CONFIG_PARAMS_AMAP {
+ u32 dw[1];
+};
+
+/*
+ * Use this IOCTL to determine whether Virtual Link Down (VLD) is currently
+ * enabled or disabled. Use IOCTL_COMMON_GET_CNTL_ATTRIBUTES to
+ * determine whether VLD can be enabled/disabled. This IOCTL can only originate
+ * from domain 0. The VLD setting applies to the entire BladeEngine
+ * and affects all NIC/iSCSI drivers.
+ */
+struct BE_IOCTL_COMMON_GET_VLD_CONFIG_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_GET_VLD_CONFIG_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_GET_VLD_CONFIG_AMAP {
+ u32 dw[5];
+};
+
+struct BE_EQ_DELAY_PARAMS_AMAP {
+ struct BE_UEXACT32_AMAP eq_id;
+ struct BE_UEXACT32_AMAP delay_in_microseconds;
+} SG_PACK;
+struct EQ_DELAY_PARAMS_AMAP {
+ u32 dw[2];
+};
+
+struct BE_IOCTL_COMMON_ANON_257_REQUEST_AMAP {
+ struct BE_UEXACT32_AMAP num_eq;
+ BE_BIT rsvd0[32]; /* DWORD 1 */
+ struct BE_EQ_DELAY_PARAMS_AMAP delay[16];
+} SG_PACK;
+struct IOCTL_COMMON_ANON_257_REQUEST_AMAP {
+ u32 dw[34];
+};
+
+struct BE_IOCTL_COMMON_ANON_258_RESPONSE_AMAP {
+ struct BE_UEXACT32_AMAP delay_resolution_in_microseconds;
+ struct BE_UEXACT32_AMAP delay_max_in_microseconds;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_258_RESPONSE_AMAP {
+ u32 dw[2];
+};
+
+union BE_MODIFY_EQ_DELAY_PARAMS_AMAP {
+ struct BE_IOCTL_COMMON_ANON_257_REQUEST_AMAP request;
+ struct BE_IOCTL_COMMON_ANON_258_RESPONSE_AMAP response;
+} SG_PACK;
+struct MODIFY_EQ_DELAY_PARAMS_AMAP {
+ u32 dw[34];
+};
+
+/* This IOCTL changes the EQ delay for a given set of EQs. */
+struct BE_IOCTL_COMMON_MODIFY_EQ_DELAY_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_MODIFY_EQ_DELAY_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_MODIFY_EQ_DELAY_AMAP {
+ u32 dw[38];
+};
+
+/* --- BE_ASIC_REVISION --- */
+#define BE_ASIC_REV_A0 (1)
+#define BE_ASIC_REV_A1 (2)
+
+struct BE_IOCTL_COMMON_ANON_260_REQUEST_AMAP {
+ BE_BIT rsvd0[32]; /* DWORD 0 */
+} SG_PACK;
+struct IOCTL_COMMON_ANON_260_REQUEST_AMAP {
+ u32 dw[1];
+};
+
+struct BE_IOCTL_COMMON_PORT_EQUALIZATION_PARAMS_AMAP {
+ struct BE_UEXACT32_AMAP emph_lev_sel_port0;
+ struct BE_UEXACT32_AMAP emph_lev_sel_port1;
+ struct BE_UEXACT8_AMAP xaui_vo_sel;
+ struct BE_UEXACT8_AMAP xaui_state;
+ BE_BIT rsvd0[16]; /* DWORD 2 */
+ struct BE_UEXACT32_AMAP xaui_eq_vector;
+} SG_PACK;
+struct IOCTL_COMMON_PORT_EQUALIZATION_PARAMS_AMAP {
+ u32 dw[4];
+};
+
+struct BE_IOCTL_COMMON_ANON_262_REQUEST_AMAP {
+ BE_BIT rsvd0[32]; /* DWORD 0 */
+} SG_PACK;
+struct IOCTL_COMMON_ANON_262_REQUEST_AMAP {
+ u32 dw[1];
+};
+
+union BE_IOCTL_COMMON_ANON_261_PARAMS_AMAP {
+ struct BE_IOCTL_COMMON_ANON_262_REQUEST_AMAP request;
+ struct BE_IOCTL_COMMON_PORT_EQUALIZATION_PARAMS_AMAP response;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_261_PARAMS_AMAP {
+ u32 dw[4];
+};
+
+/*
+ * This IOCTL can be used to read XAUI equalization parameters. The ARM
+ * firmware applies default equalization parameters during initialization
+ * These parameters may be customer-specific when derived from the SEEPROM.
+ * See SEEPROM_DATA for equalization specific fields.
+ */
+struct BE_IOCTL_COMMON_GET_PORT_EQUALIZATION_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_IOCTL_COMMON_ANON_261_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_GET_PORT_EQUALIZATION_AMAP {
+ u32 dw[8];
+};
+
+struct BE_IOCTL_COMMON_ANON_264_RESPONSE_AMAP {
+ BE_BIT rsvd0[32]; /* DWORD 0 */
+} SG_PACK;
+struct IOCTL_COMMON_ANON_264_RESPONSE_AMAP {
+ u32 dw[1];
+};
+
+union BE_IOCTL_COMMON_ANON_263_PARAMS_AMAP {
+ struct BE_IOCTL_COMMON_PORT_EQUALIZATION_PARAMS_AMAP request;
+ struct BE_IOCTL_COMMON_ANON_264_RESPONSE_AMAP response;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_263_PARAMS_AMAP {
+ u32 dw[4];
+};
+
+/*
+ * This IOCTL can be used to set XAUI equalization parameters. The ARM
+ * firmware applies default equalization parameters during initialization
+ * These parameters may be customer-specific when derived from the SEEPROM.
+ * See SEEPROM_DATA for equalization specific fields.
+ */
+struct BE_IOCTL_COMMON_SET_PORT_EQUALIZATION_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_IOCTL_COMMON_ANON_263_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_SET_PORT_EQUALIZATION_AMAP {
+ u32 dw[8];
+};
+
+struct BE_BE_RED_CHUTE_PARAMETERS_AMAP {
+ struct BE_UEXACT8_AMAP enable;
+ struct BE_UEXACT8_AMAP w1;
+ struct BE_UEXACT8_AMAP w2;
+ struct BE_UEXACT8_AMAP slope;
+ struct BE_UEXACT8_AMAP mtu_integer;
+ struct BE_UEXACT8_AMAP mtu_exponent;
+ BE_BIT rsvd0[16]; /* DWORD 1 */
+ struct BE_UEXACT16_AMAP min_pbuf;
+ struct BE_UEXACT16_AMAP max_pbuf;
+} SG_PACK;
+struct BE_RED_CHUTE_PARAMETERS_AMAP {
+ u32 dw[3];
+};
+
+struct BE_BE_RED_PARAMETERS_AMAP {
+ struct BE_BE_RED_CHUTE_PARAMETERS_AMAP chute[3];
+} SG_PACK;
+struct BE_RED_PARAMETERS_AMAP {
+ u32 dw[9];
+};
+
+struct BE_IOCTL_COMMON_ANON_266_RESPONSE_AMAP {
+ BE_BIT rsvd0[32]; /* DWORD 0 */
+} SG_PACK;
+struct IOCTL_COMMON_ANON_266_RESPONSE_AMAP {
+ u32 dw[1];
+};
+
+union BE_IOCTL_COMMON_ANON_265_PARAMS_AMAP {
+ struct BE_BE_RED_PARAMETERS_AMAP request;
+ struct BE_IOCTL_COMMON_ANON_266_RESPONSE_AMAP response;
+} SG_PACK;
+struct IOCTL_COMMON_ANON_265_PARAMS_AMAP {
+ u32 dw[9];
+};
+
+/*
+ * This IOCTL configures the Random Early Discard (RED) functionality
+ * for the PCI function. Only the chutes owned by the given PCI function are
+ * configured. The other chutes are ignored.
+ */
+struct BE_IOCTL_COMMON_RED_CONFIG_AMAP {
+ union BE_IOCTL_HEADER_AMAP header;
+ union BE_IOCTL_COMMON_ANON_265_PARAMS_AMAP params;
+} SG_PACK;
+struct IOCTL_COMMON_RED_CONFIG_AMAP {
+ u32 dw[13];
+};
+
+#endif /* __ioctl_common_amap_h__ */
diff --git a/drivers/message/beclib/fw/amap/pcicfg.h b/drivers/message/beclib/fw/amap/pcicfg.h
new file mode 100644
index 0000000..a221be8
--- /dev/null
+++ b/drivers/message/beclib/fw/amap/pcicfg.h
@@ -0,0 +1,839 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or at your option any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, 5th Floor
+ * Boston, MA 02110-1301 USA
+ *
+ *
+ * The full GNU General Public License is included in this distribution
+ * in the file called GPL.
+ *
+ * Contact Information:
+ * linux-drivers@...verengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __pcicfg_amap_h__
+#define __pcicfg_amap_h__
+
+/* Vendor and Device ID Register. */
+struct BE_PCICFG_ID_CSR_AMAP {
+ BE_BIT vendorid[16]; /* DWORD 0 */
+ BE_BIT deviceid[16]; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_ID_CSR_AMAP {
+ u32 dw[1];
+};
+
+/* IO Bar Register. */
+struct BE_PCICFG_IOBAR_CSR_AMAP {
+ BE_BIT iospace; /* DWORD 0 */
+ BE_BIT rsvd0[7]; /* DWORD 0 */
+ BE_BIT iobar[24]; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_IOBAR_CSR_AMAP {
+ u32 dw[1];
+};
+
+/* Memory BAR 0 Register. */
+struct BE_PCICFG_MEMBAR0_CSR_AMAP {
+ BE_BIT memspace; /* DWORD 0 */
+ BE_BIT type[2]; /* DWORD 0 */
+ BE_BIT pf; /* DWORD 0 */
+ BE_BIT rsvd0[10]; /* DWORD 0 */
+ BE_BIT membar0[18]; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_MEMBAR0_CSR_AMAP {
+ u32 dw[1];
+};
+
+/* Memory BAR 1 - Low Address Register. */
+struct BE_PCICFG_MEMBAR1_LO_CSR_AMAP {
+ BE_BIT memspace; /* DWORD 0 */
+ BE_BIT type[2]; /* DWORD 0 */
+ BE_BIT pf; /* DWORD 0 */
+ BE_BIT rsvd0[13]; /* DWORD 0 */
+ BE_BIT membar1lo[15]; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_MEMBAR1_LO_CSR_AMAP {
+ u32 dw[1];
+};
+
+/* Memory BAR 1 - High Address Register. */
+struct BE_PCICFG_MEMBAR1_HI_CSR_AMAP {
+ BE_BIT membar1hi[32]; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_MEMBAR1_HI_CSR_AMAP {
+ u32 dw[1];
+};
+
+/* Memory BAR 2 - Low Address Register. */
+struct BE_PCICFG_MEMBAR2_LO_CSR_AMAP {
+ BE_BIT memspace; /* DWORD 0 */
+ BE_BIT type[2]; /* DWORD 0 */
+ BE_BIT pf; /* DWORD 0 */
+ BE_BIT rsvd0[17]; /* DWORD 0 */
+ BE_BIT membar2lo[11]; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_MEMBAR2_LO_CSR_AMAP {
+ u32 dw[1];
+};
+
+/* Memory BAR 2 - High Address Register. */
+struct BE_PCICFG_MEMBAR2_HI_CSR_AMAP {
+ BE_BIT membar2hi[32]; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_MEMBAR2_HI_CSR_AMAP {
+ u32 dw[1];
+};
+
+/* Subsystem Vendor and ID (Function 0) Register. */
+struct BE_PCICFG_SUBSYSTEM_ID_F0_CSR_AMAP {
+ BE_BIT subsys_vendor_id[16]; /* DWORD 0 */
+ BE_BIT subsys_id[16]; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_SUBSYSTEM_ID_F0_CSR_AMAP {
+ u32 dw[1];
+};
+
+/* Subsystem Vendor and ID (Function 1) Register. */
+struct BE_PCICFG_SUBSYSTEM_ID_F1_CSR_AMAP {
+ BE_BIT subsys_vendor_id[16]; /* DWORD 0 */
+ BE_BIT subsys_id[16]; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_SUBSYSTEM_ID_F1_CSR_AMAP {
+ u32 dw[1];
+};
+
+/* Semaphore Register. */
+struct BE_PCICFG_SEMAPHORE_CSR_AMAP {
+ BE_BIT locked; /* DWORD 0 */
+ BE_BIT rsvd0[31]; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_SEMAPHORE_CSR_AMAP {
+ u32 dw[1];
+};
+
+/* Soft Reset Register. */
+struct BE_PCICFG_SOFT_RESET_CSR_AMAP {
+ BE_BIT rsvd0[7]; /* DWORD 0 */
+ BE_BIT softreset; /* DWORD 0 */
+ BE_BIT rsvd1[16]; /* DWORD 0 */
+ BE_BIT nec_ll_rcvdetect_i[8]; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_SOFT_RESET_CSR_AMAP {
+ u32 dw[1];
+};
+
+/* Unrecoverable Error Status (Low) Register. Each bit corresponds to
+ * an internal Unrecoverable Error. These are set by hardware and may be
+ * cleared by writing a one to the respective bit(s) to be cleared. Any
+ * bit being set that is also unmasked will result in Unrecoverable Error
+ * interrupt notification to the host CPU and/or Server Management chip
+ * and the transitioning of BladeEngine to an Offline state.
+ */
+struct BE_PCICFG_UE_STATUS_LOW_CSR_AMAP {
+ BE_BIT cev_ue_status; /* DWORD 0 */
+ BE_BIT ctx_ue_status; /* DWORD 0 */
+ BE_BIT dbuf_ue_status; /* DWORD 0 */
+ BE_BIT erx_ue_status; /* DWORD 0 */
+ BE_BIT host_ue_status; /* DWORD 0 */
+ BE_BIT mpu_ue_status; /* DWORD 0 */
+ BE_BIT ndma_ue_status; /* DWORD 0 */
+ BE_BIT ptc_ue_status; /* DWORD 0 */
+ BE_BIT rdma_ue_status; /* DWORD 0 */
+ BE_BIT rxf_ue_status; /* DWORD 0 */
+ BE_BIT rxips_ue_status; /* DWORD 0 */
+ BE_BIT rxulp0_ue_status; /* DWORD 0 */
+ BE_BIT rxulp1_ue_status; /* DWORD 0 */
+ BE_BIT rxulp2_ue_status; /* DWORD 0 */
+ BE_BIT tim_ue_status; /* DWORD 0 */
+ BE_BIT tpost_ue_status; /* DWORD 0 */
+ BE_BIT tpre_ue_status; /* DWORD 0 */
+ BE_BIT txips_ue_status; /* DWORD 0 */
+ BE_BIT txulp0_ue_status; /* DWORD 0 */
+ BE_BIT txulp1_ue_status; /* DWORD 0 */
+ BE_BIT uc_ue_status; /* DWORD 0 */
+ BE_BIT wdma_ue_status; /* DWORD 0 */
+ BE_BIT txulp2_ue_status; /* DWORD 0 */
+ BE_BIT host1_ue_status; /* DWORD 0 */
+ BE_BIT p0_ob_link_ue_status; /* DWORD 0 */
+ BE_BIT p1_ob_link_ue_status; /* DWORD 0 */
+ BE_BIT host_gpio_ue_status; /* DWORD 0 */
+ BE_BIT mbox_netw_ue_status; /* DWORD 0 */
+ BE_BIT mbox_stor_ue_status; /* DWORD 0 */
+ BE_BIT axgmac0_ue_status; /* DWORD 0 */
+ BE_BIT axgmac1_ue_status; /* DWORD 0 */
+ BE_BIT mpu_intpend_ue_status; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_UE_STATUS_LOW_CSR_AMAP {
+ u32 dw[1];
+};
+
+/* Unrecoverable Error Status (High) Register. Each bit corresponds to
+ * an internal Unrecoverable Error. These are set by hardware and may be
+ * cleared by writing a one to the respective bit(s) to be cleared. Any
+ * bit being set that is also unmasked will result in Unrecoverable Error
+ * interrupt notification to the host CPU and/or Server Management chip;
+ * and the transitioning of BladeEngine to an Offline state.
+ */
+struct BE_PCICFG_UE_STATUS_HI_CSR_AMAP {
+ BE_BIT jtag_ue_status; /* DWORD 0 */
+ BE_BIT lpcmemhost_ue_status; /* DWORD 0 */
+ BE_BIT mgmt_mac_ue_status; /* DWORD 0 */
+ BE_BIT mpu_iram_ue_status; /* DWORD 0 */
+ BE_BIT pcs0online_ue_status; /* DWORD 0 */
+ BE_BIT pcs1online_ue_status; /* DWORD 0 */
+ BE_BIT pctl0_ue_status; /* DWORD 0 */
+ BE_BIT pctl1_ue_status; /* DWORD 0 */
+ BE_BIT pmem_ue_status; /* DWORD 0 */
+ BE_BIT rr_ue_status; /* DWORD 0 */
+ BE_BIT rxpp_ue_status; /* DWORD 0 */
+ BE_BIT txpb_ue_status; /* DWORD 0 */
+ BE_BIT txp_ue_status; /* DWORD 0 */
+ BE_BIT xaui_ue_status; /* DWORD 0 */
+ BE_BIT arm_ue_status; /* DWORD 0 */
+ BE_BIT ipc_ue_status; /* DWORD 0 */
+ BE_BIT rsvd0[16]; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_UE_STATUS_HI_CSR_AMAP {
+ u32 dw[1];
+};
+
+/* Unrecoverable Error Mask (Low) Register. Each bit, when set to one,
+ * will mask the associated Unrecoverable Error status bit from notification
+ * of Unrecoverable Error to the host CPU and/or Server Managment chip and the
+ * transitioning of all BladeEngine units to an Offline state.
+ */
+struct BE_PCICFG_UE_STATUS_LOW_MASK_CSR_AMAP {
+ BE_BIT cev_ue_mask; /* DWORD 0 */
+ BE_BIT ctx_ue_mask; /* DWORD 0 */
+ BE_BIT dbuf_ue_mask; /* DWORD 0 */
+ BE_BIT erx_ue_mask; /* DWORD 0 */
+ BE_BIT host_ue_mask; /* DWORD 0 */
+ BE_BIT mpu_ue_mask; /* DWORD 0 */
+ BE_BIT ndma_ue_mask; /* DWORD 0 */
+ BE_BIT ptc_ue_mask; /* DWORD 0 */
+ BE_BIT rdma_ue_mask; /* DWORD 0 */
+ BE_BIT rxf_ue_mask; /* DWORD 0 */
+ BE_BIT rxips_ue_mask; /* DWORD 0 */
+ BE_BIT rxulp0_ue_mask; /* DWORD 0 */
+ BE_BIT rxulp1_ue_mask; /* DWORD 0 */
+ BE_BIT rxulp2_ue_mask; /* DWORD 0 */
+ BE_BIT tim_ue_mask; /* DWORD 0 */
+ BE_BIT tpost_ue_mask; /* DWORD 0 */
+ BE_BIT tpre_ue_mask; /* DWORD 0 */
+ BE_BIT txips_ue_mask; /* DWORD 0 */
+ BE_BIT txulp0_ue_mask; /* DWORD 0 */
+ BE_BIT txulp1_ue_mask; /* DWORD 0 */
+ BE_BIT uc_ue_mask; /* DWORD 0 */
+ BE_BIT wdma_ue_mask; /* DWORD 0 */
+ BE_BIT txulp2_ue_mask; /* DWORD 0 */
+ BE_BIT host1_ue_mask; /* DWORD 0 */
+ BE_BIT p0_ob_link_ue_mask; /* DWORD 0 */
+ BE_BIT p1_ob_link_ue_mask; /* DWORD 0 */
+ BE_BIT host_gpio_ue_mask; /* DWORD 0 */
+ BE_BIT mbox_netw_ue_mask; /* DWORD 0 */
+ BE_BIT mbox_stor_ue_mask; /* DWORD 0 */
+ BE_BIT axgmac0_ue_mask; /* DWORD 0 */
+ BE_BIT axgmac1_ue_mask; /* DWORD 0 */
+ BE_BIT mpu_intpend_ue_mask; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_UE_STATUS_LOW_MASK_CSR_AMAP {
+ u32 dw[1];
+};
+
+/* Unrecoverable Error Mask (High) Register. Each bit, when set to one,
+ * will mask the associated Unrecoverable Error status bit from notification
+ * of Unrecoverable Error to the host CPU and/or Server Managment chip and the
+ * transitioning of all BladeEngine units to an Offline state.
+ */
+struct BE_PCICFG_UE_STATUS_HI_MASK_CSR_AMAP {
+ BE_BIT jtag_ue_mask; /* DWORD 0 */
+ BE_BIT lpcmemhost_ue_mask; /* DWORD 0 */
+ BE_BIT mgmt_mac_ue_mask; /* DWORD 0 */
+ BE_BIT mpu_iram_ue_mask; /* DWORD 0 */
+ BE_BIT pcs0online_ue_mask; /* DWORD 0 */
+ BE_BIT pcs1online_ue_mask; /* DWORD 0 */
+ BE_BIT pctl0_ue_mask; /* DWORD 0 */
+ BE_BIT pctl1_ue_mask; /* DWORD 0 */
+ BE_BIT pmem_ue_mask; /* DWORD 0 */
+ BE_BIT rr_ue_mask; /* DWORD 0 */
+ BE_BIT rxpp_ue_mask; /* DWORD 0 */
+ BE_BIT txpb_ue_mask; /* DWORD 0 */
+ BE_BIT txp_ue_mask; /* DWORD 0 */
+ BE_BIT xaui_ue_mask; /* DWORD 0 */
+ BE_BIT arm_ue_mask; /* DWORD 0 */
+ BE_BIT ipc_ue_mask; /* DWORD 0 */
+ BE_BIT rsvd0[16]; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_UE_STATUS_HI_MASK_CSR_AMAP {
+ u32 dw[1];
+};
+
+/* Online Control Register 0. This register controls various units within
+ * BladeEngine being in an Online or Offline state.
+ */
+struct BE_PCICFG_ONLINE0_CSR_AMAP {
+ BE_BIT cev_online; /* DWORD 0 */
+ BE_BIT ctx_online; /* DWORD 0 */
+ BE_BIT dbuf_online; /* DWORD 0 */
+ BE_BIT erx_online; /* DWORD 0 */
+ BE_BIT host_online; /* DWORD 0 */
+ BE_BIT mpu_online; /* DWORD 0 */
+ BE_BIT ndma_online; /* DWORD 0 */
+ BE_BIT ptc_online; /* DWORD 0 */
+ BE_BIT rdma_online; /* DWORD 0 */
+ BE_BIT rxf_online; /* DWORD 0 */
+ BE_BIT rxips_online; /* DWORD 0 */
+ BE_BIT rxulp0_online; /* DWORD 0 */
+ BE_BIT rxulp1_online; /* DWORD 0 */
+ BE_BIT rxulp2_online; /* DWORD 0 */
+ BE_BIT tim_online; /* DWORD 0 */
+ BE_BIT tpost_online; /* DWORD 0 */
+ BE_BIT tpre_online; /* DWORD 0 */
+ BE_BIT txips_online; /* DWORD 0 */
+ BE_BIT txulp0_online; /* DWORD 0 */
+ BE_BIT txulp1_online; /* DWORD 0 */
+ BE_BIT uc_online; /* DWORD 0 */
+ BE_BIT wdma_online; /* DWORD 0 */
+ BE_BIT txulp2_online; /* DWORD 0 */
+ BE_BIT host1_online; /* DWORD 0 */
+ BE_BIT p0_ob_link_online; /* DWORD 0 */
+ BE_BIT p1_ob_link_online; /* DWORD 0 */
+ BE_BIT host_gpio_online; /* DWORD 0 */
+ BE_BIT mbox_netw_online; /* DWORD 0 */
+ BE_BIT mbox_stor_online; /* DWORD 0 */
+ BE_BIT axgmac0_online; /* DWORD 0 */
+ BE_BIT axgmac1_online; /* DWORD 0 */
+ BE_BIT mpu_intpend_online; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_ONLINE0_CSR_AMAP {
+ u32 dw[1];
+};
+
+/* Online Control Register 1. This register controls various units within
+ * BladeEngine being in an Online or Offline state.
+ */
+struct BE_PCICFG_ONLINE1_CSR_AMAP {
+ BE_BIT jtag_online; /* DWORD 0 */
+ BE_BIT lpcmemhost_online; /* DWORD 0 */
+ BE_BIT mgmt_mac_online; /* DWORD 0 */
+ BE_BIT mpu_iram_online; /* DWORD 0 */
+ BE_BIT pcs0online_online; /* DWORD 0 */
+ BE_BIT pcs1online_online; /* DWORD 0 */
+ BE_BIT pctl0_online; /* DWORD 0 */
+ BE_BIT pctl1_online; /* DWORD 0 */
+ BE_BIT pmem_online; /* DWORD 0 */
+ BE_BIT rr_online; /* DWORD 0 */
+ BE_BIT rxpp_online; /* DWORD 0 */
+ BE_BIT txpb_online; /* DWORD 0 */
+ BE_BIT txp_online; /* DWORD 0 */
+ BE_BIT xaui_online; /* DWORD 0 */
+ BE_BIT arm_online; /* DWORD 0 */
+ BE_BIT ipc_online; /* DWORD 0 */
+ BE_BIT rsvd0[16]; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_ONLINE1_CSR_AMAP {
+ u32 dw[1];
+};
+
+/* Host Timer Register. */
+struct BE_PCICFG_HOST_TIMER_INT_CTRL_CSR_AMAP {
+ BE_BIT hosttimer[24]; /* DWORD 0 */
+ BE_BIT hostintr; /* DWORD 0 */
+ BE_BIT rsvd0[7]; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_HOST_TIMER_INT_CTRL_CSR_AMAP {
+ u32 dw[1];
+};
+
+/* Scratchpad Register (for software use). */
+struct BE_PCICFG_SCRATCHPAD_CSR_AMAP {
+ BE_BIT scratchpad[32]; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_SCRATCHPAD_CSR_AMAP {
+ u32 dw[1];
+};
+
+/* PCI Express Capabilities Register. */
+struct BE_PCICFG_PCIE_CAP_CSR_AMAP {
+ BE_BIT capid[8]; /* DWORD 0 */
+ BE_BIT nextcap[8]; /* DWORD 0 */
+ BE_BIT capver[4]; /* DWORD 0 */
+ BE_BIT devport[4]; /* DWORD 0 */
+ BE_BIT rsvd0[6]; /* DWORD 0 */
+ BE_BIT rsvd1[2]; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_PCIE_CAP_CSR_AMAP {
+ u32 dw[1];
+};
+
+/* PCI Express Device Capabilities Register. */
+struct BE_PCICFG_PCIE_DEVCAP_CSR_AMAP {
+ BE_BIT payload[3]; /* DWORD 0 */
+ BE_BIT rsvd0[3]; /* DWORD 0 */
+ BE_BIT lo_lat[3]; /* DWORD 0 */
+ BE_BIT l1_lat[3]; /* DWORD 0 */
+ BE_BIT rsvd1[3]; /* DWORD 0 */
+ BE_BIT rsvd2[3]; /* DWORD 0 */
+ BE_BIT pwr_value[8]; /* DWORD 0 */
+ BE_BIT pwr_scale[2]; /* DWORD 0 */
+ BE_BIT rsvd3[4]; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_PCIE_DEVCAP_CSR_AMAP {
+ u32 dw[1];
+};
+
+/* PCI Express Device Control/Status Registers. */
+struct BE_PCICFG_PCIE_CONTROL_STATUS_CSR_AMAP {
+ BE_BIT CorrErrReportEn; /* DWORD 0 */
+ BE_BIT NonFatalErrReportEn; /* DWORD 0 */
+ BE_BIT FatalErrReportEn; /* DWORD 0 */
+ BE_BIT UnsuppReqReportEn; /* DWORD 0 */
+ BE_BIT EnableRelaxOrder; /* DWORD 0 */
+ BE_BIT Max_Payload_Size[3]; /* DWORD 0 */
+ BE_BIT ExtendTagFieldEnable; /* DWORD 0 */
+ BE_BIT PhantomFnEnable; /* DWORD 0 */
+ BE_BIT AuxPwrPMEnable; /* DWORD 0 */
+ BE_BIT EnableNoSnoop; /* DWORD 0 */
+ BE_BIT Max_Read_Req_Size[3]; /* DWORD 0 */
+ BE_BIT rsvd0; /* DWORD 0 */
+ BE_BIT CorrErrDetect; /* DWORD 0 */
+ BE_BIT NonFatalErrDetect; /* DWORD 0 */
+ BE_BIT FatalErrDetect; /* DWORD 0 */
+ BE_BIT UnsuppReqDetect; /* DWORD 0 */
+ BE_BIT AuxPwrDetect; /* DWORD 0 */
+ BE_BIT TransPending; /* DWORD 0 */
+ BE_BIT rsvd1[10]; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_PCIE_CONTROL_STATUS_CSR_AMAP {
+ u32 dw[1];
+};
+
+/* PCI Express Link Capabilities Register. */
+struct BE_PCICFG_PCIE_LINK_CAP_CSR_AMAP {
+ BE_BIT MaxLinkSpeed[4]; /* DWORD 0 */
+ BE_BIT MaxLinkWidth[6]; /* DWORD 0 */
+ BE_BIT ASPMSupport[2]; /* DWORD 0 */
+ BE_BIT L0sExitLat[3]; /* DWORD 0 */
+ BE_BIT L1ExitLat[3]; /* DWORD 0 */
+ BE_BIT rsvd0[6]; /* DWORD 0 */
+ BE_BIT PortNum[8]; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_PCIE_LINK_CAP_CSR_AMAP {
+ u32 dw[1];
+};
+
+/* PCI Express Link Status Register. */
+struct BE_PCICFG_PCIE_LINK_STATUS_CSR_AMAP {
+ BE_BIT ASPMCtl[2]; /* DWORD 0 */
+ BE_BIT rsvd0; /* DWORD 0 */
+ BE_BIT ReadCmplBndry; /* DWORD 0 */
+ BE_BIT LinkDisable; /* DWORD 0 */
+ BE_BIT RetrainLink; /* DWORD 0 */
+ BE_BIT CommonClkConfig; /* DWORD 0 */
+ BE_BIT ExtendSync; /* DWORD 0 */
+ BE_BIT rsvd1[8]; /* DWORD 0 */
+ BE_BIT LinkSpeed[4]; /* DWORD 0 */
+ BE_BIT NegLinkWidth[6]; /* DWORD 0 */
+ BE_BIT LinkTrainErr; /* DWORD 0 */
+ BE_BIT LinkTrain; /* DWORD 0 */
+ BE_BIT SlotClkConfig; /* DWORD 0 */
+ BE_BIT rsvd2[3]; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_PCIE_LINK_STATUS_CSR_AMAP {
+ u32 dw[1];
+};
+
+/* PCI Express MSI Configuration Register. */
+struct BE_PCICFG_MSI_CSR_AMAP {
+ BE_BIT capid[8]; /* DWORD 0 */
+ BE_BIT nextptr[8]; /* DWORD 0 */
+ BE_BIT tablesize[11]; /* DWORD 0 */
+ BE_BIT rsvd0[3]; /* DWORD 0 */
+ BE_BIT funcmask; /* DWORD 0 */
+ BE_BIT en; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_MSI_CSR_AMAP {
+ u32 dw[1];
+};
+
+/* MSI-X Table Offset Register. */
+struct BE_PCICFG_MSIX_TABLE_CSR_AMAP {
+ BE_BIT tablebir[3]; /* DWORD 0 */
+ BE_BIT offset[29]; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_MSIX_TABLE_CSR_AMAP {
+ u32 dw[1];
+};
+
+/* MSI-X PBA Offset Register. */
+struct BE_PCICFG_MSIX_PBA_CSR_AMAP {
+ BE_BIT pbabir[3]; /* DWORD 0 */
+ BE_BIT offset[29]; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_MSIX_PBA_CSR_AMAP {
+ u32 dw[1];
+};
+
+/* PCI Express MSI-X Message Vector Control Register. */
+struct BE_PCICFG_MSIX_VECTOR_CONTROL_CSR_AMAP {
+ BE_BIT vector_control; /* DWORD 0 */
+ BE_BIT rsvd0[31]; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_MSIX_VECTOR_CONTROL_CSR_AMAP {
+ u32 dw[1];
+};
+
+/* PCI Express MSI-X Message Data Register. */
+struct BE_PCICFG_MSIX_MSG_DATA_CSR_AMAP {
+ BE_BIT data[16]; /* DWORD 0 */
+ BE_BIT rsvd0[16]; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_MSIX_MSG_DATA_CSR_AMAP {
+ u32 dw[1];
+};
+
+/* PCI Express MSI-X Message Address Register - High Part. */
+struct BE_PCICFG_MSIX_MSG_ADDR_HI_CSR_AMAP {
+ BE_BIT addr[32]; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_MSIX_MSG_ADDR_HI_CSR_AMAP {
+ u32 dw[1];
+};
+
+/* PCI Express MSI-X Message Address Register - Low Part. */
+struct BE_PCICFG_MSIX_MSG_ADDR_LO_CSR_AMAP {
+ BE_BIT rsvd0[2]; /* DWORD 0 */
+ BE_BIT addr[30]; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_MSIX_MSG_ADDR_LO_CSR_AMAP {
+ u32 dw[1];
+};
+
+struct BE_PCICFG_ANON_18_RSVD_AMAP {
+ BE_BIT rsvd0[32]; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_ANON_18_RSVD_AMAP {
+ u32 dw[1];
+};
+
+struct BE_PCICFG_ANON_19_RSVD_AMAP {
+ BE_BIT rsvd0[32]; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_ANON_19_RSVD_AMAP {
+ u32 dw[1];
+};
+
+struct BE_PCICFG_ANON_20_RSVD_AMAP {
+ BE_BIT rsvd0[32]; /* DWORD 0 */
+ BE_BIT rsvd1[25][32]; /* DWORD 1 */
+} SG_PACK;
+struct PCICFG_ANON_20_RSVD_AMAP {
+ u32 dw[26];
+};
+
+struct BE_PCICFG_ANON_21_RSVD_AMAP {
+ BE_BIT rsvd0[32]; /* DWORD 0 */
+ BE_BIT rsvd1[1919][32]; /* DWORD 1 */
+} SG_PACK;
+struct PCICFG_ANON_21_RSVD_AMAP {
+ u32 dw[1920];
+};
+
+struct BE_PCICFG_ANON_22_MESSAGE_AMAP {
+ struct BE_PCICFG_MSIX_VECTOR_CONTROL_CSR_AMAP vec_ctrl;
+ struct BE_PCICFG_MSIX_MSG_DATA_CSR_AMAP msg_data;
+ struct BE_PCICFG_MSIX_MSG_ADDR_HI_CSR_AMAP addr_hi;
+ struct BE_PCICFG_MSIX_MSG_ADDR_LO_CSR_AMAP addr_low;
+} SG_PACK;
+struct PCICFG_ANON_22_MESSAGE_AMAP {
+ u32 dw[4];
+};
+
+struct BE_PCICFG_ANON_23_RSVD_AMAP {
+ BE_BIT rsvd0[32]; /* DWORD 0 */
+ BE_BIT rsvd1[895][32]; /* DWORD 1 */
+} SG_PACK;
+struct PCICFG_ANON_23_RSVD_AMAP {
+ u32 dw[896];
+};
+
+/* These PCI Configuration Space registers are for the Storage Function of
+ * BladeEngine (Function 0). In the memory map of the registers below their
+ * table,
+ */
+struct BE_PCICFG0_CSRMAP_AMAP {
+ struct BE_PCICFG_ID_CSR_AMAP id;
+ BE_BIT rsvd0[32]; /* DWORD 1 */
+ BE_BIT rsvd1[32]; /* DWORD 2 */
+ BE_BIT rsvd2[32]; /* DWORD 3 */
+ struct BE_PCICFG_IOBAR_CSR_AMAP iobar;
+ struct BE_PCICFG_MEMBAR0_CSR_AMAP membar0;
+ struct BE_PCICFG_MEMBAR1_LO_CSR_AMAP membar1_lo;
+ struct BE_PCICFG_MEMBAR1_HI_CSR_AMAP membar1_hi;
+ struct BE_PCICFG_MEMBAR2_LO_CSR_AMAP membar2_lo;
+ struct BE_PCICFG_MEMBAR2_HI_CSR_AMAP membar2_hi;
+ BE_BIT rsvd3[32]; /* DWORD 10 */
+ struct BE_PCICFG_SUBSYSTEM_ID_F0_CSR_AMAP subsystem_id;
+ BE_BIT rsvd4[32]; /* DWORD 12 */
+ BE_BIT rsvd5[32]; /* DWORD 13 */
+ BE_BIT rsvd6[32]; /* DWORD 14 */
+ BE_BIT rsvd7[32]; /* DWORD 15 */
+ struct BE_PCICFG_SEMAPHORE_CSR_AMAP semaphore[4];
+ struct BE_PCICFG_SOFT_RESET_CSR_AMAP soft_reset;
+ BE_BIT rsvd8[32]; /* DWORD 21 */
+ struct BE_PCICFG_SCRATCHPAD_CSR_AMAP scratchpad;
+ BE_BIT rsvd9[32]; /* DWORD 23 */
+ BE_BIT rsvd10[32]; /* DWORD 24 */
+ BE_BIT rsvd11[32]; /* DWORD 25 */
+ BE_BIT rsvd12[32]; /* DWORD 26 */
+ BE_BIT rsvd13[32]; /* DWORD 27 */
+ BE_BIT rsvd14[2][32]; /* DWORD 28 */
+ BE_BIT rsvd15[32]; /* DWORD 30 */
+ BE_BIT rsvd16[32]; /* DWORD 31 */
+ BE_BIT rsvd17[8][32]; /* DWORD 32 */
+ struct BE_PCICFG_UE_STATUS_LOW_CSR_AMAP ue_status_low;
+ struct BE_PCICFG_UE_STATUS_HI_CSR_AMAP ue_status_hi;
+ struct BE_PCICFG_UE_STATUS_LOW_MASK_CSR_AMAP ue_status_low_mask;
+ struct BE_PCICFG_UE_STATUS_HI_MASK_CSR_AMAP ue_status_hi_mask;
+ struct BE_PCICFG_ONLINE0_CSR_AMAP online0;
+ struct BE_PCICFG_ONLINE1_CSR_AMAP online1;
+ BE_BIT rsvd18[32]; /* DWORD 46 */
+ BE_BIT rsvd19[32]; /* DWORD 47 */
+ BE_BIT rsvd20[32]; /* DWORD 48 */
+ BE_BIT rsvd21[32]; /* DWORD 49 */
+ struct BE_PCICFG_HOST_TIMER_INT_CTRL_CSR_AMAP host_timer_int_ctrl;
+ BE_BIT rsvd22[32]; /* DWORD 51 */
+ struct BE_PCICFG_PCIE_CAP_CSR_AMAP pcie_cap;
+ struct BE_PCICFG_PCIE_DEVCAP_CSR_AMAP pcie_devcap;
+ struct BE_PCICFG_PCIE_CONTROL_STATUS_CSR_AMAP pcie_control_status;
+ struct BE_PCICFG_PCIE_LINK_CAP_CSR_AMAP pcie_link_cap;
+ struct BE_PCICFG_PCIE_LINK_STATUS_CSR_AMAP pcie_link_status;
+ struct BE_PCICFG_MSI_CSR_AMAP msi;
+ struct BE_PCICFG_MSIX_TABLE_CSR_AMAP msix_table_offset;
+ struct BE_PCICFG_MSIX_PBA_CSR_AMAP msix_pba_offset;
+ BE_BIT rsvd23[32]; /* DWORD 60 */
+ BE_BIT rsvd24[32]; /* DWORD 61 */
+ BE_BIT rsvd25[32]; /* DWORD 62 */
+ BE_BIT rsvd26[32]; /* DWORD 63 */
+ BE_BIT rsvd27[32]; /* DWORD 64 */
+ BE_BIT rsvd28[32]; /* DWORD 65 */
+ BE_BIT rsvd29[32]; /* DWORD 66 */
+ BE_BIT rsvd30[32]; /* DWORD 67 */
+ BE_BIT rsvd31[32]; /* DWORD 68 */
+ BE_BIT rsvd32[32]; /* DWORD 69 */
+ BE_BIT rsvd33[32]; /* DWORD 70 */
+ BE_BIT rsvd34[32]; /* DWORD 71 */
+ BE_BIT rsvd35[32]; /* DWORD 72 */
+ BE_BIT rsvd36[32]; /* DWORD 73 */
+ BE_BIT rsvd37[32]; /* DWORD 74 */
+ BE_BIT rsvd38[32]; /* DWORD 75 */
+ BE_BIT rsvd39[32]; /* DWORD 76 */
+ BE_BIT rsvd40[32]; /* DWORD 77 */
+ BE_BIT rsvd41[32]; /* DWORD 78 */
+ BE_BIT rsvd42[32]; /* DWORD 79 */
+ BE_BIT rsvd43[32]; /* DWORD 80 */
+ BE_BIT rsvd44[32]; /* DWORD 81 */
+ BE_BIT rsvd45[32]; /* DWORD 82 */
+ BE_BIT rsvd46[32]; /* DWORD 83 */
+ BE_BIT rsvd47[32]; /* DWORD 84 */
+ BE_BIT rsvd48[32]; /* DWORD 85 */
+ BE_BIT rsvd49[32]; /* DWORD 86 */
+ BE_BIT rsvd50[32]; /* DWORD 87 */
+ BE_BIT rsvd51[32]; /* DWORD 88 */
+ BE_BIT rsvd52[32]; /* DWORD 89 */
+ BE_BIT rsvd53[32]; /* DWORD 90 */
+ BE_BIT rsvd54[32]; /* DWORD 91 */
+ BE_BIT rsvd55[32]; /* DWORD 92 */
+ BE_BIT rsvd56[832]; /* DWORD 93 */
+ BE_BIT rsvd57[32]; /* DWORD 119 */
+ BE_BIT rsvd58[32]; /* DWORD 120 */
+ BE_BIT rsvd59[32]; /* DWORD 121 */
+ BE_BIT rsvd60[32]; /* DWORD 122 */
+ BE_BIT rsvd61[32]; /* DWORD 123 */
+ BE_BIT rsvd62[32]; /* DWORD 124 */
+ BE_BIT rsvd63[32]; /* DWORD 125 */
+ BE_BIT rsvd64[32]; /* DWORD 126 */
+ BE_BIT rsvd65[32]; /* DWORD 127 */
+ BE_BIT rsvd66[61440]; /* DWORD 128 */
+ struct BE_PCICFG_ANON_22_MESSAGE_AMAP message[32];
+ BE_BIT rsvd67[28672]; /* DWORD 2176 */
+ BE_BIT rsvd68[32]; /* DWORD 3072 */
+ BE_BIT rsvd69[1023][32]; /* DWORD 3073 */
+} SG_PACK;
+struct PCICFG0_CSRMAP_AMAP {
+ u32 dw[4096];
+};
+
+struct BE_PCICFG_ANON_24_RSVD_AMAP {
+ BE_BIT rsvd0[32]; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_ANON_24_RSVD_AMAP {
+ u32 dw[1];
+};
+
+struct BE_PCICFG_ANON_25_RSVD_AMAP {
+ BE_BIT rsvd0[32]; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_ANON_25_RSVD_AMAP {
+ u32 dw[1];
+};
+
+struct BE_PCICFG_ANON_26_RSVD_AMAP {
+ BE_BIT rsvd0[32]; /* DWORD 0 */
+} SG_PACK;
+struct PCICFG_ANON_26_RSVD_AMAP {
+ u32 dw[1];
+};
+
+struct BE_PCICFG_ANON_27_RSVD_AMAP {
+ BE_BIT rsvd0[32]; /* DWORD 0 */
+ BE_BIT rsvd1[32]; /* DWORD 1 */
+} SG_PACK;
+struct PCICFG_ANON_27_RSVD_AMAP {
+ u32 dw[2];
+};
+
+struct BE_PCICFG_ANON_28_RSVD_AMAP {
+ BE_BIT rsvd0[32]; /* DWORD 0 */
+ BE_BIT rsvd1[3][32]; /* DWORD 1 */
+} SG_PACK;
+struct PCICFG_ANON_28_RSVD_AMAP {
+ u32 dw[4];
+};
+
+struct BE_PCICFG_ANON_29_RSVD_AMAP {
+ BE_BIT rsvd0[32]; /* DWORD 0 */
+ BE_BIT rsvd1[36][32]; /* DWORD 1 */
+} SG_PACK;
+struct PCICFG_ANON_29_RSVD_AMAP {
+ u32 dw[37];
+};
+
+struct BE_PCICFG_ANON_30_RSVD_AMAP {
+ BE_BIT rsvd0[32]; /* DWORD 0 */
+ BE_BIT rsvd1[1930][32]; /* DWORD 1 */
+} SG_PACK;
+struct PCICFG_ANON_30_RSVD_AMAP {
+ u32 dw[1931];
+};
+
+struct BE_PCICFG_ANON_31_MESSAGE_AMAP {
+ struct BE_PCICFG_MSIX_VECTOR_CONTROL_CSR_AMAP vec_ctrl;
+ struct BE_PCICFG_MSIX_MSG_DATA_CSR_AMAP msg_data;
+ struct BE_PCICFG_MSIX_MSG_ADDR_HI_CSR_AMAP addr_hi;
+ struct BE_PCICFG_MSIX_MSG_ADDR_LO_CSR_AMAP addr_low;
+} SG_PACK;
+struct PCICFG_ANON_31_MESSAGE_AMAP {
+ u32 dw[4];
+};
+
+struct BE_PCICFG_ANON_32_RSVD_AMAP {
+ BE_BIT rsvd0[32]; /* DWORD 0 */
+ BE_BIT rsvd1[895][32]; /* DWORD 1 */
+} SG_PACK;
+struct PCICFG_ANON_32_RSVD_AMAP {
+ u32 dw[896];
+};
+
+/* This PCI configuration space register map is for the Networking Function of
+ * BladeEngine (Function 1).
+ */
+struct BE_PCICFG1_CSRMAP_AMAP {
+ struct BE_PCICFG_ID_CSR_AMAP id;
+ BE_BIT rsvd0[32]; /* DWORD 1 */
+ BE_BIT rsvd1[32]; /* DWORD 2 */
+ BE_BIT rsvd2[32]; /* DWORD 3 */
+ struct BE_PCICFG_IOBAR_CSR_AMAP iobar;
+ struct BE_PCICFG_MEMBAR0_CSR_AMAP membar0;
+ struct BE_PCICFG_MEMBAR1_LO_CSR_AMAP membar1_lo;
+ struct BE_PCICFG_MEMBAR1_HI_CSR_AMAP membar1_hi;
+ struct BE_PCICFG_MEMBAR2_LO_CSR_AMAP membar2_lo;
+ struct BE_PCICFG_MEMBAR2_HI_CSR_AMAP membar2_hi;
+ BE_BIT rsvd3[32]; /* DWORD 10 */
+ struct BE_PCICFG_SUBSYSTEM_ID_F1_CSR_AMAP subsystem_id;
+ BE_BIT rsvd4[32]; /* DWORD 12 */
+ BE_BIT rsvd5[32]; /* DWORD 13 */
+ BE_BIT rsvd6[32]; /* DWORD 14 */
+ BE_BIT rsvd7[32]; /* DWORD 15 */
+ struct BE_PCICFG_SEMAPHORE_CSR_AMAP semaphore[4];
+ struct BE_PCICFG_SOFT_RESET_CSR_AMAP soft_reset;
+ BE_BIT rsvd8[32]; /* DWORD 21 */
+ struct BE_PCICFG_SCRATCHPAD_CSR_AMAP scratchpad;
+ BE_BIT rsvd9[32]; /* DWORD 23 */
+ BE_BIT rsvd10[32]; /* DWORD 24 */
+ BE_BIT rsvd11[32]; /* DWORD 25 */
+ BE_BIT rsvd12[32]; /* DWORD 26 */
+ BE_BIT rsvd13[32]; /* DWORD 27 */
+ BE_BIT rsvd14[2][32]; /* DWORD 28 */
+ BE_BIT rsvd15[32]; /* DWORD 30 */
+ BE_BIT rsvd16[32]; /* DWORD 31 */
+ BE_BIT rsvd17[8][32]; /* DWORD 32 */
+ struct BE_PCICFG_UE_STATUS_LOW_CSR_AMAP ue_status_low;
+ struct BE_PCICFG_UE_STATUS_HI_CSR_AMAP ue_status_hi;
+ struct BE_PCICFG_UE_STATUS_LOW_MASK_CSR_AMAP ue_status_low_mask;
+ struct BE_PCICFG_UE_STATUS_HI_MASK_CSR_AMAP ue_status_hi_mask;
+ struct BE_PCICFG_ONLINE0_CSR_AMAP online0;
+ struct BE_PCICFG_ONLINE1_CSR_AMAP online1;
+ BE_BIT rsvd18[32]; /* DWORD 46 */
+ BE_BIT rsvd19[32]; /* DWORD 47 */
+ BE_BIT rsvd20[32]; /* DWORD 48 */
+ BE_BIT rsvd21[32]; /* DWORD 49 */
+ struct BE_PCICFG_HOST_TIMER_INT_CTRL_CSR_AMAP host_timer_int_ctrl;
+ BE_BIT rsvd22[32]; /* DWORD 51 */
+ struct BE_PCICFG_PCIE_CAP_CSR_AMAP pcie_cap;
+ struct BE_PCICFG_PCIE_DEVCAP_CSR_AMAP pcie_devcap;
+ struct BE_PCICFG_PCIE_CONTROL_STATUS_CSR_AMAP pcie_control_status;
+ struct BE_PCICFG_PCIE_LINK_CAP_CSR_AMAP pcie_link_cap;
+ struct BE_PCICFG_PCIE_LINK_STATUS_CSR_AMAP pcie_link_status;
+ struct BE_PCICFG_MSI_CSR_AMAP msi;
+ struct BE_PCICFG_MSIX_TABLE_CSR_AMAP msix_table_offset;
+ struct BE_PCICFG_MSIX_PBA_CSR_AMAP msix_pba_offset;
+ BE_BIT rsvd23[64]; /* DWORD 60 */
+ BE_BIT rsvd24[32]; /* DWORD 62 */
+ BE_BIT rsvd25[32]; /* DWORD 63 */
+ BE_BIT rsvd26[32]; /* DWORD 64 */
+ BE_BIT rsvd27[32]; /* DWORD 65 */
+ BE_BIT rsvd28[32]; /* DWORD 66 */
+ BE_BIT rsvd29[32]; /* DWORD 67 */
+ BE_BIT rsvd30[32]; /* DWORD 68 */
+ BE_BIT rsvd31[32]; /* DWORD 69 */
+ BE_BIT rsvd32[32]; /* DWORD 70 */
+ BE_BIT rsvd33[32]; /* DWORD 71 */
+ BE_BIT rsvd34[32]; /* DWORD 72 */
+ BE_BIT rsvd35[32]; /* DWORD 73 */
+ BE_BIT rsvd36[32]; /* DWORD 74 */
+ BE_BIT rsvd37[128]; /* DWORD 75 */
+ BE_BIT rsvd38[32]; /* DWORD 79 */
+ BE_BIT rsvd39[1184]; /* DWORD 80 */
+ BE_BIT rsvd40[61792]; /* DWORD 117 */
+ struct BE_PCICFG_ANON_31_MESSAGE_AMAP message[32];
+ BE_BIT rsvd41[28672]; /* DWORD 2176 */
+ BE_BIT rsvd42[32]; /* DWORD 3072 */
+ BE_BIT rsvd43[1023][32]; /* DWORD 3073 */
+} SG_PACK;
+struct PCICFG1_CSRMAP_AMAP {
+ u32 dw[4096];
+};
+
+#endif /* __pcicfg_amap_h__ */
--
1.5.5
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