Date:	Tue, 03 Jun 2008 02:50:42 -0700
From:	"Subbu Seetharaman" <subbus@...verengines.com>
To:	netdev@...r.kernel.org
Subject:  [PATCH 10/12] BE NIC driver - f/w header files

Signed-off-by: Subbu Seetharaman <subbus@...verengines.com>
---
 drivers/message/beclib/fw/amap/pcicfg.h |  825 +++++++++++++++++++++++++++++++
 1 files changed, 825 insertions(+), 0 deletions(-)
 create mode 100644 drivers/message/beclib/fw/amap/pcicfg.h

diff --git a/drivers/message/beclib/fw/amap/pcicfg.h b/drivers/message/beclib/fw/amap/pcicfg.h
new file mode 100644
index 0000000..37c19f8
--- /dev/null
+++ b/drivers/message/beclib/fw/amap/pcicfg.h
@@ -0,0 +1,825 @@
+/*
+ * Copyright (C) 2005 - 2008 ServerEngines
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.  The full GNU General
+ * Public License is included in this distribution in the file called COPYING.
+ *
+ * Contact Information:
+ * linux-drivers@...verengines.com
+ *
+ * ServerEngines
+ * 209 N. Fair Oaks Ave
+ * Sunnyvale, CA 94085
+ */
+/*
+ * Autogenerated by srcgen version: 0127
+ */
+#ifndef __pcicfg_amap_h__
+#define __pcicfg_amap_h__
+
+/* Vendor and Device ID Register. */
+struct BE_PCICFG_ID_CSR_AMAP {
+	BE_BIT vendorid[16];	/* DWORD 0 */
+	BE_BIT deviceid[16];	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_ID_CSR_AMAP {
+	u32 dw[1];
+};
+
+/* IO Bar Register. */
+struct BE_PCICFG_IOBAR_CSR_AMAP {
+	BE_BIT iospace;		/* DWORD 0 */
+	BE_BIT rsvd0[7];	/* DWORD 0 */
+	BE_BIT iobar[24];	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_IOBAR_CSR_AMAP {
+	u32 dw[1];
+};
+
+/* Memory BAR 0 Register. */
+struct BE_PCICFG_MEMBAR0_CSR_AMAP {
+	BE_BIT memspace;	/* DWORD 0 */
+	BE_BIT type[2];		/* DWORD 0 */
+	BE_BIT pf;		/* DWORD 0 */
+	BE_BIT rsvd0[10];	/* DWORD 0 */
+	BE_BIT membar0[18];	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_MEMBAR0_CSR_AMAP {
+	u32 dw[1];
+};
+
+/* Memory BAR 1 - Low Address Register. */
+struct BE_PCICFG_MEMBAR1_LO_CSR_AMAP {
+	BE_BIT memspace;	/* DWORD 0 */
+	BE_BIT type[2];		/* DWORD 0 */
+	BE_BIT pf;		/* DWORD 0 */
+	BE_BIT rsvd0[13];	/* DWORD 0 */
+	BE_BIT membar1lo[15];	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_MEMBAR1_LO_CSR_AMAP {
+	u32 dw[1];
+};
+
+/* Memory BAR 1 - High Address Register. */
+struct BE_PCICFG_MEMBAR1_HI_CSR_AMAP {
+	BE_BIT membar1hi[32];	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_MEMBAR1_HI_CSR_AMAP {
+	u32 dw[1];
+};
+
+/* Memory BAR 2 - Low Address Register. */
+struct BE_PCICFG_MEMBAR2_LO_CSR_AMAP {
+	BE_BIT memspace;	/* DWORD 0 */
+	BE_BIT type[2];		/* DWORD 0 */
+	BE_BIT pf;		/* DWORD 0 */
+	BE_BIT rsvd0[17];	/* DWORD 0 */
+	BE_BIT membar2lo[11];	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_MEMBAR2_LO_CSR_AMAP {
+	u32 dw[1];
+};
+
+/* Memory BAR 2 - High Address Register. */
+struct BE_PCICFG_MEMBAR2_HI_CSR_AMAP {
+	BE_BIT membar2hi[32];	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_MEMBAR2_HI_CSR_AMAP {
+	u32 dw[1];
+};
+
+/* Subsystem Vendor and ID (Function 0) Register. */
+struct BE_PCICFG_SUBSYSTEM_ID_F0_CSR_AMAP {
+	BE_BIT subsys_vendor_id[16];	/* DWORD 0 */
+	BE_BIT subsys_id[16];	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_SUBSYSTEM_ID_F0_CSR_AMAP {
+	u32 dw[1];
+};
+
+/* Subsystem Vendor and ID (Function 1) Register. */
+struct BE_PCICFG_SUBSYSTEM_ID_F1_CSR_AMAP {
+	BE_BIT subsys_vendor_id[16];	/* DWORD 0 */
+	BE_BIT subsys_id[16];	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_SUBSYSTEM_ID_F1_CSR_AMAP {
+	u32 dw[1];
+};
+
+/* Semaphore Register. */
+struct BE_PCICFG_SEMAPHORE_CSR_AMAP {
+	BE_BIT locked;		/* DWORD 0 */
+	BE_BIT rsvd0[31];	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_SEMAPHORE_CSR_AMAP {
+	u32 dw[1];
+};
+
+/* Soft Reset Register. */
+struct BE_PCICFG_SOFT_RESET_CSR_AMAP {
+	BE_BIT rsvd0[7];	/* DWORD 0 */
+	BE_BIT softreset;	/* DWORD 0 */
+	BE_BIT rsvd1[16];	/* DWORD 0 */
+	BE_BIT nec_ll_rcvdetect_i[8];	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_SOFT_RESET_CSR_AMAP {
+	u32 dw[1];
+};
+
+/* Unrecoverable Error Status (Low) Register. Each bit corresponds to
+ * an internal Unrecoverable Error.  These are set by hardware and may be
+ * cleared by writing a one to the respective bit(s) to be cleared.  Any
+ * bit being set that is also unmasked will result in Unrecoverable Error
+ * interrupt notification to the host CPU and/or Server Management chip
+ * and the transitioning of BladeEngine to an Offline state.
+ */
+struct BE_PCICFG_UE_STATUS_LOW_CSR_AMAP {
+	BE_BIT cev_ue_status;	/* DWORD 0 */
+	BE_BIT ctx_ue_status;	/* DWORD 0 */
+	BE_BIT dbuf_ue_status;	/* DWORD 0 */
+	BE_BIT erx_ue_status;	/* DWORD 0 */
+	BE_BIT host_ue_status;	/* DWORD 0 */
+	BE_BIT mpu_ue_status;	/* DWORD 0 */
+	BE_BIT ndma_ue_status;	/* DWORD 0 */
+	BE_BIT ptc_ue_status;	/* DWORD 0 */
+	BE_BIT rdma_ue_status;	/* DWORD 0 */
+	BE_BIT rxf_ue_status;	/* DWORD 0 */
+	BE_BIT rxips_ue_status;	/* DWORD 0 */
+	BE_BIT rxulp0_ue_status;	/* DWORD 0 */
+	BE_BIT rxulp1_ue_status;	/* DWORD 0 */
+	BE_BIT rxulp2_ue_status;	/* DWORD 0 */
+	BE_BIT tim_ue_status;	/* DWORD 0 */
+	BE_BIT tpost_ue_status;	/* DWORD 0 */
+	BE_BIT tpre_ue_status;	/* DWORD 0 */
+	BE_BIT txips_ue_status;	/* DWORD 0 */
+	BE_BIT txulp0_ue_status;	/* DWORD 0 */
+	BE_BIT txulp1_ue_status;	/* DWORD 0 */
+	BE_BIT uc_ue_status;	/* DWORD 0 */
+	BE_BIT wdma_ue_status;	/* DWORD 0 */
+	BE_BIT txulp2_ue_status;	/* DWORD 0 */
+	BE_BIT host1_ue_status;	/* DWORD 0 */
+	BE_BIT p0_ob_link_ue_status;	/* DWORD 0 */
+	BE_BIT p1_ob_link_ue_status;	/* DWORD 0 */
+	BE_BIT host_gpio_ue_status;	/* DWORD 0 */
+	BE_BIT mbox_netw_ue_status;	/* DWORD 0 */
+	BE_BIT mbox_stor_ue_status;	/* DWORD 0 */
+	BE_BIT axgmac0_ue_status;	/* DWORD 0 */
+	BE_BIT axgmac1_ue_status;	/* DWORD 0 */
+	BE_BIT mpu_intpend_ue_status;	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_UE_STATUS_LOW_CSR_AMAP {
+	u32 dw[1];
+};
+
+/* Unrecoverable Error Status (High) Register. Each bit corresponds to
+ * an internal Unrecoverable Error.  These are set by hardware and may be
+ * cleared by writing a one to the respective bit(s) to be cleared.  Any
+ * bit being set that is also unmasked will result in Unrecoverable Error
+ * interrupt notification to the host CPU and/or Server Management chip;
+ * and the transitioning of BladeEngine to an Offline state.
+ */
+struct BE_PCICFG_UE_STATUS_HI_CSR_AMAP {
+	BE_BIT jtag_ue_status;	/* DWORD 0 */
+	BE_BIT lpcmemhost_ue_status;	/* DWORD 0 */
+	BE_BIT mgmt_mac_ue_status;	/* DWORD 0 */
+	BE_BIT mpu_iram_ue_status;	/* DWORD 0 */
+	BE_BIT pcs0online_ue_status;	/* DWORD 0 */
+	BE_BIT pcs1online_ue_status;	/* DWORD 0 */
+	BE_BIT pctl0_ue_status;	/* DWORD 0 */
+	BE_BIT pctl1_ue_status;	/* DWORD 0 */
+	BE_BIT pmem_ue_status;	/* DWORD 0 */
+	BE_BIT rr_ue_status;	/* DWORD 0 */
+	BE_BIT rxpp_ue_status;	/* DWORD 0 */
+	BE_BIT txpb_ue_status;	/* DWORD 0 */
+	BE_BIT txp_ue_status;	/* DWORD 0 */
+	BE_BIT xaui_ue_status;	/* DWORD 0 */
+	BE_BIT arm_ue_status;	/* DWORD 0 */
+	BE_BIT ipc_ue_status;	/* DWORD 0 */
+	BE_BIT rsvd0[16];	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_UE_STATUS_HI_CSR_AMAP {
+	u32 dw[1];
+};
+
+/* Unrecoverable Error Mask (Low) Register. Each bit, when set to one,
+ * will mask the associated Unrecoverable  Error status bit from notification
+ * of Unrecoverable Error to the host CPU and/or Server Managment chip and the
+ * transitioning of all BladeEngine units to an Offline state.
+ */
+struct BE_PCICFG_UE_STATUS_LOW_MASK_CSR_AMAP {
+	BE_BIT cev_ue_mask;	/* DWORD 0 */
+	BE_BIT ctx_ue_mask;	/* DWORD 0 */
+	BE_BIT dbuf_ue_mask;	/* DWORD 0 */
+	BE_BIT erx_ue_mask;	/* DWORD 0 */
+	BE_BIT host_ue_mask;	/* DWORD 0 */
+	BE_BIT mpu_ue_mask;	/* DWORD 0 */
+	BE_BIT ndma_ue_mask;	/* DWORD 0 */
+	BE_BIT ptc_ue_mask;	/* DWORD 0 */
+	BE_BIT rdma_ue_mask;	/* DWORD 0 */
+	BE_BIT rxf_ue_mask;	/* DWORD 0 */
+	BE_BIT rxips_ue_mask;	/* DWORD 0 */
+	BE_BIT rxulp0_ue_mask;	/* DWORD 0 */
+	BE_BIT rxulp1_ue_mask;	/* DWORD 0 */
+	BE_BIT rxulp2_ue_mask;	/* DWORD 0 */
+	BE_BIT tim_ue_mask;	/* DWORD 0 */
+	BE_BIT tpost_ue_mask;	/* DWORD 0 */
+	BE_BIT tpre_ue_mask;	/* DWORD 0 */
+	BE_BIT txips_ue_mask;	/* DWORD 0 */
+	BE_BIT txulp0_ue_mask;	/* DWORD 0 */
+	BE_BIT txulp1_ue_mask;	/* DWORD 0 */
+	BE_BIT uc_ue_mask;	/* DWORD 0 */
+	BE_BIT wdma_ue_mask;	/* DWORD 0 */
+	BE_BIT txulp2_ue_mask;	/* DWORD 0 */
+	BE_BIT host1_ue_mask;	/* DWORD 0 */
+	BE_BIT p0_ob_link_ue_mask;	/* DWORD 0 */
+	BE_BIT p1_ob_link_ue_mask;	/* DWORD 0 */
+	BE_BIT host_gpio_ue_mask;	/* DWORD 0 */
+	BE_BIT mbox_netw_ue_mask;	/* DWORD 0 */
+	BE_BIT mbox_stor_ue_mask;	/* DWORD 0 */
+	BE_BIT axgmac0_ue_mask;	/* DWORD 0 */
+	BE_BIT axgmac1_ue_mask;	/* DWORD 0 */
+	BE_BIT mpu_intpend_ue_mask;	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_UE_STATUS_LOW_MASK_CSR_AMAP {
+	u32 dw[1];
+};
+
+/* Unrecoverable Error Mask (High) Register. Each bit, when set to one,
+ * will mask the associated Unrecoverable Error status bit from notification
+ * of Unrecoverable Error to the host CPU and/or Server Managment chip and the
+ * transitioning of all BladeEngine units to an Offline state.
+ */
+struct BE_PCICFG_UE_STATUS_HI_MASK_CSR_AMAP {
+	BE_BIT jtag_ue_mask;	/* DWORD 0 */
+	BE_BIT lpcmemhost_ue_mask;	/* DWORD 0 */
+	BE_BIT mgmt_mac_ue_mask;	/* DWORD 0 */
+	BE_BIT mpu_iram_ue_mask;	/* DWORD 0 */
+	BE_BIT pcs0online_ue_mask;	/* DWORD 0 */
+	BE_BIT pcs1online_ue_mask;	/* DWORD 0 */
+	BE_BIT pctl0_ue_mask;	/* DWORD 0 */
+	BE_BIT pctl1_ue_mask;	/* DWORD 0 */
+	BE_BIT pmem_ue_mask;	/* DWORD 0 */
+	BE_BIT rr_ue_mask;	/* DWORD 0 */
+	BE_BIT rxpp_ue_mask;	/* DWORD 0 */
+	BE_BIT txpb_ue_mask;	/* DWORD 0 */
+	BE_BIT txp_ue_mask;	/* DWORD 0 */
+	BE_BIT xaui_ue_mask;	/* DWORD 0 */
+	BE_BIT arm_ue_mask;	/* DWORD 0 */
+	BE_BIT ipc_ue_mask;	/* DWORD 0 */
+	BE_BIT rsvd0[16];	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_UE_STATUS_HI_MASK_CSR_AMAP {
+	u32 dw[1];
+};
+
+/* Online Control Register 0. This register controls various units within
+ * BladeEngine being in an Online or Offline state.
+ */
+struct BE_PCICFG_ONLINE0_CSR_AMAP {
+	BE_BIT cev_online;	/* DWORD 0 */
+	BE_BIT ctx_online;	/* DWORD 0 */
+	BE_BIT dbuf_online;	/* DWORD 0 */
+	BE_BIT erx_online;	/* DWORD 0 */
+	BE_BIT host_online;	/* DWORD 0 */
+	BE_BIT mpu_online;	/* DWORD 0 */
+	BE_BIT ndma_online;	/* DWORD 0 */
+	BE_BIT ptc_online;	/* DWORD 0 */
+	BE_BIT rdma_online;	/* DWORD 0 */
+	BE_BIT rxf_online;	/* DWORD 0 */
+	BE_BIT rxips_online;	/* DWORD 0 */
+	BE_BIT rxulp0_online;	/* DWORD 0 */
+	BE_BIT rxulp1_online;	/* DWORD 0 */
+	BE_BIT rxulp2_online;	/* DWORD 0 */
+	BE_BIT tim_online;	/* DWORD 0 */
+	BE_BIT tpost_online;	/* DWORD 0 */
+	BE_BIT tpre_online;	/* DWORD 0 */
+	BE_BIT txips_online;	/* DWORD 0 */
+	BE_BIT txulp0_online;	/* DWORD 0 */
+	BE_BIT txulp1_online;	/* DWORD 0 */
+	BE_BIT uc_online;	/* DWORD 0 */
+	BE_BIT wdma_online;	/* DWORD 0 */
+	BE_BIT txulp2_online;	/* DWORD 0 */
+	BE_BIT host1_online;	/* DWORD 0 */
+	BE_BIT p0_ob_link_online;	/* DWORD 0 */
+	BE_BIT p1_ob_link_online;	/* DWORD 0 */
+	BE_BIT host_gpio_online;	/* DWORD 0 */
+	BE_BIT mbox_netw_online;	/* DWORD 0 */
+	BE_BIT mbox_stor_online;	/* DWORD 0 */
+	BE_BIT axgmac0_online;	/* DWORD 0 */
+	BE_BIT axgmac1_online;	/* DWORD 0 */
+	BE_BIT mpu_intpend_online;	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_ONLINE0_CSR_AMAP {
+	u32 dw[1];
+};
+
+/* Online Control Register 1. This register controls various units within
+ * BladeEngine being in an Online or Offline state.
+ */
+struct BE_PCICFG_ONLINE1_CSR_AMAP {
+	BE_BIT jtag_online;	/* DWORD 0 */
+	BE_BIT lpcmemhost_online;	/* DWORD 0 */
+	BE_BIT mgmt_mac_online;	/* DWORD 0 */
+	BE_BIT mpu_iram_online;	/* DWORD 0 */
+	BE_BIT pcs0online_online;	/* DWORD 0 */
+	BE_BIT pcs1online_online;	/* DWORD 0 */
+	BE_BIT pctl0_online;	/* DWORD 0 */
+	BE_BIT pctl1_online;	/* DWORD 0 */
+	BE_BIT pmem_online;	/* DWORD 0 */
+	BE_BIT rr_online;	/* DWORD 0 */
+	BE_BIT rxpp_online;	/* DWORD 0 */
+	BE_BIT txpb_online;	/* DWORD 0 */
+	BE_BIT txp_online;	/* DWORD 0 */
+	BE_BIT xaui_online;	/* DWORD 0 */
+	BE_BIT arm_online;	/* DWORD 0 */
+	BE_BIT ipc_online;	/* DWORD 0 */
+	BE_BIT rsvd0[16];	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_ONLINE1_CSR_AMAP {
+	u32 dw[1];
+};
+
+/* Host Timer Register. */
+struct BE_PCICFG_HOST_TIMER_INT_CTRL_CSR_AMAP {
+	BE_BIT hosttimer[24];	/* DWORD 0 */
+	BE_BIT hostintr;	/* DWORD 0 */
+	BE_BIT rsvd0[7];	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_HOST_TIMER_INT_CTRL_CSR_AMAP {
+	u32 dw[1];
+};
+
+/* Scratchpad Register (for software use). */
+struct BE_PCICFG_SCRATCHPAD_CSR_AMAP {
+	BE_BIT scratchpad[32];	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_SCRATCHPAD_CSR_AMAP {
+	u32 dw[1];
+};
+
+/* PCI Express Capabilities Register. */
+struct BE_PCICFG_PCIE_CAP_CSR_AMAP {
+	BE_BIT capid[8];	/* DWORD 0 */
+	BE_BIT nextcap[8];	/* DWORD 0 */
+	BE_BIT capver[4];	/* DWORD 0 */
+	BE_BIT devport[4];	/* DWORD 0 */
+	BE_BIT rsvd0[6];	/* DWORD 0 */
+	BE_BIT rsvd1[2];	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_PCIE_CAP_CSR_AMAP {
+	u32 dw[1];
+};
+
+/* PCI Express Device Capabilities Register. */
+struct BE_PCICFG_PCIE_DEVCAP_CSR_AMAP {
+	BE_BIT payload[3];	/* DWORD 0 */
+	BE_BIT rsvd0[3];	/* DWORD 0 */
+	BE_BIT lo_lat[3];	/* DWORD 0 */
+	BE_BIT l1_lat[3];	/* DWORD 0 */
+	BE_BIT rsvd1[3];	/* DWORD 0 */
+	BE_BIT rsvd2[3];	/* DWORD 0 */
+	BE_BIT pwr_value[8];	/* DWORD 0 */
+	BE_BIT pwr_scale[2];	/* DWORD 0 */
+	BE_BIT rsvd3[4];	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_PCIE_DEVCAP_CSR_AMAP {
+	u32 dw[1];
+};
+
+/* PCI Express Device Control/Status Registers. */
+struct BE_PCICFG_PCIE_CONTROL_STATUS_CSR_AMAP {
+	BE_BIT CorrErrReportEn;	/* DWORD 0 */
+	BE_BIT NonFatalErrReportEn;	/* DWORD 0 */
+	BE_BIT FatalErrReportEn;	/* DWORD 0 */
+	BE_BIT UnsuppReqReportEn;	/* DWORD 0 */
+	BE_BIT EnableRelaxOrder;	/* DWORD 0 */
+	BE_BIT Max_Payload_Size[3];	/* DWORD 0 */
+	BE_BIT ExtendTagFieldEnable;	/* DWORD 0 */
+	BE_BIT PhantomFnEnable;	/* DWORD 0 */
+	BE_BIT AuxPwrPMEnable;	/* DWORD 0 */
+	BE_BIT EnableNoSnoop;	/* DWORD 0 */
+	BE_BIT Max_Read_Req_Size[3];	/* DWORD 0 */
+	BE_BIT rsvd0;		/* DWORD 0 */
+	BE_BIT CorrErrDetect;	/* DWORD 0 */
+	BE_BIT NonFatalErrDetect;	/* DWORD 0 */
+	BE_BIT FatalErrDetect;	/* DWORD 0 */
+	BE_BIT UnsuppReqDetect;	/* DWORD 0 */
+	BE_BIT AuxPwrDetect;	/* DWORD 0 */
+	BE_BIT TransPending;	/* DWORD 0 */
+	BE_BIT rsvd1[10];	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_PCIE_CONTROL_STATUS_CSR_AMAP {
+	u32 dw[1];
+};
+
+/* PCI Express Link Capabilities Register. */
+struct BE_PCICFG_PCIE_LINK_CAP_CSR_AMAP {
+	BE_BIT MaxLinkSpeed[4];	/* DWORD 0 */
+	BE_BIT MaxLinkWidth[6];	/* DWORD 0 */
+	BE_BIT ASPMSupport[2];	/* DWORD 0 */
+	BE_BIT L0sExitLat[3];	/* DWORD 0 */
+	BE_BIT L1ExitLat[3];	/* DWORD 0 */
+	BE_BIT rsvd0[6];	/* DWORD 0 */
+	BE_BIT PortNum[8];	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_PCIE_LINK_CAP_CSR_AMAP {
+	u32 dw[1];
+};
+
+/* PCI Express Link Status Register. */
+struct BE_PCICFG_PCIE_LINK_STATUS_CSR_AMAP {
+	BE_BIT ASPMCtl[2];	/* DWORD 0 */
+	BE_BIT rsvd0;		/* DWORD 0 */
+	BE_BIT ReadCmplBndry;	/* DWORD 0 */
+	BE_BIT LinkDisable;	/* DWORD 0 */
+	BE_BIT RetrainLink;	/* DWORD 0 */
+	BE_BIT CommonClkConfig;	/* DWORD 0 */
+	BE_BIT ExtendSync;	/* DWORD 0 */
+	BE_BIT rsvd1[8];	/* DWORD 0 */
+	BE_BIT LinkSpeed[4];	/* DWORD 0 */
+	BE_BIT NegLinkWidth[6];	/* DWORD 0 */
+	BE_BIT LinkTrainErr;	/* DWORD 0 */
+	BE_BIT LinkTrain;	/* DWORD 0 */
+	BE_BIT SlotClkConfig;	/* DWORD 0 */
+	BE_BIT rsvd2[3];	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_PCIE_LINK_STATUS_CSR_AMAP {
+	u32 dw[1];
+};
+
+/* PCI Express MSI Configuration Register. */
+struct BE_PCICFG_MSI_CSR_AMAP {
+	BE_BIT capid[8];	/* DWORD 0 */
+	BE_BIT nextptr[8];	/* DWORD 0 */
+	BE_BIT tablesize[11];	/* DWORD 0 */
+	BE_BIT rsvd0[3];	/* DWORD 0 */
+	BE_BIT funcmask;	/* DWORD 0 */
+	BE_BIT en;		/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_MSI_CSR_AMAP {
+	u32 dw[1];
+};
+
+/* MSI-X Table Offset Register. */
+struct BE_PCICFG_MSIX_TABLE_CSR_AMAP {
+	BE_BIT tablebir[3];	/* DWORD 0 */
+	BE_BIT offset[29];	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_MSIX_TABLE_CSR_AMAP {
+	u32 dw[1];
+};
+
+/* MSI-X PBA Offset Register. */
+struct BE_PCICFG_MSIX_PBA_CSR_AMAP {
+	BE_BIT pbabir[3];	/* DWORD 0 */
+	BE_BIT offset[29];	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_MSIX_PBA_CSR_AMAP {
+	u32 dw[1];
+};
+
+/* PCI Express MSI-X Message Vector Control Register. */
+struct BE_PCICFG_MSIX_VECTOR_CONTROL_CSR_AMAP {
+	BE_BIT vector_control;	/* DWORD 0 */
+	BE_BIT rsvd0[31];	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_MSIX_VECTOR_CONTROL_CSR_AMAP {
+	u32 dw[1];
+};
+
+/* PCI Express MSI-X Message Data Register. */
+struct BE_PCICFG_MSIX_MSG_DATA_CSR_AMAP {
+	BE_BIT data[16];	/* DWORD 0 */
+	BE_BIT rsvd0[16];	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_MSIX_MSG_DATA_CSR_AMAP {
+	u32 dw[1];
+};
+
+/* PCI Express MSI-X Message Address Register - High Part. */
+struct BE_PCICFG_MSIX_MSG_ADDR_HI_CSR_AMAP {
+	BE_BIT addr[32];	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_MSIX_MSG_ADDR_HI_CSR_AMAP {
+	u32 dw[1];
+};
+
+/* PCI Express MSI-X Message Address Register - Low Part. */
+struct BE_PCICFG_MSIX_MSG_ADDR_LO_CSR_AMAP {
+	BE_BIT rsvd0[2];	/* DWORD 0 */
+	BE_BIT addr[30];	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_MSIX_MSG_ADDR_LO_CSR_AMAP {
+	u32 dw[1];
+};
+
+struct BE_PCICFG_ANON_18_RSVD_AMAP {
+	BE_BIT rsvd0[32];	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_ANON_18_RSVD_AMAP {
+	u32 dw[1];
+};
+
+struct BE_PCICFG_ANON_19_RSVD_AMAP {
+	BE_BIT rsvd0[32];	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_ANON_19_RSVD_AMAP {
+	u32 dw[1];
+};
+
+struct BE_PCICFG_ANON_20_RSVD_AMAP {
+	BE_BIT rsvd0[32];	/* DWORD 0 */
+	BE_BIT rsvd1[25][32];	/* DWORD 1 */
+} SG_PACK;
+struct PCICFG_ANON_20_RSVD_AMAP {
+	u32 dw[26];
+};
+
+struct BE_PCICFG_ANON_21_RSVD_AMAP {
+	BE_BIT rsvd0[32];	/* DWORD 0 */
+	BE_BIT rsvd1[1919][32];	/* DWORD 1 */
+} SG_PACK;
+struct PCICFG_ANON_21_RSVD_AMAP {
+	u32 dw[1920];
+};
+
+struct BE_PCICFG_ANON_22_MESSAGE_AMAP {
+	struct BE_PCICFG_MSIX_VECTOR_CONTROL_CSR_AMAP vec_ctrl;
+	struct BE_PCICFG_MSIX_MSG_DATA_CSR_AMAP msg_data;
+	struct BE_PCICFG_MSIX_MSG_ADDR_HI_CSR_AMAP addr_hi;
+	struct BE_PCICFG_MSIX_MSG_ADDR_LO_CSR_AMAP addr_low;
+} SG_PACK;
+struct PCICFG_ANON_22_MESSAGE_AMAP {
+	u32 dw[4];
+};
+
+struct BE_PCICFG_ANON_23_RSVD_AMAP {
+	BE_BIT rsvd0[32];	/* DWORD 0 */
+	BE_BIT rsvd1[895][32];	/* DWORD 1 */
+} SG_PACK;
+struct PCICFG_ANON_23_RSVD_AMAP {
+	u32 dw[896];
+};
+
+/* These PCI Configuration Space registers are for the Storage  Function of
+ * BladeEngine (Function 0). In the memory map of the registers below their
+ * table,
+ */
+struct BE_PCICFG0_CSRMAP_AMAP {
+	struct BE_PCICFG_ID_CSR_AMAP id;
+	BE_BIT rsvd0[32];	/* DWORD 1 */
+	BE_BIT rsvd1[32];	/* DWORD 2 */
+	BE_BIT rsvd2[32];	/* DWORD 3 */
+	struct BE_PCICFG_IOBAR_CSR_AMAP iobar;
+	struct BE_PCICFG_MEMBAR0_CSR_AMAP membar0;
+	struct BE_PCICFG_MEMBAR1_LO_CSR_AMAP membar1_lo;
+	struct BE_PCICFG_MEMBAR1_HI_CSR_AMAP membar1_hi;
+	struct BE_PCICFG_MEMBAR2_LO_CSR_AMAP membar2_lo;
+	struct BE_PCICFG_MEMBAR2_HI_CSR_AMAP membar2_hi;
+	BE_BIT rsvd3[32];	/* DWORD 10 */
+	struct BE_PCICFG_SUBSYSTEM_ID_F0_CSR_AMAP subsystem_id;
+	BE_BIT rsvd4[32];	/* DWORD 12 */
+	BE_BIT rsvd5[32];	/* DWORD 13 */
+	BE_BIT rsvd6[32];	/* DWORD 14 */
+	BE_BIT rsvd7[32];	/* DWORD 15 */
+	struct BE_PCICFG_SEMAPHORE_CSR_AMAP semaphore[4];
+	struct BE_PCICFG_SOFT_RESET_CSR_AMAP soft_reset;
+	BE_BIT rsvd8[32];	/* DWORD 21 */
+	struct BE_PCICFG_SCRATCHPAD_CSR_AMAP scratchpad;
+	BE_BIT rsvd9[32];	/* DWORD 23 */
+	BE_BIT rsvd10[32];	/* DWORD 24 */
+	BE_BIT rsvd11[32];	/* DWORD 25 */
+	BE_BIT rsvd12[32];	/* DWORD 26 */
+	BE_BIT rsvd13[32];	/* DWORD 27 */
+	BE_BIT rsvd14[2][32];	/* DWORD 28 */
+	BE_BIT rsvd15[32];	/* DWORD 30 */
+	BE_BIT rsvd16[32];	/* DWORD 31 */
+	BE_BIT rsvd17[8][32];	/* DWORD 32 */
+	struct BE_PCICFG_UE_STATUS_LOW_CSR_AMAP ue_status_low;
+	struct BE_PCICFG_UE_STATUS_HI_CSR_AMAP ue_status_hi;
+	struct BE_PCICFG_UE_STATUS_LOW_MASK_CSR_AMAP ue_status_low_mask;
+	struct BE_PCICFG_UE_STATUS_HI_MASK_CSR_AMAP ue_status_hi_mask;
+	struct BE_PCICFG_ONLINE0_CSR_AMAP online0;
+	struct BE_PCICFG_ONLINE1_CSR_AMAP online1;
+	BE_BIT rsvd18[32];	/* DWORD 46 */
+	BE_BIT rsvd19[32];	/* DWORD 47 */
+	BE_BIT rsvd20[32];	/* DWORD 48 */
+	BE_BIT rsvd21[32];	/* DWORD 49 */
+	struct BE_PCICFG_HOST_TIMER_INT_CTRL_CSR_AMAP host_timer_int_ctrl;
+	BE_BIT rsvd22[32];	/* DWORD 51 */
+	struct BE_PCICFG_PCIE_CAP_CSR_AMAP pcie_cap;
+	struct BE_PCICFG_PCIE_DEVCAP_CSR_AMAP pcie_devcap;
+	struct BE_PCICFG_PCIE_CONTROL_STATUS_CSR_AMAP pcie_control_status;
+	struct BE_PCICFG_PCIE_LINK_CAP_CSR_AMAP pcie_link_cap;
+	struct BE_PCICFG_PCIE_LINK_STATUS_CSR_AMAP pcie_link_status;
+	struct BE_PCICFG_MSI_CSR_AMAP msi;
+	struct BE_PCICFG_MSIX_TABLE_CSR_AMAP msix_table_offset;
+	struct BE_PCICFG_MSIX_PBA_CSR_AMAP msix_pba_offset;
+	BE_BIT rsvd23[32];	/* DWORD 60 */
+	BE_BIT rsvd24[32];	/* DWORD 61 */
+	BE_BIT rsvd25[32];	/* DWORD 62 */
+	BE_BIT rsvd26[32];	/* DWORD 63 */
+	BE_BIT rsvd27[32];	/* DWORD 64 */
+	BE_BIT rsvd28[32];	/* DWORD 65 */
+	BE_BIT rsvd29[32];	/* DWORD 66 */
+	BE_BIT rsvd30[32];	/* DWORD 67 */
+	BE_BIT rsvd31[32];	/* DWORD 68 */
+	BE_BIT rsvd32[32];	/* DWORD 69 */
+	BE_BIT rsvd33[32];	/* DWORD 70 */
+	BE_BIT rsvd34[32];	/* DWORD 71 */
+	BE_BIT rsvd35[32];	/* DWORD 72 */
+	BE_BIT rsvd36[32];	/* DWORD 73 */
+	BE_BIT rsvd37[32];	/* DWORD 74 */
+	BE_BIT rsvd38[32];	/* DWORD 75 */
+	BE_BIT rsvd39[32];	/* DWORD 76 */
+	BE_BIT rsvd40[32];	/* DWORD 77 */
+	BE_BIT rsvd41[32];	/* DWORD 78 */
+	BE_BIT rsvd42[32];	/* DWORD 79 */
+	BE_BIT rsvd43[32];	/* DWORD 80 */
+	BE_BIT rsvd44[32];	/* DWORD 81 */
+	BE_BIT rsvd45[32];	/* DWORD 82 */
+	BE_BIT rsvd46[32];	/* DWORD 83 */
+	BE_BIT rsvd47[32];	/* DWORD 84 */
+	BE_BIT rsvd48[32];	/* DWORD 85 */
+	BE_BIT rsvd49[32];	/* DWORD 86 */
+	BE_BIT rsvd50[32];	/* DWORD 87 */
+	BE_BIT rsvd51[32];	/* DWORD 88 */
+	BE_BIT rsvd52[32];	/* DWORD 89 */
+	BE_BIT rsvd53[32];	/* DWORD 90 */
+	BE_BIT rsvd54[32];	/* DWORD 91 */
+	BE_BIT rsvd55[32];	/* DWORD 92 */
+	BE_BIT rsvd56[832];	/* DWORD 93 */
+	BE_BIT rsvd57[32];	/* DWORD 119 */
+	BE_BIT rsvd58[32];	/* DWORD 120 */
+	BE_BIT rsvd59[32];	/* DWORD 121 */
+	BE_BIT rsvd60[32];	/* DWORD 122 */
+	BE_BIT rsvd61[32];	/* DWORD 123 */
+	BE_BIT rsvd62[32];	/* DWORD 124 */
+	BE_BIT rsvd63[32];	/* DWORD 125 */
+	BE_BIT rsvd64[32];	/* DWORD 126 */
+	BE_BIT rsvd65[32];	/* DWORD 127 */
+	BE_BIT rsvd66[61440];	/* DWORD 128 */
+	struct BE_PCICFG_ANON_22_MESSAGE_AMAP message[32];
+	BE_BIT rsvd67[28672];	/* DWORD 2176 */
+	BE_BIT rsvd68[32];	/* DWORD 3072 */
+	BE_BIT rsvd69[1023][32];	/* DWORD 3073 */
+} SG_PACK;
+struct PCICFG0_CSRMAP_AMAP {
+	u32 dw[4096];
+};
+
+struct BE_PCICFG_ANON_24_RSVD_AMAP {
+	BE_BIT rsvd0[32];	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_ANON_24_RSVD_AMAP {
+	u32 dw[1];
+};
+
+struct BE_PCICFG_ANON_25_RSVD_AMAP {
+	BE_BIT rsvd0[32];	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_ANON_25_RSVD_AMAP {
+	u32 dw[1];
+};
+
+struct BE_PCICFG_ANON_26_RSVD_AMAP {
+	BE_BIT rsvd0[32];	/* DWORD 0 */
+} SG_PACK;
+struct PCICFG_ANON_26_RSVD_AMAP {
+	u32 dw[1];
+};
+
+struct BE_PCICFG_ANON_27_RSVD_AMAP {
+	BE_BIT rsvd0[32];	/* DWORD 0 */
+	BE_BIT rsvd1[32];	/* DWORD 1 */
+} SG_PACK;
+struct PCICFG_ANON_27_RSVD_AMAP {
+	u32 dw[2];
+};
+
+struct BE_PCICFG_ANON_28_RSVD_AMAP {
+	BE_BIT rsvd0[32];	/* DWORD 0 */
+	BE_BIT rsvd1[3][32];	/* DWORD 1 */
+} SG_PACK;
+struct PCICFG_ANON_28_RSVD_AMAP {
+	u32 dw[4];
+};
+
+struct BE_PCICFG_ANON_29_RSVD_AMAP {
+	BE_BIT rsvd0[32];	/* DWORD 0 */
+	BE_BIT rsvd1[36][32];	/* DWORD 1 */
+} SG_PACK;
+struct PCICFG_ANON_29_RSVD_AMAP {
+	u32 dw[37];
+};
+
+struct BE_PCICFG_ANON_30_RSVD_AMAP {
+	BE_BIT rsvd0[32];	/* DWORD 0 */
+	BE_BIT rsvd1[1930][32];	/* DWORD 1 */
+} SG_PACK;
+struct PCICFG_ANON_30_RSVD_AMAP {
+	u32 dw[1931];
+};
+
+struct BE_PCICFG_ANON_31_MESSAGE_AMAP {
+	struct BE_PCICFG_MSIX_VECTOR_CONTROL_CSR_AMAP vec_ctrl;
+	struct BE_PCICFG_MSIX_MSG_DATA_CSR_AMAP msg_data;
+	struct BE_PCICFG_MSIX_MSG_ADDR_HI_CSR_AMAP addr_hi;
+	struct BE_PCICFG_MSIX_MSG_ADDR_LO_CSR_AMAP addr_low;
+} SG_PACK;
+struct PCICFG_ANON_31_MESSAGE_AMAP {
+	u32 dw[4];
+};
+
+struct BE_PCICFG_ANON_32_RSVD_AMAP {
+	BE_BIT rsvd0[32];	/* DWORD 0 */
+	BE_BIT rsvd1[895][32];	/* DWORD 1 */
+} SG_PACK;
+struct PCICFG_ANON_32_RSVD_AMAP {
+	u32 dw[896];
+};
+
+/* This PCI configuration space register map is for the  Networking Function of
+ * BladeEngine (Function 1).
+ */
+struct BE_PCICFG1_CSRMAP_AMAP {
+	struct BE_PCICFG_ID_CSR_AMAP id;
+	BE_BIT rsvd0[32];	/* DWORD 1 */
+	BE_BIT rsvd1[32];	/* DWORD 2 */
+	BE_BIT rsvd2[32];	/* DWORD 3 */
+	struct BE_PCICFG_IOBAR_CSR_AMAP iobar;
+	struct BE_PCICFG_MEMBAR0_CSR_AMAP membar0;
+	struct BE_PCICFG_MEMBAR1_LO_CSR_AMAP membar1_lo;
+	struct BE_PCICFG_MEMBAR1_HI_CSR_AMAP membar1_hi;
+	struct BE_PCICFG_MEMBAR2_LO_CSR_AMAP membar2_lo;
+	struct BE_PCICFG_MEMBAR2_HI_CSR_AMAP membar2_hi;
+	BE_BIT rsvd3[32];	/* DWORD 10 */
+	struct BE_PCICFG_SUBSYSTEM_ID_F1_CSR_AMAP subsystem_id;
+	BE_BIT rsvd4[32];	/* DWORD 12 */
+	BE_BIT rsvd5[32];	/* DWORD 13 */
+	BE_BIT rsvd6[32];	/* DWORD 14 */
+	BE_BIT rsvd7[32];	/* DWORD 15 */
+	struct BE_PCICFG_SEMAPHORE_CSR_AMAP semaphore[4];
+	struct BE_PCICFG_SOFT_RESET_CSR_AMAP soft_reset;
+	BE_BIT rsvd8[32];	/* DWORD 21 */
+	struct BE_PCICFG_SCRATCHPAD_CSR_AMAP scratchpad;
+	BE_BIT rsvd9[32];	/* DWORD 23 */
+	BE_BIT rsvd10[32];	/* DWORD 24 */
+	BE_BIT rsvd11[32];	/* DWORD 25 */
+	BE_BIT rsvd12[32];	/* DWORD 26 */
+	BE_BIT rsvd13[32];	/* DWORD 27 */
+	BE_BIT rsvd14[2][32];	/* DWORD 28 */
+	BE_BIT rsvd15[32];	/* DWORD 30 */
+	BE_BIT rsvd16[32];	/* DWORD 31 */
+	BE_BIT rsvd17[8][32];	/* DWORD 32 */
+	struct BE_PCICFG_UE_STATUS_LOW_CSR_AMAP ue_status_low;
+	struct BE_PCICFG_UE_STATUS_HI_CSR_AMAP ue_status_hi;
+	struct BE_PCICFG_UE_STATUS_LOW_MASK_CSR_AMAP ue_status_low_mask;
+	struct BE_PCICFG_UE_STATUS_HI_MASK_CSR_AMAP ue_status_hi_mask;
+	struct BE_PCICFG_ONLINE0_CSR_AMAP online0;
+	struct BE_PCICFG_ONLINE1_CSR_AMAP online1;
+	BE_BIT rsvd18[32];	/* DWORD 46 */
+	BE_BIT rsvd19[32];	/* DWORD 47 */
+	BE_BIT rsvd20[32];	/* DWORD 48 */
+	BE_BIT rsvd21[32];	/* DWORD 49 */
+	struct BE_PCICFG_HOST_TIMER_INT_CTRL_CSR_AMAP host_timer_int_ctrl;
+	BE_BIT rsvd22[32];	/* DWORD 51 */
+	struct BE_PCICFG_PCIE_CAP_CSR_AMAP pcie_cap;
+	struct BE_PCICFG_PCIE_DEVCAP_CSR_AMAP pcie_devcap;
+	struct BE_PCICFG_PCIE_CONTROL_STATUS_CSR_AMAP pcie_control_status;
+	struct BE_PCICFG_PCIE_LINK_CAP_CSR_AMAP pcie_link_cap;
+	struct BE_PCICFG_PCIE_LINK_STATUS_CSR_AMAP pcie_link_status;
+	struct BE_PCICFG_MSI_CSR_AMAP msi;
+	struct BE_PCICFG_MSIX_TABLE_CSR_AMAP msix_table_offset;
+	struct BE_PCICFG_MSIX_PBA_CSR_AMAP msix_pba_offset;
+	BE_BIT rsvd23[64];	/* DWORD 60 */
+	BE_BIT rsvd24[32];	/* DWORD 62 */
+	BE_BIT rsvd25[32];	/* DWORD 63 */
+	BE_BIT rsvd26[32];	/* DWORD 64 */
+	BE_BIT rsvd27[32];	/* DWORD 65 */
+	BE_BIT rsvd28[32];	/* DWORD 66 */
+	BE_BIT rsvd29[32];	/* DWORD 67 */
+	BE_BIT rsvd30[32];	/* DWORD 68 */
+	BE_BIT rsvd31[32];	/* DWORD 69 */
+	BE_BIT rsvd32[32];	/* DWORD 70 */
+	BE_BIT rsvd33[32];	/* DWORD 71 */
+	BE_BIT rsvd34[32];	/* DWORD 72 */
+	BE_BIT rsvd35[32];	/* DWORD 73 */
+	BE_BIT rsvd36[32];	/* DWORD 74 */
+	BE_BIT rsvd37[128];	/* DWORD 75 */
+	BE_BIT rsvd38[32];	/* DWORD 79 */
+	BE_BIT rsvd39[1184];	/* DWORD 80 */
+	BE_BIT rsvd40[61792];	/* DWORD 117 */
+	struct BE_PCICFG_ANON_31_MESSAGE_AMAP message[32];
+	BE_BIT rsvd41[28672];	/* DWORD 2176 */
+	BE_BIT rsvd42[32];	/* DWORD 3072 */
+	BE_BIT rsvd43[1023][32];	/* DWORD 3073 */
+} SG_PACK;
+struct PCICFG1_CSRMAP_AMAP {
+	u32 dw[4096];
+};
+
+#endif /* __pcicfg_amap_h__ */
-- 
1.5.5

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