netdev - Re: qmgr for ixp4xx

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Date:	Thu, 04 Dec 2008 22:06:21 +0100
From:	Krzysztof Halasa <khc@...waw.pl>
To:	Miguel Ángel Álvarez <gotzoncabanes@...il.com>
Cc:	netdev@...r.kernel.org
Subject: Re: qmgr for ixp4xx

"Miguel Ángel Álvarez" <gotzoncabanes@...il.com> writes:

> As I am trying to use my HSSs as 4E1, I find that the FIFOs for each
> HDLC should be 1 word wide and not 4 words wide. I think that this
> finally means that when accessing the queues, I have to do the
> following modification.
>
> +++ linux-2.6.26.7/include/asm-arm/arch-ixp4xx/qmgr.h	2008-12-02
> 10:47:23.000000000 +0100
> @@ -67,16 +67,17 @@
>  void qmgr_release_queue(unsigned int queue);
>
>
> -static inline void qmgr_put_entry(unsigned int queue, u32 val)
> +static inline void qmgr_put_entry(unsigned int queue, unsigned int pipe,
> +                   u32 val)
>  {
>  	extern struct qmgr_regs __iomem *qmgr_regs;
> -	__raw_writel(val, &qmgr_regs->acc[queue][0]);
> +	__raw_writel(val, &qmgr_regs->acc[queue][pipe]);
>  }
>
> -static inline u32 qmgr_get_entry(unsigned int queue)
> +static inline u32 qmgr_get_entry(unsigned int queue, unsigned int pipe)
>  {
>  	extern struct qmgr_regs __iomem *qmgr_regs;
> -	return __raw_readl(&qmgr_regs->acc[queue][0]);
> +	return __raw_readl(&qmgr_regs->acc[queue][pipe]);
>  }

The FIFOs are some internal property of HDLC controller (it isn't
documented but they probably connect the bus master DMA controller to
the bit-stuffer and transmitter (and bit-destuffer and receiver in the
RX path)). You just need to send a message to HSS to tell it the
correct value.

Queues, on the other hand, can be 1, 2 or 4-words wide (32, 64 or 128
bits). I think nothing uses/needs 2 or 4-word queues so they aren't
implemented.

4E1 mode uses the same 1-word queues. It just uses more queues :-)
-- 
Krzysztof Halasa
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