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Message-Id: <20090209.002940.28474373.davem@davemloft.net>
Date: Mon, 09 Feb 2009 00:29:40 -0800 (PST)
From: David Miller <davem@...emloft.net>
To: risto.suominen@...il.com
Cc: netdev@...r.kernel.org
Subject: Re: [PATCH 002/002] de2104x: support for systems lacking cache
coherence
From: Risto Suominen <risto.suominen@...il.com>
Date: Mon, 9 Feb 2009 10:22:15 +0200
> Sounds good, but does not seem to help. My theory is that when the cpu
> is writing to one descriptor, it accidentally overwrites another
> descriptor, that has already been written to by the device, as there
> is only a single dirty bit, that makes the whole cacheline to be
> flushed.
You tested with 2.6.18 but you want me to apply this to current
kernels, that won't work.
Therefore you'll need to verify that the problem still exists with
current kernels before I'll consider this seriously.
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