netdev - Re: [PATCH 002/002] de2104x: support for systems lacking cache coherence

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Message-ID: <m3ab8v3vzp.fsf@intrepid.localdomain>
Date:	Tue, 10 Feb 2009 02:45:46 +0100
From:	Krzysztof Halasa <khc@...waw.pl>
To:	David Miller <davem@...emloft.net>
Cc:	risto.suominen@...il.com, netdev@...r.kernel.org
Subject: Re: [PATCH 002/002] de2104x: support for systems lacking cache coherence

David Miller <davem@...emloft.net> writes:

> The issue are descriptors that are _written_ by both the cpu
> and the device.  That is the problematic case here.

Do you mean both CPU and 21040 write to the same descriptor at (nearly)
the same time? Is it TX, RX or both?

I wonder, how would the patch help it?

The patch seems to align the descriptors on cache line boundary. That
IMHO means the corruption is caused by the 21040 writing to e.g. desc
#0, CPU writing to desc #1, which causes the cache line write bringing
the old desc #0 back.

Is it possible to use uncached memory for coherent allocations (with no
write side effects) on this machine?
-- 
Krzysztof Halasa
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