netdev - Re: [PATCH 3/3] dsa: add switch chip cascading support

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Message-Id: <1237583778.3217.4.camel@achroite>
Date:	Fri, 20 Mar 2009 21:16:18 +0000
From:	Ben Hutchings <bhutchings@...arflare.com>
To:	Lennert Buytenhek <buytenh@...tstofly.org>
Cc:	David Miller <davem@...emloft.net>, netdev@...r.kernel.org,
	Gary Thomas <gary@...assoc.com>,
	Jesper Dangaard Brouer <hawk@...u.dk>
Subject: Re: [PATCH 3/3] dsa: add switch chip cascading support

On Fri, 2009-03-20 at 20:52 +0100, Lennert Buytenhek wrote:
[...]
> For the example topology above, the dsa platform data would look
> something like this:
> 
> 	static struct dsa_chip_data sw[2] = {
> 		{
> 			.mii_bus	= &foo,
> 			.sw_addr	= 1,
> 			.port_names[0]	= "p1",
> 			.port_names[1]	= "p2",
> 			.port_names[2]	= "p3",
> 			.port_names[3]	= "p4",
> 			.port_names[4]	= "p5",
> 			.port_names[5]	= "p6",
> 			.port_names[6]	= "p7",
> 			.port_names[7]	= "p8",
> 			.port_names[9]	= "dsa",
> 			.port_names[10]	= "cpu",
> 			.rtable		= (s8 []){ -1, 9, },
[...]

Is there supposed to be a gap in the numbering here?  The diagram above
seemed to number the ports 1-10 but I'm guessing the internal numbering
of those would be 0-9.

Ben.

-- 
Ben Hutchings, Senior Software Engineer, Solarflare Communications
Not speaking for my employer; that's the marketing department's job.
They asked us to note that Solarflare product names are trademarked.

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