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Message-ID: <20090428061225.GA1591@gondor.apana.org.au>
Date:	Tue, 28 Apr 2009 14:12:25 +0800
From:	Herbert Xu <herbert@...dor.apana.org.au>
To:	Andrew Gallatin <gallatin@...i.com>
Cc:	David Miller <davem@...emloft.net>, brice@...i.com,
	sgruszka@...hat.com, netdev@...r.kernel.org
Subject: Re: [PATCH] myr10ge: again fix lro_gen_skb() alignment

On Mon, Apr 27, 2009 at 04:05:01PM +0800, Herbert Xu wrote:
> On Fri, Apr 24, 2009 at 12:16:08PM -0400, Andrew Gallatin wrote:
> >
> > These results are indeed quite close, so the performance problem seems
> > isolated to AMD CPUS, and perhaps due to the smaller caches.
> > Do you have any AMD you can use as a receiver?
> 
> I now have an AMD with 512K cache to test this.  Unfortunately
> I'd just locked it up before I got a chance to do any serious
> testing.  So it might take a while.

OK that's been fixed up.  Indeed the AMD can't do wire speed.
But still the performance seems comparable.  Both of them sit
between 6600Mb/s and 7100Mb/s.  The sender is running at about
66% idle in either case.

Cheers,
-- 
Visit Openswan at http://www.openswan.org/
Email: Herbert Xu ~{PmV>HI~} <herbert@...dor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
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