netdev - Re: [PATCH net-next-2.6] pcnet32: Remove pointless memory barriers

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Message-id: <1241050188.18295.13.camel@localhost.localdomain>
Date:	Wed, 29 Apr 2009 17:09:48 -0700
From:	Don Fry <pcnet32@...izon.net>
To:	John Dykstra <john.dykstra1@...il.com>
Cc:	netdev <netdev@...r.kernel.org>, romieu@...zoreil.com,
	David Miller <davem@...emloft.net>
Subject: Re: [PATCH net-next-2.6] pcnet32: Remove pointless memory barriers

After going back to my original NAPI changes, email exchanges today with
Francois and John, and looking through all the architecture
implementation of mmiowb and locking; I agree that this mmiowb is
unnecessary since a lock is always released which has all the memory
barriers needed.  I no longer have access to all the equipment I had
available at IBM, but it was tested a extensively on Intel and Power
platforms without the mmiowb.

Acked-by:  Don Fry <pcnet32@...izon.net>

-----Original Message-----
From: John Dykstra <john.dykstra1@...il.com>
To: netdev <netdev@...r.kernel.org>, Don Fry <pcnet32@...izon.net>
Subject: [PATCH net-next-2.6] pcnet32: Remove pointless memory barriers
Date: Tue, 28 Apr 2009 19:07:39 +0000

These two memory barriers in performance-critical paths are not needed
on x86.  Even if some other architecture does buffer PCI I/O space
writes, the existing memory-mapped I/O barriers are unlikely to be what
is needed.

Signed-off-by: John Dykstra <john.dykstra1@...il.com>
---
 drivers/net/pcnet32.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/pcnet32.c b/drivers/net/pcnet32.c
index e5e8c59..1c35e1d 100644
--- a/drivers/net/pcnet32.c
+++ b/drivers/net/pcnet32.c
@@ -1405,7 +1405,7 @@ static int pcnet32_poll(struct napi_struct *napi, int budget)
 
 		/* Set interrupt enable. */
 		lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
-		mmiowb();
+
 		spin_unlock_irqrestore(&lp->lock, flags);
 	}
 	return work_done;
@@ -2597,7 +2597,7 @@ pcnet32_interrupt(int irq, void *dev_id)
 			val = lp->a.read_csr(ioaddr, CSR3);
 			val |= 0x5f00;
 			lp->a.write_csr(ioaddr, CSR3, val);
-			mmiowb();
+
 			__napi_schedule(&lp->napi);
 			break;
 		}

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