| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Sun, 7 Jun 2009 16:58:28 -0700 From: Ron Mercer <ron.mercer@...gic.com> To: davem@...emloft.net Cc: netdev@...r.kernel.org, ron.mercer@...gic.com Subject: [net-2.6 PATCH 4/5] qlge: Fix timeout on indexed register wait. There are 8 banks of 'sub-registers' each of which are accessed through address/data register pair. An example would be reading flash or the xgmac. Accessing these require the driver to wait for a ready bit before writing the address and then accessing the data. This patch increases the timeout to 100us to prevent timeouts that have been seen on some platforms. These register are accessed in process context only. Signed-off-by: Ron Mercer <ron.mercer@...gic.com> --- drivers/net/qlge/qlge.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/net/qlge/qlge.h b/drivers/net/qlge/qlge.h index fcb159e..e186071 100644 --- a/drivers/net/qlge/qlge.h +++ b/drivers/net/qlge/qlge.h @@ -50,7 +50,7 @@ #define MAX_INTER_FRAME_WAIT 10 /* 10 usec max interframe-wait for coalescing */ #define DFLT_INTER_FRAME_WAIT (MAX_INTER_FRAME_WAIT/2) #define UDELAY_COUNT 3 -#define UDELAY_DELAY 10 +#define UDELAY_DELAY 100 #define TX_DESC_PER_IOCB 8 -- 1.6.0.2 -- To unsubscribe from this list: send the line "unsubscribe netdev" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Powered by blists - more mailing lists