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Message-ID: <20090616163856.GA17318@gondor.apana.org.au>
Date: Wed, 17 Jun 2009 02:38:56 +1000
From: Herbert Xu <herbert@...dor.apana.org.au>
To: Benjamin LaHaise <ben.lahaise@...erion.com>
Cc: David Miller <davem@...emloft.net>, netdev@...r.kernel.org
Subject: Re: [0/14] GRO: Lots of microoptimisations
On Tue, Jun 16, 2009 at 12:35:47PM -0400, Benjamin LaHaise wrote:
> On Fri, Jun 12, 2009 at 04:48:33PM -0700, David Miller wrote:
> > I find a 500Mbps difference, due to just one single cache miss on
> > every packet, simply astounding and unbelievable. But hey, it is
> > what you are seeing, so something has to account for it. :)
>
> The cache miss only accounts for ~50Mbpsi, it'd be nice if there was an
> easy way to get the whole 500Mbps back. The rest seems to be in the
> general overhead of the GRO code vs the normal NAPI rx path. The P4
> Xeon is substantially worse at string operations than the Core 2 / Core i7
> based Xeons, so I'm hoping to test and see if they do any better with the
> GRO code when I get access to a new machine soon.
I'm hoping to get onto this tomorrow. I think there's definitely
something broken because there's no way GRO should be slower than
GRO off. Slightly slower than LRO perhaps but surely not worse than
not merging at all :)
Cheers,
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Email: Herbert Xu ~{PmV>HI~} <herbert@...dor.apana.org.au>
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