netdev - RE: [PATCH 29/29] ioat2, 3: cacheline align software descriptor allocations

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Message-ID: <129600E5E5FB004392DDC3FB599660D7B554819B@irsmsx504.ger.corp.intel.com>
Date:	Mon, 14 Sep 2009 16:02:37 +0100
From:	"Sosnowski, Maciej" <maciej.sosnowski@...el.com>
To:	"Williams, Dan J" <dan.j.williams@...el.com>
CC:	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-raid@...r.kernel.org" <linux-raid@...r.kernel.org>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>
Subject: RE: [PATCH 29/29] ioat2,	3: cacheline align software descriptor
 allocations

Williams, Dan J wrote:
> All the necessary fields for handling an ioat2,3 ring entry can fit into
> one cacheline.  Move ->len prior to ->txd in struct ioat_ring_ent, and
> move allocation of these entries to a hw-cache-aligned kmem cache to
> reduce the number of cachelines dirtied for descriptor management.
> 
> Signed-off-by: Dan Williams <dan.j.williams@...el.com>
> ---

Signed-off-by: Maciej Sosnowski <maciej.sosnowski@...el.com>
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