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Message-Id: <pvmiqcfbpep.fsf@chavey.mtv.corp.google.com>
Date:	Wed, 09 Dec 2009 17:15:10 -0800
From:	chavey@...gle.com
To:	jeffrey.t.kirsher@...el.com
CC:	netdev@...r.kernel.org, gospo@...hat.com, gregory.v.rose@...el.com,
	peter.p.waskiewicz.jr@...el.com
Subject: Re: [RFC PATCH 05/12] ixgbe: Add SR-IOV features to main module

From: Greg Rose <gregory.v.rose@...el.com>

Adds SR-IOV features supported by the 82599 controller to the main driver
module.  If the CONFIG_PCI_IOV kernel option is selected then the SR-IOV
features are enabled.  Use the max_vfs module option to allocate up to 63
virtual functions per physical port.

Signed-off-by: Greg Rose <gregory.v.rose@...el.com>
Acked-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@...el.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@...el.com>
---

+static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
+{
+       struct ixgbe_hw *hw = &adapter->hw;
+       u32 gcr;
+       u32 gpie;
+       u32 vmdctl;
+
+#ifdef CONFIG_PCI_IOV
+       /* disable iov and allow time for transactions to clear */
+       pci_disable_sriov(adapter->pdev);
+#endif
+       msleep(500);

what is the sleep used for ?
if this is to wait for pci_disable then add it
in the #ifdef above.
i s there a registerthat can be checked to ensure that
the device is in the expected state ? (similar to line 311 of
the orginal patch)


@@ -2269,6 +2376,20 @@ static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
       }
       IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);

+       if (adapter->num_vfs) {
+               u32 reg;
+
+               /* Map PF MAC address in RAR Entry 0 to first pool
+                * following VFs */
+               hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
+
+               /* Set up VF register offsets for selected VT Mode, i.e.
+                * 64 VFs for SR-IOV */
+               reg = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
+               reg |= 0x80000003;

what is the significance of the 0x80000003 ?

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