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Date:	Tue, 09 Feb 2010 12:13:56 -0800 (PST)
From:	David Miller <davem@...emloft.net>
To:	agust@...x.de
Cc:	wg@...ndegger.com, netdev@...r.kernel.org, dzu@...x.de, wd@...x.de,
	jcrigby@...il.com, kosmo@...ihalf.com, linuxppc-dev@...abs.org,
	grant.likely@...retlab.ca
Subject: Re: [net-next-2.6 PATCH 2/3] fs_enet: Add support for MPC512x to
 fs_enet driver

From: Anatolij Gustschin <agust@...x.de>
Date: Tue, 9 Feb 2010 15:23:17 +0100

> In my understanding, in the ESP scsi driver the set of defines for
> the register offsets is common for all chip drivers. The chip driver
> methods for register access translate the offsets because the
> registers on some chips are at different intervals (4-byte, 1-byte,
> 16-byte for mac_esp.c). But the register order is the same for
> different chips.
> 
> In our case non only the register order is not the same for 8xx
> FEC and 5121 FEC, but there are also other differences, different
> reserved areas between several registers, some registers are
> available only on 8xx and some only on 5121.

That only means you would need to use a table based register address
translation scheme, rather than a simple calculation.  Something
like:

static unsigned int chip_xxx_table[] =
{
	[GENERIC_REG_FOO]	 = CHIP_XXX_FOO,
	...
};

static u32 chip_xxx_read_reg(struct chip *p, unsigned int reg)
{
	unsigned int reg_off = chip_xxx_table[reg];

	return readl(p->regs + reg_off);
}

And this table can have special tokens in entries for
registers which do not exist on a chip, so you can trap
attempted access to them in these read/write handlers.

Please stop looking for excuses to fork this driver, a
unified driver I think can be done cleanly.
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