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Date:	Sat, 27 Mar 2010 12:40:59 +0100
From:	François Romieu <romieu@...zoreil.com>
To:	Timo Teräs <timo.teras@....fi>
Cc:	Ivan Vecera <ivecera@...hat.com>, netdev@...r.kernel.org
Subject: Re: r8169 mac reading/writing broken

Timo Teräs <timo.teras@....fi> :
[...]
> I did some more testing, and added debugging info to rtl_rar_set(). It would
> appear that even if I write any mac address (with ifconfig) and reread the
> MAC0..MAC5 register, the first four bytes get zeroed. So it would sounds like
> the hardware is faulty, or that the rtl_rar_set function is buggy.
> 
> Any suggestions to fix this ?

Try something like the patch below and please send a complete lspci -vvv.

I wonder what the bus controler looks like.

diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c
index 9d3ebf3..5db357a 100644
--- a/drivers/net/r8169.c
+++ b/drivers/net/r8169.c
@@ -2814,6 +2814,7 @@ static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
 	void __iomem *ioaddr = tp->mmio_addr;
 	u32 high;
 	u32 low;
+	int i;
 
 	low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
 	high = addr[4] | (addr[5] << 8);
@@ -2822,7 +2823,17 @@ static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
 
 	RTL_W8(Cfg9346, Cfg9346_Unlock);
 	RTL_W32(MAC0, low);
-	RTL_W32(MAC4, high);
+	for (i = 0; i < 16; i++) {
+		u32 read;
+
+		RTL_W32(MAC4, high);
+		read = RTL_R32(MAC4);
+		if (read != high) {
+			printk(KERN_ERR PFX
+			       "failure %02d: read = 0x%08x, write = 0x%08x\n",
+				i, read, high);
+		}
+	}
 	RTL_W8(Cfg9346, Cfg9346_Lock);
 
 	spin_unlock_irq(&tp->lock);
--
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