netdev - Re: [PATCH net-next-2.6] net: Increase NET_SKB

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Date:	Fri, 07 May 2010 09:53:48 +0200
From:	Michal Simek <monstr@...str.eu>
To:	Eric Dumazet <eric.dumazet@...il.com>
CC:	David Miller <davem@...emloft.net>, netdev@...r.kernel.org,
	hadi@...erus.ca, therbert@...gle.com,
	microblaze-uclinux@...e.uq.edu.au
Subject: Re: [PATCH net-next-2.6] net: Increase NET_SKB_PAD to 64 bytes

Eric Dumazet wrote:
> Le jeudi 06 mai 2010 à 22:02 -0700, David Miller a écrit :
> 
>> Seeing this made me go check who was overriding NET_IP_ALIGN or
>> NET_SKB_PAD.
>>
>> The powerpc bits are legitimate, but the microblaze case is complete
>> bogosity.  It defines NET_IP_ALIGN to the default (2) and sets
>> NET_SKB_PAD to L1_CACHE_BYTES which on microblaze is 4 and
>> significantly smaller than the default.
>>
>> So I'm going to delete them in net-next-2.6 like so:
>>
>> --------------------
>> microblaze: Kill NET_SKB_PAD and NET_IP_ALIGN overrides.
>>
>> NET_IP_ALIGN defaults to 2, no need to override.
>>
>> NET_SKB_PAD is now 64, which is much larger than microblaze's
>> L1_CACHE_SIZE so no need to override that either.
>>
>> Signed-off-by: David S. Miller <davem@...emloft.net>
>> ---
>>  arch/microblaze/include/asm/system.h |   10 ----------
>>  1 files changed, 0 insertions(+), 10 deletions(-)
>>
>> diff --git a/arch/microblaze/include/asm/system.h b/arch/microblaze/include/asm/system.h
>> index 48c4f03..b1e2f07 100644
>> --- a/arch/microblaze/include/asm/system.h
>> +++ b/arch/microblaze/include/asm/system.h
>> @@ -97,14 +97,4 @@ extern struct dentry *of_debugfs_root;
>>  
>>  #define arch_align_stack(x) (x)
>>  
>> -/*
>> - * MicroBlaze doesn't handle unaligned accesses in hardware.
>> - *
>> - * Based on this we force the IP header alignment in network drivers.
>> - * We also modify NET_SKB_PAD to be a cacheline in size, thus maintaining
>> - * cacheline alignment of buffers.
>> - */
>> -#define NET_IP_ALIGN	2
>> -#define NET_SKB_PAD	L1_CACHE_BYTES
>> -
>>  #endif /* _ASM_MICROBLAZE_SYSTEM_H */
> 
> Yes, this seems strange it actually worked if L1_CACHE_BYTES = 4

This was fault which I fixed. I sent pull request to Linus yesterday 
with contains patch which fix it.
L1_CACHE_BYTES was setup to 32 which is maximum cache line length on 
Microblaze.

I will add this Microblaze patch to my repo for testing and anyway 
should go through my repo.

Thanks,
Michal

-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian
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