netdev - Re: [PATCH 1/3] gianfar: Implement workaround for eTSEC74 erratum

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <20100630.113706.133400770.davem@davemloft.net>
Date:	Wed, 30 Jun 2010 11:37:06 -0700 (PDT)
From:	David Miller <davem@...emloft.net>
To:	avorontsov@...sta.com
Cc:	manfred.rudigier@...cron.at, Sandeep.Kumar@...escale.com,
	afleming@...escale.com, netdev@...r.kernel.org,
	linuxppc-dev@...abs.org
Subject: Re: [PATCH 1/3] gianfar: Implement workaround for eTSEC74 erratum

From: Anton Vorontsov <avorontsov@...sta.com>
Date: Wed, 30 Jun 2010 20:38:04 +0400

> On Tue, Jun 29, 2010 at 03:16:26PM -0700, David Miller wrote:
>> 
>> I really don't see any value at all to this config option,
>> the errata fixup code should be there all the time.
> 
> Well, at least for eTSEC76 erratum (patch 2/3) we have to touch
> fast path (i.e. start_xmit), so I just wanted to make zero
> overhead for controllers that don't need any fixups.
> 
> Not that there's much of the overhead in a single additional
> 'if' condition, no. ;-)

The register accesses will dominate the costs with this chip.

The only case where a if() test is going to potentially create
some practical performance impact is if the TX is performed
purely using changes to a shared memory data structure and
absolutely no MMIO register reads or writes.
--
To unsubscribe from this list: send the line "unsubscribe netdev" in
the body of a message to majordomo@...r.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html