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Message-ID: <1280784368-4226-1-git-send-email-mcarlson@broadcom.com>
Date: Mon, 2 Aug 2010 14:25:55 -0700
From: "Matt Carlson" <mcarlson@...adcom.com>
To: davem@...emloft.net
cc: netdev@...r.kernel.org, andy@...yhouse.net, mcarlson@...adcom.com
Subject: [PATCH net-next 01/14] tg3: Add 5784 ASIC rev to earlier PCIe
MPS fix
tg3 commit e7126997342560533317d8467e8516119ebcbd21 entitled
"tg3: Preserve PCIe MPS setting for new devs" attempted to ensure the
PCIe link negotiated Maximum Payload Size (MPS) setting was 128 bytes
for all devices that didn't support higher speeds. The 5784 device was
mistakenly added to this list when it shouldn't have. This patch
removes the 5784 ASIC rev devices from that list.
Reviewed-by: Benjamin Li <benli@...adcom.com>
Reviewed-by: Michael Chan <mchan@...adcom.com>
Signed-off-by: Matt Carlson <mcarlson@...adcom.com>
---
drivers/net/tg3.c | 3 +--
1 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index b26a577..98ca0d2 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -7002,8 +7002,7 @@ static int tg3_chip_reset(struct tg3 *tp)
* Older PCIe devices only support the 128 byte
* MPS setting. Enforce the restriction.
*/
- if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
- (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
+ if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
pci_write_config_word(tp->pdev,
tp->pcie_cap + PCI_EXP_DEVCTL,
--
1.7.1
--
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