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Message-Id: <20100917.161325.179286731.davem@davemloft.net>
Date:	Fri, 17 Sep 2010 16:13:25 -0700 (PDT)
From:	David Miller <davem@...emloft.net>
To:	peppe.cavallaro@...com
Cc:	netdev@...r.kernel.org, js@...21.net, deepak.sikri@...com
Subject: Re: [net-next 2/4] stmmac: consolidate and tidy-up the COE support

From: Giuseppe CAVALLARO <peppe.cavallaro@...com>
Date: Fri, 17 Sep 2010 15:23:40 +0200

> The first version of the driver had hard-coded the logic
> for handling the checksum offloading.
> This was designed according to the chips included in
> the STM platforms where:
> o MAC10/100 supports no COE at all.
> o GMAC fully supports RX/TX COE.
> 
> This is not good for other chip configurations where,
> for example, the mac10/100 supports the tx csum in HW
> or when the GMAC has no IPC.
> 
> Thanks to Johannes Stezenbach; he provided me a first
> draft of this patch that only reviewed the IPC for the
> GMAC devices.
> 
> This patch also helps on SPEAr platforms where the
> MAC10/100 can perform the TX csum in HW.
> Thanks to Deepak SIKRI for his support on this.
> 
> In the end, GMAC devices for STM platforms have
> a bugged Jumbo frame support that needs to have
> the Tx COE disabled for oversized frames (due to
> limited buffer sizes). This information is also
> passed through the driver's platform structure.
> 
> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@...com>
> Signed-off-by: Johannes Stezenbach <js@...21.net>
> Signed-off-by: Deepak SIKRI <deepak.sikri@...com>

Applied.
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