>From b84eaf51494f6e46609f2fb0c8961bf99c6ea9ec Mon Sep 17 00:00:00 2001 From: Francois Romieu Date: Fri, 1 Oct 2010 00:28:16 +0200 Subject: [PATCH 3/9] r8169: use device dependent methods to access the MII registers. Current mdio_{read/write} can not reach enough information to work correctly with newer chipsets. Signed-off-by: Francois Romieu Cc: Hayes --- drivers/net/r8169.c | 309 ++++++++++++++++++++++++++------------------------- 1 files changed, 160 insertions(+), 149 deletions(-) diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c index 6e80df6..790d34a 100644 --- a/drivers/net/r8169.c +++ b/drivers/net/r8169.c @@ -498,9 +498,9 @@ struct rtl8169_private { #endif int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex); int (*get_settings)(struct net_device *, struct ethtool_cmd *); - void (*phy_reset_enable)(void __iomem *); + void (*phy_reset_enable)(struct rtl8169_private *tp); void (*hw_start)(struct net_device *); - unsigned int (*phy_reset_pending)(void __iomem *); + unsigned int (*phy_reset_pending)(struct rtl8169_private *tp); unsigned int (*link_ok)(void __iomem *); int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd); int pcie_cap; @@ -541,7 +541,7 @@ static int rtl8169_poll(struct napi_struct *napi, int budget); static const unsigned int rtl8169_rx_config = (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); -static void mdio_write(void __iomem *ioaddr, int reg_addr, int value) +static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value) { int i; @@ -563,7 +563,7 @@ static void mdio_write(void __iomem *ioaddr, int reg_addr, int value) udelay(20); } -static int mdio_read(void __iomem *ioaddr, int reg_addr) +static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr) { int i, value = -1; @@ -589,34 +589,42 @@ static int mdio_read(void __iomem *ioaddr, int reg_addr) return value; } -static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value) +static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val) { - mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value); + r8169_mdio_write(tp->mmio_addr, location, val); } -static void mdio_plus_minus(void __iomem *ioaddr, int reg_addr, int p, int m) +static int rtl_readphy(struct rtl8169_private *tp, int location) +{ + return r8169_mdio_read(tp->mmio_addr, location); +} + +static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value) +{ + rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value); +} + +static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m) { int val; - val = mdio_read(ioaddr, reg_addr); - mdio_write(ioaddr, reg_addr, (val | p) & ~m); + val = rtl_readphy(tp, reg_addr); + rtl_writephy(tp, reg_addr, (val | p) & ~m); } static void rtl_mdio_write(struct net_device *dev, int phy_id, int location, int val) { struct rtl8169_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; - mdio_write(ioaddr, location, val); + rtl_writephy(tp, location, val); } static int rtl_mdio_read(struct net_device *dev, int phy_id, int location) { struct rtl8169_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; - return mdio_read(ioaddr, location); + return rtl_readphy(tp, location); } static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value) @@ -717,14 +725,16 @@ static void rtl8169_asic_down(void __iomem *ioaddr) RTL_R16(CPlusCmd); } -static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr) +static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp) { + void __iomem *ioaddr = tp->mmio_addr; + return RTL_R32(TBICSR) & TBIReset; } -static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr) +static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp) { - return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET; + return rtl_readphy(tp, MII_BMCR) & BMCR_RESET; } static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr) @@ -737,17 +747,19 @@ static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr) return RTL_R8(PHYstatus) & LinkStatus; } -static void rtl8169_tbi_reset_enable(void __iomem *ioaddr) +static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp) { + void __iomem *ioaddr = tp->mmio_addr; + RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset); } -static void rtl8169_xmii_reset_enable(void __iomem *ioaddr) +static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp) { unsigned int val; - val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET; - mdio_write(ioaddr, MII_BMCR, val & 0xffff); + val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET; + rtl_writephy(tp, MII_BMCR, val & 0xffff); } static void rtl8169_check_link_status(struct net_device *dev, @@ -901,18 +913,17 @@ static int rtl8169_set_speed_xmii(struct net_device *dev, u8 autoneg, u16 speed, u8 duplex) { struct rtl8169_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; int giga_ctrl, bmcr; if (autoneg == AUTONEG_ENABLE) { int auto_nego; - auto_nego = mdio_read(ioaddr, MII_ADVERTISE); + auto_nego = rtl_readphy(tp, MII_ADVERTISE); auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL | ADVERTISE_100HALF | ADVERTISE_100FULL); auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; - giga_ctrl = mdio_read(ioaddr, MII_CTRL1000); + giga_ctrl = rtl_readphy(tp, MII_CTRL1000); giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); /* The 8100e/8101e/8102e do Fast Ethernet only. */ @@ -940,12 +951,12 @@ static int rtl8169_set_speed_xmii(struct net_device *dev, * Vendor specific (0x1f) and reserved (0x0e) MII * registers. */ - mdio_write(ioaddr, 0x1f, 0x0000); - mdio_write(ioaddr, 0x0e, 0x0000); + rtl_writephy(tp, 0x1f, 0x0000); + rtl_writephy(tp, 0x0e, 0x0000); } - mdio_write(ioaddr, MII_ADVERTISE, auto_nego); - mdio_write(ioaddr, MII_CTRL1000, giga_ctrl); + rtl_writephy(tp, MII_ADVERTISE, auto_nego); + rtl_writephy(tp, MII_CTRL1000, giga_ctrl); } else { giga_ctrl = 0; @@ -959,21 +970,21 @@ static int rtl8169_set_speed_xmii(struct net_device *dev, if (duplex == DUPLEX_FULL) bmcr |= BMCR_FULLDPLX; - mdio_write(ioaddr, 0x1f, 0x0000); + rtl_writephy(tp, 0x1f, 0x0000); } tp->phy_1000_ctrl_reg = giga_ctrl; - mdio_write(ioaddr, MII_BMCR, bmcr); + rtl_writephy(tp, MII_BMCR, bmcr); if ((tp->mac_version == RTL_GIGA_MAC_VER_02) || (tp->mac_version == RTL_GIGA_MAC_VER_03)) { if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) { - mdio_write(ioaddr, 0x17, 0x2138); - mdio_write(ioaddr, 0x0e, 0x0260); + rtl_writephy(tp, 0x17, 0x2138); + rtl_writephy(tp, 0x0e, 0x0260); } else { - mdio_write(ioaddr, 0x17, 0x2108); - mdio_write(ioaddr, 0x0e, 0x0000); + rtl_writephy(tp, 0x17, 0x2108); + rtl_writephy(tp, 0x0e, 0x0000); } } @@ -1381,15 +1392,16 @@ struct phy_reg { u16 val; }; -static void rtl_phy_write(void __iomem *ioaddr, const struct phy_reg *regs, int len) +static void rtl_writephy_batch(struct rtl8169_private *tp, + const struct phy_reg *regs, int len) { while (len-- > 0) { - mdio_write(ioaddr, regs->reg, regs->val); + rtl_writephy(tp, regs->reg, regs->val); regs++; } } -static void rtl8169s_hw_phy_config(void __iomem *ioaddr) +static void rtl8169s_hw_phy_config(struct rtl8169_private *tp) { static const struct phy_reg phy_reg_init[] = { { 0x1f, 0x0001 }, @@ -1453,10 +1465,10 @@ static void rtl8169s_hw_phy_config(void __iomem *ioaddr) { 0x00, 0x9200 } }; - rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); + rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); } -static void rtl8169sb_hw_phy_config(void __iomem *ioaddr) +static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp) { static const struct phy_reg phy_reg_init[] = { { 0x1f, 0x0002 }, @@ -1464,11 +1476,10 @@ static void rtl8169sb_hw_phy_config(void __iomem *ioaddr) { 0x1f, 0x0000 } }; - rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); + rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); } -static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp, - void __iomem *ioaddr) +static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp) { struct pci_dev *pdev = tp->pci_dev; u16 vendor_id, device_id; @@ -1479,13 +1490,12 @@ static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp, if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000)) return; - mdio_write(ioaddr, 0x1f, 0x0001); - mdio_write(ioaddr, 0x10, 0xf01b); - mdio_write(ioaddr, 0x1f, 0x0000); + rtl_writephy(tp, 0x1f, 0x0001); + rtl_writephy(tp, 0x10, 0xf01b); + rtl_writephy(tp, 0x1f, 0x0000); } -static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp, - void __iomem *ioaddr) +static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp) { static const struct phy_reg phy_reg_init[] = { { 0x1f, 0x0001 }, @@ -1527,12 +1537,12 @@ static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp, { 0x1f, 0x0000 } }; - rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); + rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); - rtl8169scd_hw_phy_config_quirk(tp, ioaddr); + rtl8169scd_hw_phy_config_quirk(tp); } -static void rtl8169sce_hw_phy_config(void __iomem *ioaddr) +static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp) { static const struct phy_reg phy_reg_init[] = { { 0x1f, 0x0001 }, @@ -1582,23 +1592,23 @@ static void rtl8169sce_hw_phy_config(void __iomem *ioaddr) { 0x1f, 0x0000 } }; - rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); + rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); } -static void rtl8168bb_hw_phy_config(void __iomem *ioaddr) +static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp) { static const struct phy_reg phy_reg_init[] = { { 0x10, 0xf41b }, { 0x1f, 0x0000 } }; - mdio_write(ioaddr, 0x1f, 0x0001); - mdio_patch(ioaddr, 0x16, 1 << 0); + rtl_writephy(tp, 0x1f, 0x0001); + rtl_patchphy(tp, 0x16, 1 << 0); - rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); + rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); } -static void rtl8168bef_hw_phy_config(void __iomem *ioaddr) +static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp) { static const struct phy_reg phy_reg_init[] = { { 0x1f, 0x0001 }, @@ -1606,10 +1616,10 @@ static void rtl8168bef_hw_phy_config(void __iomem *ioaddr) { 0x1f, 0x0000 } }; - rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); + rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); } -static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr) +static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp) { static const struct phy_reg phy_reg_init[] = { { 0x1f, 0x0000 }, @@ -1619,10 +1629,10 @@ static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr) { 0x1f, 0x0000 } }; - rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); + rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); } -static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr) +static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp) { static const struct phy_reg phy_reg_init[] = { { 0x1f, 0x0001 }, @@ -1630,14 +1640,14 @@ static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr) { 0x1f, 0x0000 } }; - mdio_write(ioaddr, 0x1f, 0x0000); - mdio_patch(ioaddr, 0x14, 1 << 5); - mdio_patch(ioaddr, 0x0d, 1 << 5); + rtl_writephy(tp, 0x1f, 0x0000); + rtl_patchphy(tp, 0x14, 1 << 5); + rtl_patchphy(tp, 0x0d, 1 << 5); - rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); + rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); } -static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr) +static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp) { static const struct phy_reg phy_reg_init[] = { { 0x1f, 0x0001 }, @@ -1659,14 +1669,14 @@ static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr) { 0x09, 0x0000 } }; - rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); + rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); - mdio_patch(ioaddr, 0x14, 1 << 5); - mdio_patch(ioaddr, 0x0d, 1 << 5); - mdio_write(ioaddr, 0x1f, 0x0000); + rtl_patchphy(tp, 0x14, 1 << 5); + rtl_patchphy(tp, 0x0d, 1 << 5); + rtl_writephy(tp, 0x1f, 0x0000); } -static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr) +static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp) { static const struct phy_reg phy_reg_init[] = { { 0x1f, 0x0001 }, @@ -1686,15 +1696,15 @@ static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr) { 0x1f, 0x0000 } }; - rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); + rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); - mdio_patch(ioaddr, 0x16, 1 << 0); - mdio_patch(ioaddr, 0x14, 1 << 5); - mdio_patch(ioaddr, 0x0d, 1 << 5); - mdio_write(ioaddr, 0x1f, 0x0000); + rtl_patchphy(tp, 0x16, 1 << 0); + rtl_patchphy(tp, 0x14, 1 << 5); + rtl_patchphy(tp, 0x0d, 1 << 5); + rtl_writephy(tp, 0x1f, 0x0000); } -static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr) +static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp) { static const struct phy_reg phy_reg_init[] = { { 0x1f, 0x0001 }, @@ -1708,21 +1718,22 @@ static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr) { 0x1f, 0x0000 } }; - rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); + rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); - mdio_patch(ioaddr, 0x16, 1 << 0); - mdio_patch(ioaddr, 0x14, 1 << 5); - mdio_patch(ioaddr, 0x0d, 1 << 5); - mdio_write(ioaddr, 0x1f, 0x0000); + rtl_patchphy(tp, 0x16, 1 << 0); + rtl_patchphy(tp, 0x14, 1 << 5); + rtl_patchphy(tp, 0x0d, 1 << 5); + rtl_writephy(tp, 0x1f, 0x0000); } -static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr) +static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp) { - rtl8168c_3_hw_phy_config(ioaddr); + rtl8168c_3_hw_phy_config(tp); } -static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr) +static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp) { + void __iomem *ioaddr = tp->mmio_addr; static const struct phy_reg phy_reg_init_0[] = { /* Channel Estimation */ { 0x1f, 0x0001 }, @@ -2140,15 +2151,15 @@ static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr) { 0x1f, 0x0000 } }; - rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); + rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); /* * Rx Error Issue * Fine Tune Switching regulator parameter */ - mdio_write(ioaddr, 0x1f, 0x0002); - mdio_plus_minus(ioaddr, 0x0b, 0x0010, 0x00ef); - mdio_plus_minus(ioaddr, 0x0c, 0xa200, 0x5d00); + rtl_writephy(tp, 0x1f, 0x0002); + rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef); + rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00); if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) { static const struct phy_reg phy_reg_init[] = { @@ -2161,9 +2172,9 @@ static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr) }; int val; - rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); + rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); - val = mdio_read(ioaddr, 0x0d); + val = rtl_readphy(tp, 0x0d); if ((val & 0x00ff) != 0x006c) { static const u32 set[] = { @@ -2172,11 +2183,11 @@ static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr) }; int i; - mdio_write(ioaddr, 0x1f, 0x0002); + rtl_writephy(tp, 0x1f, 0x0002); val &= 0xff00; for (i = 0; i < ARRAY_SIZE(set); i++) - mdio_write(ioaddr, 0x0d, val | set[i]); + rtl_writephy(tp, 0x0d, val | set[i]); } } else { static const struct phy_reg phy_reg_init[] = { @@ -2187,28 +2198,28 @@ static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr) { 0x06, 0x6662 } }; - rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); + rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); } /* RSET couple improve */ - mdio_write(ioaddr, 0x1f, 0x0002); - mdio_patch(ioaddr, 0x0d, 0x0300); - mdio_patch(ioaddr, 0x0f, 0x0010); + rtl_writephy(tp, 0x1f, 0x0002); + rtl_patchphy(tp, 0x0d, 0x0300); + rtl_patchphy(tp, 0x0f, 0x0010); /* Fine tune PLL performance */ - mdio_write(ioaddr, 0x1f, 0x0002); - mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600); - mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000); + rtl_writephy(tp, 0x1f, 0x0002); + rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600); + rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000); - mdio_write(ioaddr, 0x1f, 0x0005); - mdio_write(ioaddr, 0x05, 0x001b); - if (mdio_read(ioaddr, 0x06) == 0xbf00) - rtl_phy_write(ioaddr, phy_reg_init_2, ARRAY_SIZE(phy_reg_init_2)); + rtl_writephy(tp, 0x1f, 0x0005); + rtl_writephy(tp, 0x05, 0x001b); + if (rtl_readphy(tp, 0x06) == 0xbf00) + rtl_writephy_batch(tp, phy_reg_init_2, ARRAY_SIZE(phy_reg_init_2)); - mdio_write(ioaddr, 0x1f, 0x0000); + rtl_writephy(tp, 0x1f, 0x0000); } -static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr) +static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp) { static const struct phy_reg phy_reg_init_0[] = { /* Channel Estimation */ @@ -2584,8 +2595,9 @@ static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr) { 0x06, 0x00fc }, { 0x1f, 0x0000 } }; + void __iomem *ioaddr = tp->mmio_addr; - rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); + rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) { static const struct phy_reg phy_reg_init[] = { @@ -2599,9 +2611,9 @@ static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr) }; int val; - rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); + rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); - val = mdio_read(ioaddr, 0x0d); + val = rtl_readphy(tp, 0x0d); if ((val & 0x00ff) != 0x006c) { u32 set[] = { 0x0065, 0x0066, 0x0067, 0x0068, @@ -2609,11 +2621,11 @@ static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr) }; int i; - mdio_write(ioaddr, 0x1f, 0x0002); + rtl_writephy(tp, 0x1f, 0x0002); val &= 0xff00; for (i = 0; i < ARRAY_SIZE(set); i++) - mdio_write(ioaddr, 0x0d, val | set[i]); + rtl_writephy(tp, 0x0d, val | set[i]); } } else { static const struct phy_reg phy_reg_init[] = { @@ -2624,27 +2636,27 @@ static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr) { 0x06, 0x2642 } }; - rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); + rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); } /* Fine tune PLL performance */ - mdio_write(ioaddr, 0x1f, 0x0002); - mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600); - mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000); + rtl_writephy(tp, 0x1f, 0x0002); + rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600); + rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000); /* Switching regulator Slew rate */ - mdio_write(ioaddr, 0x1f, 0x0002); - mdio_patch(ioaddr, 0x0f, 0x0017); + rtl_writephy(tp, 0x1f, 0x0002); + rtl_patchphy(tp, 0x0f, 0x0017); - mdio_write(ioaddr, 0x1f, 0x0005); - mdio_write(ioaddr, 0x05, 0x001b); - if (mdio_read(ioaddr, 0x06) == 0xb300) - rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1)); + rtl_writephy(tp, 0x1f, 0x0005); + rtl_writephy(tp, 0x05, 0x001b); + if (rtl_readphy(tp, 0x06) == 0xb300) + rtl_writephy_batch(tp, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1)); - mdio_write(ioaddr, 0x1f, 0x0000); + rtl_writephy(tp, 0x1f, 0x0000); } -static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr) +static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp) { static const struct phy_reg phy_reg_init[] = { { 0x1f, 0x0002 }, @@ -2702,10 +2714,10 @@ static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr) { 0x1f, 0x0000 } }; - rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); + rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); } -static void rtl8102e_hw_phy_config(void __iomem *ioaddr) +static void rtl8102e_hw_phy_config(struct rtl8169_private *tp) { static const struct phy_reg phy_reg_init[] = { { 0x1f, 0x0003 }, @@ -2714,18 +2726,17 @@ static void rtl8102e_hw_phy_config(void __iomem *ioaddr) { 0x1f, 0x0000 } }; - mdio_write(ioaddr, 0x1f, 0x0000); - mdio_patch(ioaddr, 0x11, 1 << 12); - mdio_patch(ioaddr, 0x19, 1 << 13); - mdio_patch(ioaddr, 0x10, 1 << 15); + rtl_writephy(tp, 0x1f, 0x0000); + rtl_patchphy(tp, 0x11, 1 << 12); + rtl_patchphy(tp, 0x19, 1 << 13); + rtl_patchphy(tp, 0x10, 1 << 15); - rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); + rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); } static void rtl_hw_phy_config(struct net_device *dev) { struct rtl8169_private *tp = netdev_priv(dev); - void __iomem *ioaddr = tp->mmio_addr; rtl8169_print_mac_version(tp); @@ -2734,58 +2745,58 @@ static void rtl_hw_phy_config(struct net_device *dev) break; case RTL_GIGA_MAC_VER_02: case RTL_GIGA_MAC_VER_03: - rtl8169s_hw_phy_config(ioaddr); + rtl8169s_hw_phy_config(tp); break; case RTL_GIGA_MAC_VER_04: - rtl8169sb_hw_phy_config(ioaddr); + rtl8169sb_hw_phy_config(tp); break; case RTL_GIGA_MAC_VER_05: - rtl8169scd_hw_phy_config(tp, ioaddr); + rtl8169scd_hw_phy_config(tp); break; case RTL_GIGA_MAC_VER_06: - rtl8169sce_hw_phy_config(ioaddr); + rtl8169sce_hw_phy_config(tp); break; case RTL_GIGA_MAC_VER_07: case RTL_GIGA_MAC_VER_08: case RTL_GIGA_MAC_VER_09: - rtl8102e_hw_phy_config(ioaddr); + rtl8102e_hw_phy_config(tp); break; case RTL_GIGA_MAC_VER_11: - rtl8168bb_hw_phy_config(ioaddr); + rtl8168bb_hw_phy_config(tp); break; case RTL_GIGA_MAC_VER_12: - rtl8168bef_hw_phy_config(ioaddr); + rtl8168bef_hw_phy_config(tp); break; case RTL_GIGA_MAC_VER_17: - rtl8168bef_hw_phy_config(ioaddr); + rtl8168bef_hw_phy_config(tp); break; case RTL_GIGA_MAC_VER_18: - rtl8168cp_1_hw_phy_config(ioaddr); + rtl8168cp_1_hw_phy_config(tp); break; case RTL_GIGA_MAC_VER_19: - rtl8168c_1_hw_phy_config(ioaddr); + rtl8168c_1_hw_phy_config(tp); break; case RTL_GIGA_MAC_VER_20: - rtl8168c_2_hw_phy_config(ioaddr); + rtl8168c_2_hw_phy_config(tp); break; case RTL_GIGA_MAC_VER_21: - rtl8168c_3_hw_phy_config(ioaddr); + rtl8168c_3_hw_phy_config(tp); break; case RTL_GIGA_MAC_VER_22: - rtl8168c_4_hw_phy_config(ioaddr); + rtl8168c_4_hw_phy_config(tp); break; case RTL_GIGA_MAC_VER_23: case RTL_GIGA_MAC_VER_24: - rtl8168cp_2_hw_phy_config(ioaddr); + rtl8168cp_2_hw_phy_config(tp); break; case RTL_GIGA_MAC_VER_25: - rtl8168d_1_hw_phy_config(ioaddr); + rtl8168d_1_hw_phy_config(tp); break; case RTL_GIGA_MAC_VER_26: - rtl8168d_2_hw_phy_config(ioaddr); + rtl8168d_2_hw_phy_config(tp); break; case RTL_GIGA_MAC_VER_27: - rtl8168d_3_hw_phy_config(ioaddr); + rtl8168d_3_hw_phy_config(tp); break; default: @@ -2914,7 +2925,7 @@ static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); RTL_W8(0x82, 0x01); dprintk("Set PHY Reg 0x0bh = 0x00h\n"); - mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0 + rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0 } rtl8169_phy_reset(dev, tp); @@ -2984,11 +2995,11 @@ static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *dat return 0; case SIOCGMIIREG: - data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f); + data->val_out = rtl_readphy(tp, data->reg_num & 0x1f); return 0; case SIOCSMIIREG: - mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in); + rtl_writephy(tp, data->reg_num & 0x1f, data->val_in); return 0; } return -EOPNOTSUPP; -- 1.7.3.2