>From d777443c097b65b06f1d0e7da37db1368185db8e Mon Sep 17 00:00:00 2001 From: Francois Romieu Date: Tue, 28 Jun 2011 17:01:29 +0200 Subject: [PATCH 1/3] r8169: noise redux. - insert an empty record in rtl_chip_infos for future chipsets. NB: the array is only accessed through the RTL_GIGA_MAC_VER_xy enum. - ready-to-use ERIAR bits definitions. Those were not used. - ERIDR / ERIAR confusion. This one is already in Linus's tree. I'll remove it before the final submission. - make room for different 8168e hw_phy_config and hw_start methods. Signed-off-by: Francois Romieu --- drivers/net/r8169.c | 23 ++++++++++++----------- 1 files changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c index fbd6838..f5b8d52 100644 --- a/drivers/net/r8169.c +++ b/drivers/net/r8169.c @@ -216,7 +216,7 @@ static const struct { [RTL_GIGA_MAC_VER_32] = _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1), [RTL_GIGA_MAC_VER_33] = - _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2) + _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2), }; #undef _R @@ -351,12 +351,12 @@ enum rtl8168_registers { #define ERIAR_WRITE_CMD 0x80000000 #define ERIAR_READ_CMD 0x00000000 #define ERIAR_ADDR_BYTE_ALIGN 4 -#define ERIAR_EXGMAC 0 -#define ERIAR_MSIX 1 -#define ERIAR_ASF 2 #define ERIAR_TYPE_SHIFT 16 -#define ERIAR_BYTEEN 0x0f +#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) +#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) +#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) #define ERIAR_BYTEEN_SHIFT 12 +#define ERIAR_BYTEEN (0x0f << ERIAR_BYTEEN_SHIFT) EPHY_RXER_NUM = 0x7c, OCPDR = 0xb0, /* OCP GPHY access */ #define OCPDR_WRITE_CMD 0x80000000 @@ -749,11 +749,12 @@ static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd) int i; RTL_W8(ERIDR, cmd); - RTL_W32(ERIAR, 0x800010e8); + /* Could 0x10e8 be replaced with (ERIAR_BYTEEN | 0x00e8) ? */ + RTL_W32(ERIAR, ERIAR_WRITE_CMD | ERIAR_EXGMAC | 0x10e8); msleep(2); for (i = 0; i < 5; i++) { udelay(100); - if (!(RTL_R32(ERIDR) & ERIAR_FLAG)) + if (!(RTL_R32(ERIAR) & ERIAR_FLAG)) break; } @@ -2617,7 +2618,7 @@ static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp) rtl_patchphy(tp, 0x0d, 1 << 5); } -static void rtl8168e_hw_phy_config(struct rtl8169_private *tp) +static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp) { static const struct phy_reg phy_reg_init[] = { /* Enable Delay cap */ @@ -2809,7 +2810,7 @@ static void rtl_hw_phy_config(struct net_device *dev) break; case RTL_GIGA_MAC_VER_32: case RTL_GIGA_MAC_VER_33: - rtl8168e_hw_phy_config(tp); + rtl8168e_1_hw_phy_config(tp); break; default: @@ -4148,7 +4149,7 @@ static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev) rtl_enable_clock_request(pdev); } -static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev) +static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev) { static const struct ephy_info e_info_8168e[] = { { 0x00, 0x0200, 0x0100 }, @@ -4271,7 +4272,7 @@ static void rtl_hw_start_8168(struct net_device *dev) case RTL_GIGA_MAC_VER_32: case RTL_GIGA_MAC_VER_33: - rtl_hw_start_8168e(ioaddr, pdev); + rtl_hw_start_8168e_1(ioaddr, pdev); break; default: -- 1.7.4.4