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Date:	Tue, 22 Nov 2011 08:51:59 +0100
From:	Markus Trippelsdorf <markus@...ppelsdorf.de>
To:	Eric Dumazet <eric.dumazet@...il.com>
Cc:	Christoph Lameter <cl@...ux.com>,
	Christian Kujau <lists@...dbynature.de>,
	Benjamin Herrenschmidt <benh@...nel.crashing.org>,
	"Alex,Shi" <alex.shi@...el.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-mm@...ck.org" <linux-mm@...ck.org>,
	Pekka Enberg <penberg@...nel.org>,
	Matt Mackall <mpm@...enic.com>,
	"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
	Tejun Heo <tj@...nel.org>
Subject: Re: WARNING: at mm/slub.c:3357, kernel BUG at mm/slub.c:3413

On 2011.11.22 at 08:48 +0100, Eric Dumazet wrote:
> Le lundi 21 novembre 2011 à 21:18 -0600, Christoph Lameter a écrit :
> 
> > Hmmm... That means that c->page points to page not frozen. Per cpu
> > partial pages are frozen until they are reused or until the partial list
> > is flushed.
> > 
> > Does this ever happen on x86 or only on other platforms? In put_cpu_partial() the
> > this_cpu_cmpxchg really needs really to be irq safe. this_cpu_cmpxchg is
> > only preempt safe.
> > 
> > Index: linux-2.6/mm/slub.c
> > ===================================================================
> > --- linux-2.6.orig/mm/slub.c	2011-11-21 21:15:41.575673204 -0600
> > +++ linux-2.6/mm/slub.c	2011-11-21 21:16:33.442336849 -0600
> > @@ -1969,7 +1969,7 @@
> >  		page->pobjects = pobjects;
> >  		page->next = oldpage;
> > 
> > -	} while (this_cpu_cmpxchg(s->cpu_slab->partial, oldpage, page) != oldpage);
> > +	} while (irqsafe_cpu_cmpxchg(s->cpu_slab->partial, oldpage, page) != oldpage);
> >  	stat(s, CPU_PARTIAL_FREE);
> >  	return pobjects;
> >  }
> > 
> 
> For x86, I wonder if our !X86_FEATURE_CX16 support is correct on SMP
> machines.
> 
> this_cpu_cmpxchg16b_emu() claims to be IRQ safe, but may be buggy...
> 
> Could we have somewhere a NMI handler calling kmalloc() ?
> 
> Please Markus send us :
> 
> cat /proc/cpuinfo
 processor       : 0
 vendor_id       : AuthenticAMD
 cpu family      : 16
 model           : 4
 model name      : AMD Phenom(tm) II X4 955 Processor
 stepping        : 2
 microcode       : 0x10000c6
 cpu MHz         : 800.000
 cache size      : 512 KB
 physical id     : 0
 siblings        : 4
 core id         : 0
 cpu cores       : 4
 apicid          : 0
 initial apicid  : 0
 fpu             : yes
 fpu_exception   : yes
 cpuid level     : 5
 wp              : yes
 flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
 mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext
 fxsr_opt pdpe1gb rdtscp lm 3dnowext 3dnow constant_tsc rep_good nopl
 nonstop_tsc extd_apicid pni monitor cx16 popcnt lahf_lm cmp_legacy svm
 extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit
 wdt npt lbrv svm_lock nrip_save
 bogomips        : 6420.59
 TLB size        : 1024 4K pages
 clflush size    : 64
 cache_alignment : 64
 address sizes   : 48 bits physical, 48 bits virtual
 power management: ts ttp tm stc 100mhzsteps hwpstate
(*4)

-- 
Markus
--
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