netdev - Re: am3359 (cpsw): unable to get gigabit link working (PHY: ICPlus IP1001)

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Message-ID: <CAGm1_ksx7cZaUPOLq3bQcwEchaZY6xM7svb0i+6KGtJYvwU_Gw@mail.gmail.com>
Date:	Thu, 14 Jun 2012 10:28:03 +0200
From:	Yegor Yefremov <yegorslists@...glemail.com>
To:	"N, Mugunthan V" <mugunthanvnm@...com>
Cc:	netdev <netdev@...r.kernel.org>,
	"Chemparathy, Cyril" <cyril@...com>,
	"Govindarajan, Sriramakrishnan" <srk@...com>
Subject: Re: am3359 (cpsw): unable to get gigabit link working (PHY: ICPlus IP1001)

On Thu, Jun 14, 2012 at 10:16 AM, N, Mugunthan V <mugunthanvnm@...com> wrote:
>> -----Original Message-----
>> From: Yegor Yefremov [mailto:yegorslists@...glemail.com]
>> Sent: Wednesday, June 13, 2012 5:59 PM
>> To: netdev
>> Cc: Chemparathy, Cyril; Govindarajan, Sriramakrishnan; N, Mugunthan V
>> Subject: am3359 (cpsw): unable to get gigabit link working (PHY: ICPlus
>> IP1001)
>>
>> I'm using a custom am3359 based board. The first CPSW ports is
>> connected to ICPlus IP1001 phy via RGMII interface. I have no problem
>> with 100mbit link, but as soon as I connect my board to a 1Gbit switch
>> the communication fails. I can see that some data goes on wire, but
>> switch refuses to forward it. I can't receive anything either. Phy
>>. detects 1Gbit link correctly
>>
>> My kernel: https://github.com/koenkooi/linux
>>
>> I also define phy interface as RGMII:
>>
>> static struct cpsw_slave_data am33xx_cpsw_slaves[] = {
>>         {
>>                 .slave_reg_ofs  = 0x208,
>>                 .sliver_reg_ofs = 0xd80,
>>                 .phy_id         = "0:02",
>>                 .phy_if               = PHY_INTERFACE_MODE_RGMII,
>>         },
>>         {
>>                 .slave_reg_ofs  = 0x308,
>>                 .sliver_reg_ofs = 0xdc0,
>>                 .phy_id         = "0:01",
>>         },
>> };
>>
>> As far as I can see in the mainline cpsw driver
>> PHY_INTERFACE_MODE_RGMII will be ignored. Why? In the current driver
>> it sets two bits in mac_control register:
>>
>> if (phy->interface == PHY_INTERFACE_MODE_RGMII) /* RGMII */
>>                         mac_control |= (BIT(15)|BIT(16));
>>
>> Any idea where should I look to solve the problem?
>
> Phy interface in cpsw is always MII, there is an external gasket to convert from MII/GMII to RMII/RGMII. So this is a dead code resides in current driver and will be removed, that's why this part of code is not up streamed.
>
> Can you verify the design/board layout with hardware engineer; also look for cpsw statistics counters for errors.

Thanks for the quick reply.

I have just fixed the problem. In this thread
http://e2e.ti.com/support/dsp/sitara_arm174_microprocessors/f/791/p/172049/685105.aspx#685105
Paul suggests to disable internal delay. I followed his suggestion and
now it works.

#define RGMII_MODE_ENABLE       0x3A

 __raw_writel(RGMII_MODE_ENABLE,
                        AM33XX_CTRL_REGADDR(MAC_MII_SEL));

Yegor
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