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Date: Wed, 22 Aug 2012 10:26:06 -0700 From: Linus Torvalds <torvalds@...ux-foundation.org> To: Ben Hutchings <bhutchings@...arflare.com> Cc: "H. Peter Anvin" <hpa@...or.com>, David Laight <David.Laight@...lab.com>, Benjamin LaHaise <bcrl@...ck.org>, David Miller <davem@...emloft.net>, tglx@...utronix.de, mingo@...hat.com, netdev@...r.kernel.org, linux-net-drivers@...arflare.com, x86@...nel.org Subject: Re: [PATCH 2/3] x86_64: Define 128-bit memory-mapped I/O operations On Wed, Aug 22, 2012 at 10:09 AM, Ben Hutchings <bhutchings@...arflare.com> wrote: > > But the architecture code must be responsible for reporting whether the > host supports it, right? How? It's impossible. As far as the CPU is concerned, the writes happen atomically. Look how you use it: you don't even query dynamically about whether the stuff outside the CPU can handle atomic 128-bit writes. You just assume it at compile-time with an #ifdef. How the hell do you expect that to be able to then say "oh, on this machine the device you are doing the access to is behind an odd PCI->PCIe bridge that will split the access"? Not that we even tend to *know* those kinds of things. It's really esoteric chipset knowledge. I wouldn't even expect it to be necessarily documented in the chipset docs, it *might* be in some NDA'd BIOS writer's guide thing. You don't even seem to realize that things like the Intel FSB was patented and wasn't fully documented by Intel at all? And that's for a bus interface that was used for over a decade from the dominant CPU manufacturer. What do you think happens with odd random chipsets? Who do you expects to know? I *suspect* that 128-bit writes would generally make it intact over PCIe in real life, but I absolutely wouldn't guarantee it on all machines. Exactly because of issues like "what happens with a nVidia host bridge and the old FSB model on older Intel chips?" or "What does the AMD memory pipeline do?". Many CPU cores have 64-bit buses even *internally*, much less externally. Yes, they have atomicity guarantees in their architecture manual, but go look at it: those talk about memory accesses, and they are based on cache coherency (these days - they *used* to be based on certain bus guarantees). The MMIO side is a completely different animal, and is still based on the bus - and nobody documents that, afaik. Linus -- To unsubscribe from this list: send the line "unsubscribe netdev" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
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