netdev - Re: [PATCH v4] lxt PHY: Support for the buggy LXT973 rev A2

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Message-ID: <506070C7.9020507@c-s.fr>
Date:	Mon, 24 Sep 2012 16:40:07 +0200
From:	leroy christophe <christophe.leroy@....fr>
To:	David Laight <David.Laight@...LAB.COM>
CC:	David S Miller <davem@...emloft.net>,
	Richard Cochran <richardcochran@...il.com>,
	netdev@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4] lxt PHY: Support for the buggy LXT973 rev A2


Le 24/09/2012 16:13, David Laight a écrit :
>> This patch adds proper handling of the buggy revision A2 of LXT973 phy, adding
>> precautions linked to ERRATA Item 4:
>>
>> Revision A2 of LXT973 chip randomly returns the contents of the previous even
>> register when you read a odd register regularly
> Does reading the PHY registers involve bit-banging an MII interface?
> If so this code is likely to stall the system for significant
> periods (ready phy registers at all can be a problem).
>
> I know some ethernet mac have hardware blocks for reading MII
> and even polling one MII register for changes.
>
> Maybe some of this code ought to be using async software
> bit-bang - especially when just polling for link status change.
> I'm sure it ought to be possible to do one bit-bang action
> per clock tick instead of spinning for the required delays.
>
> 	David
>
Not sure I understand what you mean. We have been using this code 
without any problem for about 2 years on our Hardware.
It does almost same as genphy_read_status() except that it also reads 
the BMCR register (which is the register preceeding the BMSR) in order 
to detect the unlikely happening of the bug reported by the ERRATA. In 
case it happens (which is really seldom), it does a re-read.
We are not spinning on any delays here.

Christophe
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