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Message-Id: <1349374497-9540-4-git-send-email-monstr@monstr.eu>
Date: Thu, 4 Oct 2012 20:14:50 +0200
From: Michal Simek <monstr@...str.eu>
To: netdev@...r.kernel.org
Cc: linux-kernel@...r.kernel.org, Michal Simek <monstr@...str.eu>,
Wendy Liang <wendy.liang@...alogix.com>,
Nico Augustijn <Nico.Augustijn@...as.nl>,
Anirudha Sarangi <anirudh@...inx.com>,
John Linn <John.Linn@...inx.com>,
Grant Likely <grant.likely@...retlab.ca>,
Rob Herring <rob.herring@...xeda.com>,
"David S. Miller" <davem@...emloft.net>
Subject: [PATCH 04/11] net: axienet: Additional MDIO clock functionality
The MDIO clock was previously hard coded and it is now
calculated thanks to a patch from the community.
Modify the Xilinx patch to get the clock frequency from
the connected AXI bus instead of the CPU.
Currently, the AXI ethernet mdio bus id is set as the mdio device node start
address, but the mdio node don't have a start address. Use the start address
of the AXI ethernet controller which connects to the MDIO bus instead.
Signed-off-by: Wendy Liang <wendy.liang@...alogix.com>
Signed-off-by: Nico Augustijn <Nico.Augustijn@...as.nl>
CC: Anirudha Sarangi <anirudh@...inx.com>
CC: John Linn <John.Linn@...inx.com>
CC: Grant Likely <grant.likely@...retlab.ca>
CC: Rob Herring <rob.herring@...xeda.com>
CC: David S. Miller <davem@...emloft.net>
---
drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c | 76 +++++++++++----------
1 files changed, 40 insertions(+), 36 deletions(-)
diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c b/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c
index e90e1f4..49acc1e 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c
@@ -128,11 +128,11 @@ static int axienet_mdio_write(struct mii_bus *bus, int phy_id, int reg,
int axienet_mdio_setup(struct axienet_local *lp, struct device_node *np)
{
int ret;
- u32 clk_div, host_clock;
- u32 *property_p;
+ u32 clk_div;
struct mii_bus *bus;
struct resource res;
struct device_node *np1;
+ struct device_node *npp = 0; /* the ethernet controller device node */
/* clk_div can be calculated by deriving it from the equation:
* fMDIO = fHOST / ((1 + clk_div) * 2)
@@ -158,41 +158,46 @@ int axienet_mdio_setup(struct axienet_local *lp, struct device_node *np)
* fHOST can be read from the flattened device tree as property
* "clock-frequency" from the CPU
*/
-
- np1 = of_find_node_by_name(NULL, "cpu");
- if (!np1) {
- printk(KERN_WARNING "%s(): Could not find CPU device node.",
- __func__);
- printk(KERN_WARNING "Setting MDIO clock divisor to "
- "default %d\n", DEFAULT_CLOCK_DIVISOR);
- clk_div = DEFAULT_CLOCK_DIVISOR;
- goto issue;
- }
- property_p = (u32 *) of_get_property(np1, "clock-frequency", NULL);
- if (!property_p) {
- printk(KERN_WARNING "%s(): Could not find CPU property: "
- "clock-frequency.", __func__);
- printk(KERN_WARNING "Setting MDIO clock divisor to "
- "default %d\n", DEFAULT_CLOCK_DIVISOR);
+ np1 = of_get_parent(lp->phy_node);
+ if (np1)
+ npp = of_get_parent(np1);
+ if (!npp) {
+ dev_warn(lp->dev,
+ "Could not find ethernet controller device node.");
+ dev_warn(lp->dev, "Setting MDIO clock divisor to default %d\n",
+ DEFAULT_CLOCK_DIVISOR);
clk_div = DEFAULT_CLOCK_DIVISOR;
- goto issue;
+ } else {
+ u32 *property_p;
+
+ property_p = (uint32_t *)of_get_property(npp,
+ "clock-frequency", NULL);
+ if (!property_p) {
+ dev_warn(lp->dev, "Could not find clock ethernet " \
+ "controller property.");
+ dev_warn(lp->dev,
+ "Setting MDIO clock divisor to default %d\n",
+ DEFAULT_CLOCK_DIVISOR);
+ clk_div = DEFAULT_CLOCK_DIVISOR;
+ } else {
+ u32 host_clock = be32_to_cpup(property_p);
+
+ clk_div = (host_clock / (MAX_MDIO_FREQ * 2)) - 1;
+
+ /* If there is any remainder from the division of
+ * fHOST / (MAX_MDIO_FREQ * 2), then we need to add 1
+ * to the clock divisor or we will surely be
+ * above 2.5 MHz */
+ if (host_clock % (MAX_MDIO_FREQ * 2))
+ clk_div++;
+ dev_dbg(lp->dev, "Setting MDIO clock divisor to %u " \
+ "based on %u Hz host clock.\n",
+ clk_div, host_clock);
+ }
}
- host_clock = be32_to_cpup(property_p);
- clk_div = (host_clock / (MAX_MDIO_FREQ * 2)) - 1;
- /* If there is any remainder from the division of
- * fHOST / (MAX_MDIO_FREQ * 2), then we need to add
- * 1 to the clock divisor or we will surely be above 2.5 MHz */
- if (host_clock % (MAX_MDIO_FREQ * 2))
- clk_div++;
-
- printk(KERN_DEBUG "%s(): Setting MDIO clock divisor to %u based "
- "on %u Hz host clock.\n", __func__, clk_div, host_clock);
-
- of_node_put(np1);
-issue:
- axienet_iow(lp, XAE_MDIO_MC_OFFSET,
- (((u32) clk_div) | XAE_MDIO_MC_MDIOEN_MASK));
+ axienet_iow(lp, XAE_MDIO_MC_OFFSET, (((u32)clk_div) |
+ XAE_MDIO_MC_MDIOEN_MASK));
ret = axienet_mdio_wait_until_ready(lp);
if (ret < 0)
@@ -202,8 +207,7 @@ issue:
if (!bus)
return -ENOMEM;
- np1 = of_get_parent(lp->phy_node);
- of_address_to_resource(np1, 0, &res);
+ of_address_to_resource(npp, 0, &res);
snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx",
(unsigned long long) res.start);
--
1.7.0.4
--
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