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Message-ID: <CAMAG_eeeQrvyKizbHb2hkRMV+MiV7u-G+LvSAs3C3NDdGzT4Eg@mail.gmail.com>
Date: Sun, 3 Feb 2013 23:00:30 +0200
From: saeed bishara <saeed.bishara@...il.com>
To: Eric Dumazet <eric.dumazet@...il.com>
Cc: ling.ma.program@...il.com, David Miller <davem@...emloft.net>,
netdev <netdev@...r.kernel.org>,
Maciej Żenczykowski <maze@...gle.com>
Subject: Re: [PATCH v2 net-next] inet: Get critical word in first 64bit of
cache line
On Sat, Feb 2, 2013 at 5:03 PM, Eric Dumazet <eric.dumazet@...il.com> wrote:
> From: Ma Ling <ling.ma.program@...il.com>
>
> In order to reduce memory latency when last level cache miss occurs,
> modern CPUs i.e. x86 and arm introduced Critical Word First(CWF) or
> Early Restart(ER) to get data ASAP. For CWF if critical word is first
> member
> in cache line, memory feed CPU with critical word, then fill others
> data in cache line one by one, otherwise after critical word it must
> cost more cycle to fill the remaining cache line. For Early First CPU
> will restart until critical word in cache line reaches.
>
> Hash value is critical word, so in this patch we place it as first
> member in cache line (sock address is cache-line aligned), and it is
> also good for Early Restart platform as well .
I think the description of this patch doen't make sense. the purpose
of CWF hardware feature is to release the sw from moving critical word
as first member of the cache.
that's ofcourse depends on how you define the CWF, but at least
according to http://lwn.net/Articles/252125/ and here
https://github.com/jamie-allen/cpu_caches/blob/master/preso/presentation.md
the CWF means the hw will do the job.
so I think the patch maybe usefull (1) for system that doesn't have
CWF, (2) CWF may not totaly eliminate the additional latency. this is
of course a prediction as you see.
saeed
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