netdev - Re: [PATCH 1/5 net-next] tg3: Add 57766 device support.

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Date:	Thu, 14 Feb 2013 14:25:50 -0800
From:	Joe Perches <joe@...ches.com>
To:	Michael Chan <mchan@...adcom.com>,
	Matt Carlson <mcarlson@...adcom.com>
Cc:	davem@...emloft.net, netdev@...r.kernel.org, nsujir@...adcom.com
Subject: Re: [PATCH 1/5 net-next] tg3: Add 57766 device support.

On Thu, 2013-02-14 at 14:13 -0800, Michael Chan wrote:
> From: Matt Carlson <mcarlson@...adcom.com>
> 
> The patch also adds a couple of fixes
> 
>  - For the 57766, bootcode needs to setup the PCIE Fast Training
>    Sequence (FTS) value to prevent transmit hangs. Unfortunately, it
>    does not have enough room in the selfboot case (i.e. devices with no
>    NVRAM).  The driver needs to implement this.
[]
> diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
[]
> @@ -9179,7 +9180,14 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
>  		}
>  
>  		if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) {
> -			u32 grc_mode = tr32(GRC_MODE);
> +			u32 grc_mode;
> +
> +			/* Fix transmit hangs */
> +			val = tr32(TG3_CPMU_PADRNG_CTL);
> +			val |= TG3_CPMU_PADRNG_CTL_RDIV2;
> +			tw32(TG3_CPMU_PADRNG_CTL, val);
> +

This seems to write this val to more devices than just
a 57766.  Intentional?

> +			grc_mode = tr32(GRC_MODE);
>  
>  			/* Access the lower 1K of DL PCIE block registers. */
>  			val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;


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