netdev - Re: [PATCH] net-packet: tx timestamping on tpacket ring

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Message-ID: <CA+FuTSedhCD2_uWL17bNSjDG5+3RhagkjFCVMcOx9G4H7byi2g@mail.gmail.com>
Date:	Mon, 15 Apr 2013 13:08:52 -0400
From:	Willem de Bruijn <willemb@...gle.com>
To:	David Laight <David.Laight@...lab.com>
Cc:	Daniel Borkmann <dborkman@...hat.com>,
	Paul Chavent <paul.chavent@...ra.fr>,
	Richard Cochran <richardcochran@...il.com>,
	Eric Dumazet <edumazet@...gle.com>,
	daniel.borkmann@....ee.ethz.ch, xemul@...allels.com,
	ebiederm@...ssion.com, netdev@...r.kernel.org
Subject: Re: [PATCH] net-packet: tx timestamping on tpacket ring

On Mon, Apr 15, 2013 at 5:45 AM, David Laight <David.Laight@...lab.com> wrote:
>> > +   case TPACKET_V1:
>> > +           h1 = frame;
>> > +           h1->tp_sec = ts.tv_sec;
>> > +           h1->tp_usec = ts.tv_nsec / NSEC_PER_USEC;
>> > +
>> > +           flush_dcache_page(pgv_to_page(&h1->tp_sec));
>> > +           flush_dcache_page(pgv_to_page(&h1->tp_usec));
>>
>> Hmm, not sure, but could we also flush the dcache only once?
>
> If it isn't a silly question, why is the dcache being flushed
> here at all?

I'm not an expert on this, but have a look at
Documentation/cachetlb.txt, specifically the bits on this function and
the discussion of aliasing: on virtually indexed cache architectures,
the same physical address may be cached in multiple cachelines at the
same time. If I understand correctly, updating the kernel logical
address does not necessarily invalidate the user virtual cacheline for
the same physical memory.

>         David
>
>
>
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